Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3112943

1

T3

1

T5

163

T6

257

auto[1]

26590

1

T12

43

T16

206

T30

51

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

796012

1

T3

1

T5

163

T6

1

auto[1]

2343521

1

T6

256

T12

12747

T16

5186

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	598325	1			T3	1		T5	25		T6	257
auto[524288:1048575]	364442	1			T5	100		T12	362		T16	538
auto[1048576:1572863]	364386	1			T12	1131		T16	12		T30	280
auto[1572864:2097151]	401288	1			T5	3		T12	4333		T16	1032
auto[2097152:2621439]	416803	1			T12	14		T13	26		T16	260
auto[2621440:3145727]	343212	1			T12	1235		T16	32		T48	2
auto[3145728:3670015]	316081	1			T5	35		T12	2224		T13	98
auto[3670016:4194303]	334996	1			T12	2754		T16	146		T48	11

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2376172

1

T3

1

T5

8

T6

257

auto[1]

763361

1

T5

155

T12

1

T13

189

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2735550

1

T3

1

T5

163

T6

257

auto[1]

403983

1

T12

6079

T16

2337

T48

19

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	169739	1			T3	1		T5	25		T6	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	380496	1			T6	256		T12	761		T16	518
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	93214	1			T5	100		T12	2		T16	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	231665	1			T12	4		T16	515		T30	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85064	1			T12	7		T16	4		T30	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	228664	1			T12	1121		T16	1		T30	258
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	88487	1			T5	3		T12	8		T16	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	247432	1			T12	640		T16	1024		T30	6579
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	110259	1			T12	1		T13	26		T16	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	240743	1			T12	1		T16	257		T30	514
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	87614	1			T12	11		T16	6		T30	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	210606	1			T12	1205		T16	2		T30	2597
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	68532	1			T5	35		T12	10		T13	98
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	189079	1			T12	2207		T16	257		T30	11
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	70334	1			T12	3		T16	4		T30	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	211189	1			T12	729		T16	142		T24	825
auto[0]	auto[1]	auto[0:524287]	auto[0]	2867	1			T16	4		T48	6		T30	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	41147	1			T16	2278		T44	642		T86	513
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2053	1			T49	22		T24	2		T26	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	33810	1			T12	356		T26	201		T37	1544
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	592	1			T24	27		T26	4		T37	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46930	1			T24	2625		T37	644		T41	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	4894	1			T12	4		T24	9		T26	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57339	1			T12	3681		T24	514		T26	4761
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	984	1			T12	1		T49	13		T24	34
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	61662	1			T12	1		T24	3479		T37	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1565	1			T12	3		T16	2		T48	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	40259	1			T12	2		T16	1		T26	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1333	1			T12	2		T49	5		T26	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53860	1			T12	2		T26	384		T37	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	4841	1			T12	4		T48	11		T49	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45690	1			T12	2011		T26	1		T44	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	453	1			T12	2		T16	6		T30	5
auto[1]	auto[0]	auto[0:524287]	auto[1]	2811	1			T12	4		T16	66		T30	16
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	357	1			T16	3		T30	1		T24	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2933	1			T16	14		T37	19		T44	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	428	1			T12	3		T16	1		T30	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2231	1			T16	6		T30	12		T37	35
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	405	1			T16	1		T49	5		T24	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2284	1			T16	2		T49	512		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	325	1			T12	1		T30	2		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2202	1			T12	7		T30	7		T26	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	349	1			T12	3		T16	1		T30	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2201	1			T12	5		T16	16		T30	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	337	1			T16	1		T30	2		T24	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2695	1			T16	37		T30	2		T18	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	389	1			T12	2		T49	3		T24	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2033	1			T12	4		T18	6		T44	33
auto[1]	auto[1]	auto[0:524287]	auto[0]	66	1			T16	1		T44	2		T45	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	746	1			T16	47		T45	7		T50	8
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	53	1			T37	2		T86	1		T50	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	357	1			T37	5		T86	27		T50	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	84	1			T161	1		T182	2		T133	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	393	1			T182	19		T133	22		T150	16
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	97	1			T26	2		T37	1		T18	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	350	1			T26	5		T18	1		T50	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	93	1			T12	1		T49	4		T24	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	535	1			T12	1		T37	5		T50	37
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	80	1			T12	2		T16	1		T26	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	538	1			T12	4		T16	3		T26	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	54	1			T12	2		T162	5		T182	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	191	1			T12	1		T162	10		T182	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	70	1			T12	1		T49	3		T26	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	450	1			T26	1		T86	1		T50	13

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1965118	1			T3	1		T5	8		T6	257
auto[0]	auto[0]	auto[1]	747999	1			T5	155		T13	189		T16	4
auto[0]	auto[1]	auto[0]	385138	1			T12	6067		T16	2283		T48	19
auto[0]	auto[1]	auto[1]	14688	1			T16	2		T37	1		T155	1
auto[1]	auto[0]	auto[0]	21866	1			T12	31		T16	150		T30	51
auto[1]	auto[0]	auto[1]	567	1			T16	4		T49	2		T24	8
auto[1]	auto[1]	auto[0]	4050	1			T12	11		T16	51		T49	5
auto[1]	auto[1]	auto[1]	107	1			T12	1		T16	1		T49	2