Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2597308	1			T1	985		T2	1		T3	1
all_pins[1]	2597308	1			T1	985		T2	1		T3	1
all_pins[2]	2597308	1			T1	985		T2	1		T3	1
all_pins[3]	2597308	1			T1	985		T2	1		T3	1
all_pins[4]	2597308	1			T1	985		T2	1		T3	1
all_pins[5]	2597308	1			T1	985		T2	1		T3	1
all_pins[6]	2597308	1			T1	985		T2	1		T3	1
all_pins[7]	2597308	1			T1	985		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20730586	1			T1	7880		T2	8		T3	8
values[0x1]	47878	1			T17	15		T18	43		T19	9
transitions[0x0=>0x1]	46504	1			T17	12		T18	30		T19	9
transitions[0x1=>0x0]	46518	1			T17	12		T18	31		T19	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2596509	1			T1	985		T2	1		T3	1
all_pins[0]	values[0x1]	799	1			T17	2		T18	6		T20	67
all_pins[0]	transitions[0x0=>0x1]	416	1			T17	2		T18	5		T20	26
all_pins[0]	transitions[0x1=>0x0]	243	1			T17	2		T18	6		T19	2
all_pins[1]	values[0x0]	2596682	1			T1	985		T2	1		T3	1
all_pins[1]	values[0x1]	626	1			T17	2		T18	7		T19	2
all_pins[1]	transitions[0x0=>0x1]	467	1			T17	2		T18	6		T19	2
all_pins[1]	transitions[0x1=>0x0]	144	1			T17	3		T18	4		T19	1
all_pins[2]	values[0x0]	2597005	1			T1	985		T2	1		T3	1
all_pins[2]	values[0x1]	303	1			T17	3		T18	5		T19	1
all_pins[2]	transitions[0x0=>0x1]	261	1			T17	1		T18	4		T19	1
all_pins[2]	transitions[0x1=>0x0]	154	1			T17	1		T18	2		T20	2
all_pins[3]	values[0x0]	2597112	1			T1	985		T2	1		T3	1
all_pins[3]	values[0x1]	196	1			T17	3		T18	3		T20	3
all_pins[3]	transitions[0x0=>0x1]	146	1			T17	3		T18	2		T20	3
all_pins[3]	transitions[0x1=>0x0]	120	1			T18	4		T19	1		T21	5
all_pins[4]	values[0x0]	2597138	1			T1	985		T2	1		T3	1
all_pins[4]	values[0x1]	170	1			T18	5		T19	1		T21	6
all_pins[4]	transitions[0x0=>0x1]	132	1			T18	2		T19	1		T21	5
all_pins[4]	transitions[0x1=>0x0]	1749	1			T17	1		T18	1		T19	1
all_pins[5]	values[0x0]	2595521	1			T1	985		T2	1		T3	1
all_pins[5]	values[0x1]	1787	1			T17	1		T18	4		T19	1
all_pins[5]	transitions[0x0=>0x1]	1181	1			T18	2		T19	1		T20	3
all_pins[5]	transitions[0x1=>0x0]	43213	1			T17	2		T18	3		T19	3
all_pins[6]	values[0x0]	2553489	1			T1	985		T2	1		T3	1
all_pins[6]	values[0x1]	43819	1			T17	3		T18	5		T19	3
all_pins[6]	transitions[0x0=>0x1]	43777	1			T17	3		T18	4		T19	3
all_pins[6]	transitions[0x1=>0x0]	136	1			T17	1		T18	7		T19	1
all_pins[7]	values[0x0]	2597130	1			T1	985		T2	1		T3	1
all_pins[7]	values[0x1]	178	1			T17	1		T18	8		T19	1
all_pins[7]	transitions[0x0=>0x1]	124	1			T17	1		T18	5		T19	1
all_pins[7]	transitions[0x1=>0x0]	759	1			T17	2		T18	4		T20	66