Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481

1

T5

8

T6

24

T7

6

auto[1]

12613

1

T3

20

T16

166

T30

113

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3783	1			T16	27		T30	24		T41	20
values[1]	3485	1			T15	2		T30	20		T49	20
values[2]	4230	1			T16	77		T49	40		T50	111
values[3]	3901	1			T3	20		T14	6		T30	20
values[4]	4056	1			T6	24		T16	118		T30	28
values[5]	4092	1			T5	8		T7	6		T30	39
values[6]	3989	1			T16	121		T48	14		T30	80
values[7]	3558	1			T16	23		T51	20		T193	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3605	1			T41	20		T109	16		T192	10
values[1]	4097	1			T16	118		T30	20		T49	20
values[2]	3996	1			T5	8		T16	178		T49	20
values[3]	4082	1			T3	20		T30	44		T49	20
values[4]	3959	1			T7	6		T15	2		T16	27
values[5]	3757	1			T14	6		T16	20		T30	65
values[6]	4056	1			T6	24		T30	48		T41	21
values[7]	3542	1			T16	23		T48	14		T30	34

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	199	1			T41	13		T54	13		T222	16
auto[0]	values[0]	values[1]	240	1			T54	13		T160	6		T207	27
auto[0]	values[0]	values[2]	278	1			T223	2		T22	52		T33	17
auto[0]	values[0]	values[3]	411	1			T30	16		T87	61		T158	97
auto[0]	values[0]	values[4]	247	1			T16	14		T54	14		T22	40
auto[0]	values[0]	values[5]	390	1			T154	18		T50	34		T22	61
auto[0]	values[0]	values[6]	254	1			T20	25		T22	16		T133	18
auto[0]	values[0]	values[7]	209	1			T53	12		T191	23		T187	11
auto[0]	values[1]	values[0]	192	1			T208	26		T22	18		T224	4
auto[0]	values[1]	values[1]	257	1			T49	11		T108	8		T198	7
auto[0]	values[1]	values[2]	269	1			T50	9		T225	4		T226	16
auto[0]	values[1]	values[3]	265	1			T30	10		T41	5		T87	11
auto[0]	values[1]	values[4]	321	1			T15	2		T23	18		T212	14
auto[0]	values[1]	values[5]	155	1			T41	15		T20	37		T187	12
auto[0]	values[1]	values[6]	302	1			T53	13		T54	12		T208	13
auto[0]	values[1]	values[7]	113	1			T160	12		T22	11		T188	14
auto[0]	values[2]	values[0]	292	1			T54	8		T160	14		T204	4
auto[0]	values[2]	values[1]	553	1			T20	6		T182	48		T186	17
auto[0]	values[2]	values[2]	308	1			T16	70		T49	10		T54	13
auto[0]	values[2]	values[3]	498	1			T49	9		T99	14		T160	4
auto[0]	values[2]	values[4]	337	1			T50	83		T99	26		T209	72
auto[0]	values[2]	values[5]	198	1			T50	9		T53	10		T160	11
auto[0]	values[2]	values[6]	303	1			T53	7		T159	13		T176	68
auto[0]	values[2]	values[7]	279	1			T214	16		T20	18		T22	28
auto[0]	values[3]	values[0]	302	1			T209	47		T188	11		T132	11
auto[0]	values[3]	values[1]	241	1			T95	14		T33	40		T133	12
auto[0]	values[3]	values[2]	201	1			T20	25		T227	2		T188	15
auto[0]	values[3]	values[3]	367	1			T160	9		T176	50		T20	24
auto[0]	values[3]	values[4]	370	1			T54	13		T160	10		T22	20
auto[0]	values[3]	values[5]	303	1			T14	6		T20	14		T179	22
auto[0]	values[3]	values[6]	398	1			T30	10		T228	4		T158	14
auto[0]	values[3]	values[7]	160	1			T49	15		T53	13		T54	16
auto[0]	values[4]	values[0]	240	1			T192	10		T54	12		T87	8
auto[0]	values[4]	values[1]	541	1			T16	69		T160	9		T20	24
auto[0]	values[4]	values[2]	421	1			T206	20		T208	10		T22	7
auto[0]	values[4]	values[3]	221	1			T164	16		T205	73		T229	17
auto[0]	values[4]	values[4]	198	1			T179	8		T187	13		T230	24
auto[0]	values[4]	values[5]	201	1			T55	11		T50	12		T53	6
auto[0]	values[4]	values[6]	452	1			T6	24		T30	12		T41	18
auto[0]	values[4]	values[7]	156	1			T16	6		T50	12		T188	11
auto[0]	values[5]	values[0]	478	1			T87	9		T20	9		T188	48
auto[0]	values[5]	values[1]	291	1			T99	12		T231	12		T188	15
auto[0]	values[5]	values[2]	276	1			T5	8		T160	6		T179	72
auto[0]	values[5]	values[3]	311	1			T53	10		T133	12		T36	11
auto[0]	values[5]	values[4]	322	1			T7	6		T54	9		T20	14
auto[0]	values[5]	values[5]	286	1			T30	14		T50	6		T53	11
auto[0]	values[5]	values[6]	151	1			T50	35		T200	18		T232	9
auto[0]	values[5]	values[7]	380	1			T50	25		T53	13		T233	7
auto[0]	values[6]	values[0]	256	1			T20	13		T132	24		T133	7
auto[0]	values[6]	values[1]	231	1			T30	10		T20	22		T22	43
auto[0]	values[6]	values[2]	251	1			T16	15		T20	41		T22	10
auto[0]	values[6]	values[3]	195	1			T50	62		T234	12		T184	17
auto[0]	values[6]	values[4]	293	1			T221	18		T182	10		T185	13
auto[0]	values[6]	values[5]	426	1			T16	12		T30	15		T94	14
auto[0]	values[6]	values[6]	292	1			T176	14		T182	21		T133	16
auto[0]	values[6]	values[7]	247	1			T48	14		T30	11		T155	4
auto[0]	values[7]	values[0]	167	1			T183	17		T188	12		T33	10
auto[0]	values[7]	values[1]	216	1			T16	14		T87	15		T188	12
auto[0]	values[7]	values[2]	217	1			T50	11		T87	79		T22	11
auto[0]	values[7]	values[3]	356	1			T158	11		T33	10		T133	5
auto[0]	values[7]	values[4]	308	1			T177	6		T212	69		T87	10
auto[0]	values[7]	values[5]	321	1			T38	22		T53	10		T87	9
auto[0]	values[7]	values[6]	320	1			T158	11		T180	8		T235	8
auto[0]	values[7]	values[7]	248	1			T193	10		T160	12		T36	12
auto[1]	values[0]	values[0]	216	1			T41	7		T54	7		T207	7
auto[1]	values[0]	values[1]	241	1			T54	7		T160	14		T207	11
auto[1]	values[0]	values[2]	118	1			T22	10		T33	4		T236	10
auto[1]	values[0]	values[3]	184	1			T30	8		T87	7		T158	20
auto[1]	values[0]	values[4]	191	1			T16	13		T54	6		T22	10
auto[1]	values[0]	values[5]	184	1			T50	9		T22	27		T132	11
auto[1]	values[0]	values[6]	151	1			T20	20		T22	4		T133	4
auto[1]	values[0]	values[7]	270	1			T53	8		T191	39		T187	9
auto[1]	values[1]	values[0]	284	1			T208	203		T22	8		T33	3
auto[1]	values[1]	values[1]	131	1			T49	9		T198	15		T237	13
auto[1]	values[1]	values[2]	183	1			T52	8		T50	58		T36	10
auto[1]	values[1]	values[3]	237	1			T30	10		T41	25		T87	64
auto[1]	values[1]	values[4]	236	1			T212	15		T160	13		T179	10
auto[1]	values[1]	values[5]	142	1			T41	12		T20	8		T187	8
auto[1]	values[1]	values[6]	311	1			T53	7		T54	8		T208	99
auto[1]	values[1]	values[7]	87	1			T160	8		T22	9		T188	6
auto[1]	values[2]	values[0]	138	1			T54	12		T160	6		T176	30
auto[1]	values[2]	values[1]	165	1			T20	14		T182	8		T238	8
auto[1]	values[2]	values[2]	231	1			T16	7		T49	10		T54	7
auto[1]	values[2]	values[3]	151	1			T49	11		T99	6		T160	16
auto[1]	values[2]	values[4]	163	1			T50	8		T99	14		T209	9
auto[1]	values[2]	values[5]	173	1			T50	11		T53	10		T160	9
auto[1]	values[2]	values[6]	235	1			T53	13		T159	36		T176	36
auto[1]	values[2]	values[7]	206	1			T20	24		T22	11		T33	10
auto[1]	values[3]	values[0]	121	1			T209	9		T188	9		T132	9
auto[1]	values[3]	values[1]	234	1			T33	6		T133	8		T205	22
auto[1]	values[3]	values[2]	260	1			T20	11		T188	5		T132	7
auto[1]	values[3]	values[3]	237	1			T3	20		T160	11		T176	6
auto[1]	values[3]	values[4]	179	1			T54	7		T160	10		T22	10
auto[1]	values[3]	values[5]	153	1			T20	9		T179	24		T239	8
auto[1]	values[3]	values[6]	214	1			T30	10		T158	6		T182	11
auto[1]	values[3]	values[7]	161	1			T49	5		T53	7		T54	4
auto[1]	values[4]	values[0]	172	1			T109	16		T54	8		T87	12
auto[1]	values[4]	values[1]	208	1			T16	26		T160	11		T20	41
auto[1]	values[4]	values[2]	281	1			T208	22		T22	15		T182	7
auto[1]	values[4]	values[3]	107	1			T240	18		T205	11		T229	9
auto[1]	values[4]	values[4]	205	1			T179	12		T187	7		T241	12
auto[1]	values[4]	values[5]	293	1			T50	17		T53	14		T87	13
auto[1]	values[4]	values[6]	241	1			T30	16		T41	3		T158	8
auto[1]	values[4]	values[7]	119	1			T16	17		T50	8		T188	9
auto[1]	values[5]	values[0]	167	1			T87	32		T20	17		T188	7
auto[1]	values[5]	values[1]	199	1			T242	2		T99	8		T188	5
auto[1]	values[5]	values[2]	151	1			T160	14		T179	6		T133	3
auto[1]	values[5]	values[3]	242	1			T53	10		T133	39		T36	9
auto[1]	values[5]	values[4]	191	1			T54	11		T20	13		T22	14
auto[1]	values[5]	values[5]	154	1			T30	25		T50	16		T53	9
auto[1]	values[5]	values[6]	83	1			T50	34		T232	14		T243	9
auto[1]	values[5]	values[7]	410	1			T50	9		T53	7		T233	18
auto[1]	values[6]	values[0]	290	1			T20	7		T199	12		T132	11
auto[1]	values[6]	values[1]	207	1			T30	10		T20	8		T22	10
auto[1]	values[6]	values[2]	292	1			T16	86		T20	15		T22	52
auto[1]	values[6]	values[3]	105	1			T50	12		T234	8		T184	3
auto[1]	values[6]	values[4]	108	1			T182	11		T185	7		T205	5
auto[1]	values[6]	values[5]	184	1			T16	8		T30	11		T50	11
auto[1]	values[6]	values[6]	240	1			T176	6		T182	109		T133	4
auto[1]	values[6]	values[7]	372	1			T30	23		T50	89		T216	20
auto[1]	values[7]	values[0]	91	1			T188	8		T33	10		T244	7
auto[1]	values[7]	values[1]	142	1			T16	9		T51	20		T87	7
auto[1]	values[7]	values[2]	259	1			T50	83		T87	8		T22	28
auto[1]	values[7]	values[3]	195	1			T158	9		T33	10		T133	15
auto[1]	values[7]	values[4]	290	1			T212	9		T87	25		T160	9
auto[1]	values[7]	values[5]	194	1			T53	10		T87	11		T182	4
auto[1]	values[7]	values[6]	109	1			T158	28		T245	4		T246	6
auto[1]	values[7]	values[7]	125	1			T160	8		T36	22		T186	29