Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	448	1			T5	2		T16	1		T30	1
auto[ReadAddrCrossIntoMailbox]	295	1			T16	5		T30	5		T95	2
auto[ReadAddrCrossOutOfMailbox]	274	1			T16	2		T30	1		T49	2
auto[ReadAddrCrossAllMailbox]	225	1			T16	3		T30	2		T49	1
auto[ReadAddrOutsideMailbox]	3568	1			T3	4		T6	4		T14	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2298

1

T3

2

T5

1

T6

2

auto[1]

2512

1

T3

2

T5

1

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	840	1			T3	4		T5	2		T6	2
read_ops[0x0b]	787	1			T16	9		T30	7		T51	2
read_ops[0x3b]	842	1			T14	2		T16	1		T30	10
read_ops[0x6b]	737	1			T16	8		T30	3		T51	4
read_ops[0xbb]	781	1			T16	5		T30	5		T49	6
read_ops[0xeb]	823	1			T6	2		T16	9		T30	8

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T5	1		T164	2		T50	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T5	1		T30	1		T164	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T30	1		T208	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T50	2		T160	1		T20	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T164	1		T50	2		T87	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T164	1		T50	2		T87	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T164	1		T225	1		T247	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T164	1		T225	1		T160	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T3	2		T6	1		T14	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T3	2		T6	1		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T95	2		T50	1		T192	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T95	2		T192	1		T54	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T16	1		T50	1		T158	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T16	1		T30	2		T22	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T208	1		T158	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T16	2		T30	1		T50	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T95	2		T87	1		T22	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T95	2		T22	1		T187	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T16	2		T30	4		T51	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T16	3		T51	1		T193	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T49	1		T95	1		T228	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T95	1		T228	2		T235	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T95	1		T50	1		T87	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T95	1		T54	2		T160	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	11	1			T50	1		T54	1		T87	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T49	1		T50	1		T53	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T188	1		T233	1		T237	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T30	1		T22	1		T182	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T14	1		T30	2		T49	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T14	1		T16	1		T30	7
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T16	1		T41	1		T50	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T208	1		T176	1		T235	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T87	1		T160	1		T22	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T50	1		T208	1		T188	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T54	2		T247	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T247	1		T33	1		T185	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T16	1		T164	1		T176	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T164	1		T20	1		T205	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T16	1		T30	3		T51	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T16	5		T51	2		T164	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T248	1		T20	1		T133	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T50	1		T54	1		T208	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T20	1		T22	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T87	2		T20	2		T182	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T132	1		T241	1		T249	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T208	1		T20	2		T22	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T164	1		T50	2		T54	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T16	1		T30	1		T49	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T16	2		T30	1		T49	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T16	2		T30	3		T49	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T192	1		T176	1		T22	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T192	1		T99	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T30	2		T53	1		T176	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T16	3		T158	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T49	1		T87	1		T160	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T50	1		T20	2		T22	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T50	1		T176	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T16	1		T176	1		T20	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T6	1		T16	1		T30	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T6	1		T16	4		T30	3