Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3410	1			T48	14		T51	20		T155	4
values[1]	4012	1			T5	8		T30	67		T49	20
values[2]	3665	1			T16	43		T30	26		T164	16
values[3]	3877	1			T16	27		T23	18		T41	48
values[4]	4030	1			T16	158		T30	54		T41	20
values[5]	4026	1			T30	20		T49	20		T94	14
values[6]	4099	1			T3	20		T14	6		T15	2
values[7]	3975	1			T6	24		T7	6		T16	37

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4135	1			T14	6		T48	14		T30	20
values[1]	4430	1			T6	24		T49	20		T164	16
values[2]	3464	1			T16	121		T30	54		T49	20
values[3]	3654	1			T15	2		T16	77		T30	20
values[4]	3803	1			T7	6		T16	58		T49	20
values[5]	3752	1			T5	8		T16	23		T30	39
values[6]	4082	1			T16	64		T41	30		T50	83
values[7]	3774	1			T3	20		T16	23		T30	78

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30229

1

T3

10

T5

8

T6

24

auto[1]

865

1

T3

10

T16

3

T30

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	292	1			T48	14		T248	16		T159	49
auto[0]	values[0]	values[1]	413	1			T22	60		T236	26		T250	20
auto[0]	values[0]	values[2]	313	1			T188	20		T251	20		T205	81
auto[0]	values[0]	values[3]	412	1			T51	18		T188	20		T132	20
auto[0]	values[0]	values[4]	506	1			T155	4		T176	17		T20	124
auto[0]	values[0]	values[5]	462	1			T160	18		T223	2		T245	4
auto[0]	values[0]	values[6]	414	1			T54	17		T99	19		T208	20
auto[0]	values[0]	values[7]	495	1			T160	20		T22	37		T191	18
auto[0]	values[1]	values[0]	627	1			T49	19		T193	10		T50	20
auto[0]	values[1]	values[1]	532	1			T199	12		T33	63		T186	20
auto[0]	values[1]	values[2]	659	1			T30	27		T53	39		T160	18
auto[0]	values[1]	values[3]	193	1			T187	19		T252	14		T201	20
auto[0]	values[1]	values[4]	358	1			T52	6		T99	20		T22	20
auto[0]	values[1]	values[5]	452	1			T5	8		T30	38		T50	22
auto[0]	values[1]	values[6]	645	1			T41	28		T54	20		T231	12
auto[0]	values[1]	values[7]	444	1			T53	18		T160	19		T22	43
auto[0]	values[2]	values[0]	416	1			T20	35		T187	18		T185	20
auto[0]	values[2]	values[1]	504	1			T164	16		T209	55		T158	57
auto[0]	values[2]	values[2]	496	1			T16	20		T30	25		T20	66
auto[0]	values[2]	values[3]	440	1			T212	29		T20	23		T182	20
auto[0]	values[2]	values[4]	405	1			T87	32		T160	18		T132	26
auto[0]	values[2]	values[5]	130	1			T16	21		T55	11		T36	20
auto[0]	values[2]	values[6]	272	1			T54	19		T20	45		T33	18
auto[0]	values[2]	values[7]	879	1			T109	16		T154	18		T54	20
auto[0]	values[3]	values[0]	613	1			T108	8		T99	20		T33	49
auto[0]	values[3]	values[1]	450	1			T50	41		T87	41		T208	112
auto[0]	values[3]	values[2]	541	1			T41	24		T87	67		T176	29
auto[0]	values[3]	values[3]	499	1			T253	2		T182	18		T186	22
auto[0]	values[3]	values[4]	454	1			T50	65		T54	20		T20	21
auto[0]	values[3]	values[5]	544	1			T23	18		T41	20		T50	27
auto[0]	values[3]	values[6]	292	1			T16	27		T50	20		T20	20
auto[0]	values[3]	values[7]	389	1			T50	71		T54	20		T33	65
auto[0]	values[4]	values[0]	347	1			T242	2		T158	20		T176	19
auto[0]	values[4]	values[1]	364	1			T239	8		T254	45		T236	19
auto[0]	values[4]	values[2]	180	1			T83	20		T198	19		T249	19
auto[0]	values[4]	values[3]	672	1			T16	77		T30	20		T41	19
auto[0]	values[4]	values[4]	406	1			T16	58		T54	16		T177	6
auto[0]	values[4]	values[5]	654	1			T208	180		T227	2		T22	39
auto[0]	values[4]	values[6]	636	1			T50	34		T53	20		T20	20
auto[0]	values[4]	values[7]	644	1			T16	23		T30	31		T50	42
auto[0]	values[5]	values[0]	449	1			T30	20		T226	16		T160	20
auto[0]	values[5]	values[1]	871	1			T50	91		T53	38		T160	19
auto[0]	values[5]	values[2]	383	1			T50	20		T87	20		T22	25
auto[0]	values[5]	values[3]	387	1			T22	31		T182	35		T179	20
auto[0]	values[5]	values[4]	628	1			T49	17		T87	22		T255	2
auto[0]	values[5]	values[5]	525	1			T94	14		T53	19		T99	19
auto[0]	values[5]	values[6]	445	1			T183	17		T188	20		T174	10
auto[0]	values[5]	values[7]	232	1			T208	32		T33	46		T133	39
auto[0]	values[6]	values[0]	423	1			T14	6		T209	79		T20	22
auto[0]	values[6]	values[1]	575	1			T50	93		T256	10		T99	18
auto[0]	values[6]	values[2]	484	1			T16	101		T54	20		T20	20
auto[0]	values[6]	values[3]	488	1			T15	2		T158	45		T182	34
auto[0]	values[6]	values[4]	472	1			T38	22		T158	39		T180	8
auto[0]	values[6]	values[5]	470	1			T95	14		T87	20		T191	48
auto[0]	values[6]	values[6]	797	1			T54	20		T160	40		T204	4
auto[0]	values[6]	values[7]	278	1			T3	10		T30	20		T22	29
auto[0]	values[7]	values[0]	861	1			T53	20		T54	18		T20	20
auto[0]	values[7]	values[1]	594	1			T6	24		T49	20		T33	40
auto[0]	values[7]	values[2]	320	1			T49	20		T228	4		T53	15
auto[0]	values[7]	values[3]	455	1			T87	57		T158	78		T176	54
auto[0]	values[7]	values[4]	470	1			T7	6		T87	20		T257	48
auto[0]	values[7]	values[5]	415	1			T187	19		T236	45		T258	20
auto[0]	values[7]	values[6]	469	1			T16	36		T50	29		T53	20
auto[0]	values[7]	values[7]	294	1			T30	23		T50	97		T133	33
auto[1]	values[0]	values[0]	10	1			T244	2		T259	2		T260	4
auto[1]	values[0]	values[1]	15	1			T22	2		T236	1		T229	2
auto[1]	values[0]	values[2]	3	1			T205	3		-	-		-	-
auto[1]	values[0]	values[3]	9	1			T51	2		T261	1		T243	2
auto[1]	values[0]	values[4]	14	1			T176	3		T20	2		T22	3
auto[1]	values[0]	values[5]	26	1			T160	2		T244	1		T184	4
auto[1]	values[0]	values[6]	13	1			T54	3		T99	1		T176	2
auto[1]	values[0]	values[7]	13	1			T22	2		T191	2		T262	1
auto[1]	values[1]	values[0]	15	1			T49	1		T207	1		T20	1
auto[1]	values[1]	values[1]	8	1			T33	1		T263	2		T264	4
auto[1]	values[1]	values[2]	17	1			T30	1		T53	1		T160	2
auto[1]	values[1]	values[3]	11	1			T187	1		T184	1		T265	3
auto[1]	values[1]	values[4]	9	1			T52	2		T234	1		T266	1
auto[1]	values[1]	values[5]	5	1			T30	1		T20	1		T22	2
auto[1]	values[1]	values[6]	21	1			T41	2		T22	4		T201	1
auto[1]	values[1]	values[7]	16	1			T53	2		T160	1		T133	1
auto[1]	values[2]	values[0]	22	1			T20	1		T187	2		T205	2
auto[1]	values[2]	values[1]	10	1			T209	1		T158	2		T267	2
auto[1]	values[2]	values[2]	16	1			T30	1		T20	2		T22	2
auto[1]	values[2]	values[3]	15	1			T182	2		T268	1		T269	6
auto[1]	values[2]	values[4]	16	1			T87	1		T160	2		T132	3
auto[1]	values[2]	values[5]	4	1			T16	2		T236	2		-	-
auto[1]	values[2]	values[6]	11	1			T54	1		T33	2		T201	1
auto[1]	values[2]	values[7]	29	1			T216	8		T87	1		T160	2
auto[1]	values[3]	values[0]	11	1			T33	2		T190	1		T134	1
auto[1]	values[3]	values[1]	9	1			T50	2		T33	1		T270	2
auto[1]	values[3]	values[2]	16	1			T41	3		T87	1		T176	1
auto[1]	values[3]	values[3]	12	1			T182	3		T186	1		T271	2
auto[1]	values[3]	values[4]	10	1			T50	2		T234	1		T272	1
auto[1]	values[3]	values[5]	14	1			T41	1		T20	1		T22	5
auto[1]	values[3]	values[6]	10	1			T229	2		T201	1		T273	5
auto[1]	values[3]	values[7]	13	1			T50	3		T33	2		T198	2
auto[1]	values[4]	values[0]	4	1			T176	1		T236	1		T249	2
auto[1]	values[4]	values[1]	24	1			T236	1		T244	1		T232	1
auto[1]	values[4]	values[2]	6	1			T198	1		T249	1		T190	2
auto[1]	values[4]	values[3]	19	1			T41	1		T87	2		T20	1
auto[1]	values[4]	values[4]	16	1			T54	4		T176	1		T33	4
auto[1]	values[4]	values[5]	22	1			T208	4		T22	3		T187	1
auto[1]	values[4]	values[6]	18	1			T20	2		T188	1		T182	4
auto[1]	values[4]	values[7]	18	1			T30	3		T87	1		T160	1
auto[1]	values[5]	values[0]	9	1			T33	1		T36	1		T274	2
auto[1]	values[5]	values[1]	22	1			T53	2		T160	1		T83	1
auto[1]	values[5]	values[2]	9	1			T188	2		T205	1		T237	2
auto[1]	values[5]	values[3]	12	1			T22	1		T238	2		T241	1
auto[1]	values[5]	values[4]	21	1			T49	3		T20	2		T22	1
auto[1]	values[5]	values[5]	11	1			T53	1		T99	1		T187	1
auto[1]	values[5]	values[6]	10	1			T236	4		T205	1		T43	2
auto[1]	values[5]	values[7]	12	1			T133	4		T190	6		T275	1
auto[1]	values[6]	values[0]	15	1			T209	2		T182	2		T132	2
auto[1]	values[6]	values[1]	22	1			T50	1		T99	2		T202	2
auto[1]	values[6]	values[2]	6	1			T234	1		T276	1		T275	2
auto[1]	values[6]	values[3]	15	1			T158	1		T186	2		T236	1
auto[1]	values[6]	values[4]	11	1			T22	2		T264	3		T277	2
auto[1]	values[6]	values[5]	10	1			T229	2		T202	3		T278	2
auto[1]	values[6]	values[6]	22	1			T22	5		T182	1		T220	3
auto[1]	values[6]	values[7]	11	1			T3	10		T22	1		-	-
auto[1]	values[7]	values[0]	21	1			T54	2		T185	2		T236	2
auto[1]	values[7]	values[1]	17	1			T185	1		T237	1		T267	1
auto[1]	values[7]	values[2]	15	1			T53	5		T133	2		T234	2
auto[1]	values[7]	values[3]	15	1			T87	1		T176	2		T191	3
auto[1]	values[7]	values[4]	7	1			T133	2		T184	1		T274	2
auto[1]	values[7]	values[5]	8	1			T187	1		T236	2		T134	1
auto[1]	values[7]	values[6]	7	1			T16	1		T20	1		T234	1
auto[1]	values[7]	values[7]	7	1			T30	1		T50	4		T279	2