Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	771	1			T17	8		T18	31		T19	7
all_values[1]	771	1			T17	8		T18	31		T19	7
all_values[2]	771	1			T17	8		T18	31		T19	7
all_values[3]	771	1			T17	8		T18	31		T19	7
all_values[4]	771	1			T17	8		T18	31		T19	7
all_values[5]	771	1			T17	8		T18	31		T19	7
all_values[6]	771	1			T17	8		T18	31		T19	7
all_values[7]	771	1			T17	8		T18	31		T19	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3246

1

T17

30

T18

138

T19

26

auto[1]

2922

1

T17

34

T18

110

T19

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2527

1

T17

27

T18

114

T19

27

auto[1]

3641

1

T17

37

T18

134

T19

29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3575

1

T17

38

T18

150

T19

33

auto[1]

2593

1

T17

26

T18

98

T19

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	164	1			T18	2		T19	1		T20	1
all_values[0]	auto[0]	auto[0]	auto[1]	77	1			T18	7		T19	1		T20	1
all_values[0]	auto[0]	auto[1]	auto[0]	134	1			T17	2		T18	7		T19	2
all_values[0]	auto[0]	auto[1]	auto[1]	60	1			T17	1		T18	1		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T17	4		T18	8		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	159	1			T17	1		T18	6		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	147	1			T17	3		T18	8		T20	3
all_values[1]	auto[0]	auto[0]	auto[1]	63	1			T18	3		T21	2		T132	2
all_values[1]	auto[0]	auto[1]	auto[0]	158	1			T17	1		T18	8		T19	2
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T17	1		T18	3		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	161	1			T17	2		T18	4		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T17	1		T18	5		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T18	7		T19	2		T21	4
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T17	1		T18	1		T21	2
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T17	1		T18	4		T19	3
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T17	2		T18	5		T19	1
all_values[2]	auto[1]	auto[0]	auto[1]	170	1			T17	3		T18	9		T20	1
all_values[2]	auto[1]	auto[1]	auto[1]	143	1			T17	1		T18	5		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	168	1			T17	1		T18	14		T19	4
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T17	1		T18	2		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	106	1			T17	1		T18	4		T19	1
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T17	1		T20	1		T21	3
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T17	1		T18	7		T19	1
all_values[3]	auto[1]	auto[1]	auto[1]	157	1			T17	3		T18	4		T20	3
all_values[4]	auto[0]	auto[0]	auto[0]	169	1			T17	2		T18	6		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T18	5		T21	1		T22	6
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T17	2		T18	3		T20	2
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T18	1		T21	3		T132	2
all_values[4]	auto[1]	auto[0]	auto[1]	178	1			T17	3		T18	10		T19	4
all_values[4]	auto[1]	auto[1]	auto[1]	145	1			T17	1		T18	6		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	218	1			T17	1		T18	6		T19	1
all_values[5]	auto[0]	auto[1]	auto[0]	241	1			T17	6		T18	13		T19	3
all_values[5]	auto[1]	auto[0]	auto[1]	159	1			T17	1		T18	8		T19	3
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T18	4		T20	1		T21	2
all_values[6]	auto[0]	auto[0]	auto[0]	155	1			T18	14		T21	4		T22	1
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T17	2		T20	2		T21	4
all_values[6]	auto[0]	auto[1]	auto[0]	135	1			T17	3		T18	3		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T17	1		T18	2		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T17	2		T18	5		T19	1
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T18	7		T19	3		T20	2
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T17	2		T18	5		T19	2
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T18	3		T20	1		T21	3
all_values[7]	auto[0]	auto[1]	auto[0]	145	1			T17	2		T18	10		T19	3
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T17	1		T18	3		T20	1
all_values[7]	auto[1]	auto[0]	auto[1]	172	1			T17	1		T18	4		T20	2
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T17	2		T18	6		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal