Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1763

1

T1

5

T2

5

T4

8

auto[1]

1720

1

T1

3

T2

6

T4

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1904

1

T1

6

T12

11

T27

22

auto[1]

1579

1

T1

2

T2

11

T4

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2760

1

T1

3

T2

11

T4

11

auto[1]

723

1

T1

5

T12

3

T27

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	728	1			T1	2		T2	2		T4	2
valid[1]	678	1			T1	2		T2	1		T4	6
valid[2]	705	1			T1	1		T2	1		T4	2
valid[3]	680	1			T1	1		T2	4		T9	10
valid[4]	692	1			T1	2		T2	3		T4	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	130	1			T1	1		T27	2		T28	1
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T1	1		T4	2		T9	6
auto[0]	auto[0]	valid[1]	auto[0]	129	1			T28	1		T30	1		T26	1
auto[0]	auto[0]	valid[1]	auto[1]	169	1			T1	1		T4	5		T9	5
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T12	1		T27	3		T28	2
auto[0]	auto[0]	valid[2]	auto[1]	136	1			T2	1		T9	2		T92	1
auto[0]	auto[0]	valid[3]	auto[0]	106	1			T12	1		T27	2		T28	2
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T2	1		T9	3		T29	3
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T12	2		T28	3		T30	2
auto[0]	auto[0]	valid[4]	auto[1]	163	1			T2	3		T4	1		T9	3
auto[0]	auto[1]	valid[0]	auto[0]	110	1			T12	1		T28	1		T30	2
auto[0]	auto[1]	valid[0]	auto[1]	165	1			T2	2		T9	5		T92	2
auto[0]	auto[1]	valid[1]	auto[0]	98	1			T27	1		T28	2		T30	1
auto[0]	auto[1]	valid[1]	auto[1]	141	1			T2	1		T4	1		T9	3
auto[0]	auto[1]	valid[2]	auto[0]	137	1			T12	1		T27	3		T30	1
auto[0]	auto[1]	valid[2]	auto[1]	173	1			T4	2		T9	5		T29	2
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T12	1		T27	3		T28	3
auto[0]	auto[1]	valid[3]	auto[1]	152	1			T2	3		T9	7		T93	3
auto[0]	auto[1]	valid[4]	auto[0]	110	1			T12	1		T30	1		T26	1
auto[0]	auto[1]	valid[4]	auto[1]	150	1			T9	6		T29	2		T92	1
auto[1]	auto[0]	valid[0]	auto[0]	69	1			T12	3		T30	1		T37	3
auto[1]	auto[0]	valid[1]	auto[0]	69	1			T299	1		T50	1		T292	1
auto[1]	auto[0]	valid[2]	auto[0]	67	1			T26	2		T41	4		T292	2
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T1	1		T28	1		T30	3
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T1	1		T27	2		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T28	1		T291	1		T292	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T1	1		T27	1		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	72	1			T1	1		T27	1		T30	1
auto[1]	auto[1]	valid[3]	auto[0]	65	1			T27	4		T44	1		T299	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T1	1		T28	1		T41	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal