Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47175

1

T1

176

T10

1

T12

308

auto[1]

16177

1

T1

54

T2

11

T4

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46109

1

T1

153

T2

11

T4

11

auto[1]

17243

1

T1

77

T10

1

T12

123

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32488	1			T1	111		T2	11		T4	11
others[1]	5389	1			T1	29		T9	38		T12	32
others[2]	5358	1			T1	15		T9	43		T12	25
others[3]	6102	1			T1	18		T9	51		T10	1
interest[1]	3523	1			T1	16		T9	27		T12	21
interest[4]	21132	1			T1	74		T2	11		T4	11
interest[64]	10492	1			T1	41		T9	89		T12	62

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15207	1			T1	48		T12	94		T27	180
auto[0]	auto[0]	others[1]	2604	1			T1	12		T12	19		T27	26
auto[0]	auto[0]	others[2]	2544	1			T1	7		T12	12		T27	25
auto[0]	auto[0]	others[3]	2885	1			T1	6		T12	19		T27	38
auto[0]	auto[0]	interest[1]	1681	1			T1	10		T12	12		T27	21
auto[0]	auto[0]	interest[4]	9779	1			T1	32		T12	57		T27	127
auto[0]	auto[0]	interest[64]	5011	1			T1	16		T12	29		T27	61
auto[0]	auto[1]	others[0]	8418	1			T1	28		T2	11		T4	11
auto[0]	auto[1]	others[1]	1380	1			T1	8		T9	38		T12	5
auto[0]	auto[1]	others[2]	1312	1			T1	2		T9	43		T12	2
auto[0]	auto[1]	others[3]	1570	1			T1	4		T9	51		T12	9
auto[0]	auto[1]	interest[1]	903	1			T1	3		T9	27		T12	1
auto[0]	auto[1]	interest[4]	5599	1			T1	19		T2	11		T4	11
auto[0]	auto[1]	interest[64]	2594	1			T1	9		T9	89		T12	9
auto[1]	auto[0]	others[0]	8863	1			T1	35		T12	60		T27	73
auto[1]	auto[0]	others[1]	1405	1			T1	9		T12	8		T27	18
auto[1]	auto[0]	others[2]	1502	1			T1	6		T12	11		T27	23
auto[1]	auto[0]	others[3]	1647	1			T1	8		T10	1		T12	12
auto[1]	auto[0]	interest[1]	939	1			T1	3		T12	8		T27	7
auto[1]	auto[0]	interest[4]	5754	1			T1	23		T12	43		T27	44
auto[1]	auto[0]	interest[64]	2887	1			T1	16		T12	24		T27	33

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal