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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
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T167 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4172841543 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:11 PM PDT 24 2796303404 ps
T1029 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1824507785 Aug 16 04:45:16 PM PDT 24 Aug 16 04:45:17 PM PDT 24 16537546 ps
T1030 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2625699051 Aug 16 04:44:52 PM PDT 24 Aug 16 04:44:53 PM PDT 24 12012234 ps
T123 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3568302214 Aug 16 04:44:53 PM PDT 24 Aug 16 04:44:55 PM PDT 24 76046281 ps
T169 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2025038384 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:12 PM PDT 24 555961156 ps
T114 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2280566682 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:07 PM PDT 24 404927334 ps
T1031 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1087423399 Aug 16 04:45:10 PM PDT 24 Aug 16 04:45:10 PM PDT 24 12619767 ps
T1032 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3104546519 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 22707431 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1458347785 Aug 16 04:44:58 PM PDT 24 Aug 16 04:44:59 PM PDT 24 49601162 ps
T111 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1005771992 Aug 16 04:44:49 PM PDT 24 Aug 16 04:44:52 PM PDT 24 120561104 ps
T143 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2318495126 Aug 16 04:44:51 PM PDT 24 Aug 16 04:45:13 PM PDT 24 3790717217 ps
T1033 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3894630452 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:03 PM PDT 24 20134595 ps
T1034 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3177696030 Aug 16 04:45:01 PM PDT 24 Aug 16 04:45:04 PM PDT 24 165156370 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3031951537 Aug 16 04:45:06 PM PDT 24 Aug 16 04:45:09 PM PDT 24 112574236 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3385287399 Aug 16 04:44:55 PM PDT 24 Aug 16 04:44:56 PM PDT 24 67268365 ps
T1035 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.805609056 Aug 16 04:45:05 PM PDT 24 Aug 16 04:45:06 PM PDT 24 29543124 ps
T1036 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4189235882 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:03 PM PDT 24 102487962 ps
T170 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.43300182 Aug 16 04:45:06 PM PDT 24 Aug 16 04:45:18 PM PDT 24 3163985665 ps
T165 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3736084000 Aug 16 04:44:52 PM PDT 24 Aug 16 04:44:57 PM PDT 24 306742596 ps
T1037 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3620484887 Aug 16 04:44:54 PM PDT 24 Aug 16 04:44:55 PM PDT 24 40106185 ps
T1038 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1596290809 Aug 16 04:45:06 PM PDT 24 Aug 16 04:45:08 PM PDT 24 30306801 ps
T1039 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2369878670 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:08 PM PDT 24 232400486 ps
T1040 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1502124631 Aug 16 04:45:07 PM PDT 24 Aug 16 04:45:08 PM PDT 24 16023931 ps
T144 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2979833254 Aug 16 04:44:51 PM PDT 24 Aug 16 04:45:06 PM PDT 24 6436447402 ps
T145 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3071881678 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:02 PM PDT 24 58931947 ps
T1041 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.829285793 Aug 16 04:45:10 PM PDT 24 Aug 16 04:45:10 PM PDT 24 10883552 ps
T146 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3586508079 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:03 PM PDT 24 238127637 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3706278652 Aug 16 04:44:54 PM PDT 24 Aug 16 04:44:55 PM PDT 24 80497359 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.279524679 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:00 PM PDT 24 115681430 ps
T171 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.85922334 Aug 16 04:44:53 PM PDT 24 Aug 16 04:45:06 PM PDT 24 10626449951 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1850375706 Aug 16 04:44:53 PM PDT 24 Aug 16 04:44:57 PM PDT 24 57141164 ps
T1044 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1274897907 Aug 16 04:45:09 PM PDT 24 Aug 16 04:45:09 PM PDT 24 14036220 ps
T1045 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1146181109 Aug 16 04:45:16 PM PDT 24 Aug 16 04:45:17 PM PDT 24 38164781 ps
T1046 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1969832267 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:02 PM PDT 24 117736579 ps
T1047 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.497923028 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 12461539 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.987965469 Aug 16 04:44:52 PM PDT 24 Aug 16 04:44:54 PM PDT 24 268196168 ps
T147 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3188534895 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:08 PM PDT 24 611688815 ps
T116 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1003594829 Aug 16 04:45:03 PM PDT 24 Aug 16 04:45:07 PM PDT 24 387535360 ps
T128 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3432247383 Aug 16 04:44:48 PM PDT 24 Aug 16 04:45:02 PM PDT 24 389740671 ps
T1048 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4060395833 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 52494714 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1092922149 Aug 16 04:44:54 PM PDT 24 Aug 16 04:44:57 PM PDT 24 194812527 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2804636036 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:07 PM PDT 24 466772777 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1169670761 Aug 16 04:44:48 PM PDT 24 Aug 16 04:44:50 PM PDT 24 253564817 ps
T1052 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3832554577 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:06 PM PDT 24 762060504 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4076657061 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:01 PM PDT 24 34885286 ps
T148 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1613701283 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:26 PM PDT 24 1218722702 ps
T168 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2470529801 Aug 16 04:44:57 PM PDT 24 Aug 16 04:45:17 PM PDT 24 837586452 ps
T129 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1335172151 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:01 PM PDT 24 36157349 ps
T149 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.200057135 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:04 PM PDT 24 61683777 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2495995184 Aug 16 04:44:53 PM PDT 24 Aug 16 04:44:54 PM PDT 24 13049579 ps
T1055 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2992986295 Aug 16 04:45:07 PM PDT 24 Aug 16 04:45:08 PM PDT 24 27399687 ps
T130 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3075375139 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:02 PM PDT 24 27848067 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1152967591 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:14 PM PDT 24 551129628 ps
T1057 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3330260726 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:22 PM PDT 24 4530685604 ps
T1058 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1001806799 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:08 PM PDT 24 153104881 ps
T1059 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3803147967 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 18744324 ps
T1060 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4182229306 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:01 PM PDT 24 29491361 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4246729796 Aug 16 04:44:58 PM PDT 24 Aug 16 04:44:59 PM PDT 24 90174313 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4066308504 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:02 PM PDT 24 34523260 ps
T90 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3929162687 Aug 16 04:44:48 PM PDT 24 Aug 16 04:44:50 PM PDT 24 22315910 ps
T1063 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1968023736 Aug 16 04:45:06 PM PDT 24 Aug 16 04:45:10 PM PDT 24 190647534 ps
T1064 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3697586342 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 25369364 ps
T1065 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1531702419 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 42150086 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3892524533 Aug 16 04:44:56 PM PDT 24 Aug 16 04:45:09 PM PDT 24 1251762109 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1244615649 Aug 16 04:45:01 PM PDT 24 Aug 16 04:45:03 PM PDT 24 321653826 ps
T1068 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4214998313 Aug 16 04:44:56 PM PDT 24 Aug 16 04:44:58 PM PDT 24 234759236 ps
T1069 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2997484993 Aug 16 04:44:57 PM PDT 24 Aug 16 04:45:01 PM PDT 24 73126684 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1631168834 Aug 16 04:44:54 PM PDT 24 Aug 16 04:44:55 PM PDT 24 103209506 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.521178107 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:06 PM PDT 24 41240357 ps
T1072 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1570790844 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:05 PM PDT 24 91715311 ps
T166 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3188948595 Aug 16 04:44:51 PM PDT 24 Aug 16 04:44:56 PM PDT 24 2199117424 ps
T1073 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2692655987 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:08 PM PDT 24 152835613 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1284288202 Aug 16 04:44:57 PM PDT 24 Aug 16 04:44:58 PM PDT 24 51416165 ps
T1075 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.578927499 Aug 16 04:45:07 PM PDT 24 Aug 16 04:45:08 PM PDT 24 14422548 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.668488741 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:02 PM PDT 24 49104504 ps
T1077 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2250166976 Aug 16 04:45:09 PM PDT 24 Aug 16 04:45:10 PM PDT 24 19639775 ps
T91 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3960140006 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:01 PM PDT 24 170693016 ps
T1078 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3311531999 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:02 PM PDT 24 664057765 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.497092144 Aug 16 04:45:01 PM PDT 24 Aug 16 04:45:24 PM PDT 24 873840046 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1352572553 Aug 16 04:44:53 PM PDT 24 Aug 16 04:44:56 PM PDT 24 45896284 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3292010721 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:00 PM PDT 24 916529171 ps
T1082 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2912073324 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:06 PM PDT 24 89015592 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3648953410 Aug 16 04:44:50 PM PDT 24 Aug 16 04:45:03 PM PDT 24 1107458234 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3703698461 Aug 16 04:44:55 PM PDT 24 Aug 16 04:44:56 PM PDT 24 36495135 ps
T1085 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.685612028 Aug 16 04:45:03 PM PDT 24 Aug 16 04:45:07 PM PDT 24 266048053 ps
T1086 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.32060634 Aug 16 04:45:00 PM PDT 24 Aug 16 04:45:02 PM PDT 24 102807647 ps
T1087 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4147475337 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:04 PM PDT 24 81012361 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2611139635 Aug 16 04:44:57 PM PDT 24 Aug 16 04:44:59 PM PDT 24 76462301 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3254802912 Aug 16 04:44:55 PM PDT 24 Aug 16 04:44:59 PM PDT 24 153696836 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3981156714 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:00 PM PDT 24 130126005 ps
T1091 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3237778064 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 44374829 ps
T1092 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2784882477 Aug 16 04:45:09 PM PDT 24 Aug 16 04:45:09 PM PDT 24 45212437 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3707768785 Aug 16 04:44:55 PM PDT 24 Aug 16 04:44:59 PM PDT 24 312793665 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1237573292 Aug 16 04:44:53 PM PDT 24 Aug 16 04:44:55 PM PDT 24 56912751 ps
T1095 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.497318309 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:03 PM PDT 24 15447338 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1450075550 Aug 16 04:44:51 PM PDT 24 Aug 16 04:44:56 PM PDT 24 163397026 ps
T1097 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3385812396 Aug 16 04:45:06 PM PDT 24 Aug 16 04:45:10 PM PDT 24 304634451 ps
T1098 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2728153237 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 13193720 ps
T1099 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3921442034 Aug 16 04:45:07 PM PDT 24 Aug 16 04:45:08 PM PDT 24 25240580 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1408691591 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:07 PM PDT 24 112266854 ps
T1101 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3758569822 Aug 16 04:44:56 PM PDT 24 Aug 16 04:45:00 PM PDT 24 154476049 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1937730220 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:08 PM PDT 24 131257931 ps
T1103 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2026653507 Aug 16 04:44:55 PM PDT 24 Aug 16 04:44:58 PM PDT 24 146945855 ps
T1104 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.442012737 Aug 16 04:45:01 PM PDT 24 Aug 16 04:45:02 PM PDT 24 92795744 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.796684726 Aug 16 04:44:50 PM PDT 24 Aug 16 04:44:50 PM PDT 24 112293265 ps
T1106 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1206639115 Aug 16 04:45:03 PM PDT 24 Aug 16 04:45:04 PM PDT 24 52229300 ps
T1107 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4008123768 Aug 16 04:45:02 PM PDT 24 Aug 16 04:45:04 PM PDT 24 69580327 ps
T1108 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3749256274 Aug 16 04:45:08 PM PDT 24 Aug 16 04:45:09 PM PDT 24 13886333 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1890312726 Aug 16 04:44:57 PM PDT 24 Aug 16 04:44:59 PM PDT 24 23972200 ps
T1110 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.54053102 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:01 PM PDT 24 121141191 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.927896054 Aug 16 04:44:48 PM PDT 24 Aug 16 04:44:49 PM PDT 24 10254332 ps
T1112 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1726936264 Aug 16 04:45:04 PM PDT 24 Aug 16 04:45:11 PM PDT 24 105022966 ps
T1113 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3745096230 Aug 16 04:44:53 PM PDT 24 Aug 16 04:45:06 PM PDT 24 210306799 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1740205223 Aug 16 04:45:01 PM PDT 24 Aug 16 04:45:06 PM PDT 24 619545581 ps
T1115 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2194719627 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:02 PM PDT 24 1063235628 ps
T1116 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2350321894 Aug 16 04:45:03 PM PDT 24 Aug 16 04:45:06 PM PDT 24 463488475 ps
T1117 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2600943008 Aug 16 04:45:06 PM PDT 24 Aug 16 04:45:07 PM PDT 24 19032962 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.82929123 Aug 16 04:44:55 PM PDT 24 Aug 16 04:44:56 PM PDT 24 15446907 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4216452380 Aug 16 04:44:56 PM PDT 24 Aug 16 04:45:03 PM PDT 24 115885492 ps
T1120 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3598830847 Aug 16 04:45:03 PM PDT 24 Aug 16 04:45:04 PM PDT 24 26879868 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.885676375 Aug 16 04:44:51 PM PDT 24 Aug 16 04:44:52 PM PDT 24 36731991 ps
T1122 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2167983322 Aug 16 04:45:01 PM PDT 24 Aug 16 04:45:05 PM PDT 24 554937182 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1502964064 Aug 16 04:44:56 PM PDT 24 Aug 16 04:44:59 PM PDT 24 82829150 ps
T1124 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1406750584 Aug 16 04:45:09 PM PDT 24 Aug 16 04:45:10 PM PDT 24 46468198 ps
T1125 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1415110719 Aug 16 04:44:53 PM PDT 24 Aug 16 04:44:57 PM PDT 24 690909251 ps
T1126 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3906441374 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:05 PM PDT 24 99135063 ps
T1127 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4151750526 Aug 16 04:44:58 PM PDT 24 Aug 16 04:45:01 PM PDT 24 43302439 ps
T1128 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.169325524 Aug 16 04:45:16 PM PDT 24 Aug 16 04:45:17 PM PDT 24 26589256 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2474333272 Aug 16 04:44:59 PM PDT 24 Aug 16 04:45:00 PM PDT 24 38521231 ps
T1130 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3193670551 Aug 16 04:44:54 PM PDT 24 Aug 16 04:44:55 PM PDT 24 40088689 ps

Test location /workspace/coverage/default/7.spi_device_upload.2011983326
Short name T6
Test name
Test status
Simulation time 12766834029 ps
CPU time 15.88 seconds
Started Aug 16 05:49:50 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 225420 kb
Host smart-e6d2118f-0ea4-43b2-8049-1a6e412c4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011983326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2011983326
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.681398869
Short name T12
Test name
Test status
Simulation time 178540059899 ps
CPU time 306.14 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 265732 kb
Host smart-546881d8-7d5a-46ca-a563-73efeb618b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681398869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.681398869
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2360888325
Short name T18
Test name
Test status
Simulation time 39828548476 ps
CPU time 125.67 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:52:04 PM PDT 24
Peak memory 258364 kb
Host smart-55fa916c-f4f2-4d15-b1c2-2c45cdd8f191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360888325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2360888325
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3476473442
Short name T30
Test name
Test status
Simulation time 9064110666 ps
CPU time 141.92 seconds
Started Aug 16 05:51:10 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 266544 kb
Host smart-90d182ca-4ea8-48ef-8154-5929cf6f1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476473442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3476473442
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3222732830
Short name T107
Test name
Test status
Simulation time 147457070 ps
CPU time 3.6 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 218092 kb
Host smart-9259713d-219d-4849-ab5d-fa240ecd7896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222732830 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3222732830
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.614773141
Short name T20
Test name
Test status
Simulation time 77013358981 ps
CPU time 748.79 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 06:03:16 PM PDT 24
Peak memory 283024 kb
Host smart-339f3eda-3306-4ef2-89d8-a0b0f447429c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614773141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.614773141
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3916328990
Short name T41
Test name
Test status
Simulation time 33225056498 ps
CPU time 100.14 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 242096 kb
Host smart-d946b843-8e32-43de-8f00-2d3af3bb8409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916328990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3916328990
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1292931142
Short name T73
Test name
Test status
Simulation time 17126000 ps
CPU time 0.75 seconds
Started Aug 16 05:49:50 PM PDT 24
Finished Aug 16 05:49:50 PM PDT 24
Peak memory 216828 kb
Host smart-6fc9658a-7e13-4b14-ae03-83012e00a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292931142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1292931142
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2465328822
Short name T36
Test name
Test status
Simulation time 68414262044 ps
CPU time 395.59 seconds
Started Aug 16 05:51:23 PM PDT 24
Finished Aug 16 05:57:59 PM PDT 24
Peak memory 283640 kb
Host smart-755538f4-5a89-4e2a-b256-b393ecdc24f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465328822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2465328822
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.268968948
Short name T50
Test name
Test status
Simulation time 28936050349 ps
CPU time 123.12 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:53:37 PM PDT 24
Peak memory 272468 kb
Host smart-c7ee95c3-b78b-42e4-9f3b-9a2c33a5b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268968948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.268968948
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.676549495
Short name T133
Test name
Test status
Simulation time 5423951914 ps
CPU time 130.9 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:53:25 PM PDT 24
Peak memory 269764 kb
Host smart-e7885e96-5fe9-4e15-a547-99a61a307715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676549495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.676549495
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2528085415
Short name T236
Test name
Test status
Simulation time 8878792217 ps
CPU time 97.34 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:52:27 PM PDT 24
Peak memory 266460 kb
Host smart-304e3923-6abd-4b2d-99ac-93cbe8ce1498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528085415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2528085415
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4172841543
Short name T167
Test name
Test status
Simulation time 2796303404 ps
CPU time 12.55 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:11 PM PDT 24
Peak memory 216104 kb
Host smart-71fd7603-a855-417f-8217-cec16e22cdde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172841543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4172841543
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3662202531
Short name T331
Test name
Test status
Simulation time 39218663 ps
CPU time 0.7 seconds
Started Aug 16 05:50:28 PM PDT 24
Finished Aug 16 05:50:28 PM PDT 24
Peak memory 205724 kb
Host smart-4617b844-ec6d-4fdd-8063-e54ddaca7a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662202531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3662202531
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3560824190
Short name T25
Test name
Test status
Simulation time 175725479 ps
CPU time 3.96 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:17 PM PDT 24
Peak memory 218324 kb
Host smart-e703b318-fd6a-42b2-a7b8-63f000665d96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3560824190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3560824190
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.4117377810
Short name T184
Test name
Test status
Simulation time 117905921085 ps
CPU time 448.8 seconds
Started Aug 16 05:50:03 PM PDT 24
Finished Aug 16 05:57:32 PM PDT 24
Peak memory 266380 kb
Host smart-bdf59229-733b-47ea-9c46-1e16e4cfd0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117377810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.4117377810
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.352544445
Short name T112
Test name
Test status
Simulation time 319505118 ps
CPU time 5.28 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 215212 kb
Host smart-4bcc2f93-5f62-44ca-81fa-cd92331f91c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352544445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.352544445
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2581801743
Short name T121
Test name
Test status
Simulation time 19900798 ps
CPU time 1.3 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 206744 kb
Host smart-80264e6b-3d2d-479c-8658-45a1c6e31871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581801743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
581801743
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.342011057
Short name T22
Test name
Test status
Simulation time 86393816554 ps
CPU time 665.43 seconds
Started Aug 16 05:52:13 PM PDT 24
Finished Aug 16 06:03:18 PM PDT 24
Peak memory 287744 kb
Host smart-e89c55d9-a855-4aa9-b571-07f973ef27a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342011057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.342011057
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1813814404
Short name T205
Test name
Test status
Simulation time 31103273660 ps
CPU time 265.32 seconds
Started Aug 16 05:49:54 PM PDT 24
Finished Aug 16 05:54:19 PM PDT 24
Peak memory 266444 kb
Host smart-a93c69da-1720-4cf7-be25-380d5af04ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813814404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1813814404
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1125305488
Short name T54
Test name
Test status
Simulation time 207308549879 ps
CPU time 350.16 seconds
Started Aug 16 05:52:09 PM PDT 24
Finished Aug 16 05:58:00 PM PDT 24
Peak memory 250004 kb
Host smart-bc2a9029-f0e4-4517-a0bd-788360836fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125305488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1125305488
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2602333485
Short name T1
Test name
Test status
Simulation time 1023387444 ps
CPU time 13.83 seconds
Started Aug 16 05:52:18 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 217152 kb
Host smart-5c674788-bf2c-45af-8c21-8d639d50cd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602333485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2602333485
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3876399813
Short name T77
Test name
Test status
Simulation time 384687482 ps
CPU time 1.06 seconds
Started Aug 16 05:49:35 PM PDT 24
Finished Aug 16 05:49:36 PM PDT 24
Peak memory 237192 kb
Host smart-27d78d41-21b7-4d66-997c-a388e56d6002
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876399813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3876399813
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1170499924
Short name T190
Test name
Test status
Simulation time 481732363269 ps
CPU time 638.77 seconds
Started Aug 16 05:51:19 PM PDT 24
Finished Aug 16 06:01:58 PM PDT 24
Peak memory 282844 kb
Host smart-d2d95bd1-a4ed-4845-af96-fa3cfdf0571b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170499924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1170499924
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1103099673
Short name T281
Test name
Test status
Simulation time 983628023 ps
CPU time 14.2 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:15 PM PDT 24
Peak memory 225428 kb
Host smart-52d59e99-fcb5-4773-b545-bbbfd6e00f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103099673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1103099673
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3062878543
Short name T37
Test name
Test status
Simulation time 73895526908 ps
CPU time 333.55 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:56:21 PM PDT 24
Peak memory 252380 kb
Host smart-561bd050-abf7-4364-b290-0dd15c207921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062878543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3062878543
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.294608434
Short name T132
Test name
Test status
Simulation time 3120021459 ps
CPU time 80.72 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:52:12 PM PDT 24
Peak memory 266448 kb
Host smart-3fdd156b-da17-4f19-82bd-3b543902de49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294608434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.294608434
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2450450740
Short name T266
Test name
Test status
Simulation time 144445287600 ps
CPU time 172.26 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 253448 kb
Host smart-e2d117ef-8816-41ea-8893-0a6efe576686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450450740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2450450740
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.395830206
Short name T302
Test name
Test status
Simulation time 10221468153 ps
CPU time 66.52 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:52:16 PM PDT 24
Peak memory 256708 kb
Host smart-0eb338e2-fd50-44d9-bc84-dcc511c2d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395830206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.395830206
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3610656719
Short name T991
Test name
Test status
Simulation time 8878915258 ps
CPU time 100.45 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 282324 kb
Host smart-f1ba4124-0b33-4002-8bec-52c2bcf7f544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610656719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3610656719
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3603401604
Short name T188
Test name
Test status
Simulation time 13115567730 ps
CPU time 78.94 seconds
Started Aug 16 05:51:07 PM PDT 24
Finished Aug 16 05:52:26 PM PDT 24
Peak memory 258312 kb
Host smart-5a1ae779-22b8-4001-866c-015c60b78e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603401604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3603401604
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.985607794
Short name T276
Test name
Test status
Simulation time 98598273170 ps
CPU time 182.76 seconds
Started Aug 16 05:52:18 PM PDT 24
Finished Aug 16 05:55:21 PM PDT 24
Peak memory 256348 kb
Host smart-3299ceab-75ab-49a0-845b-7969dc7f19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985607794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.985607794
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2979833254
Short name T144
Test name
Test status
Simulation time 6436447402 ps
CPU time 15.05 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215280 kb
Host smart-62061897-4bec-46f0-a6ca-222482bea8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979833254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2979833254
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3085203064
Short name T310
Test name
Test status
Simulation time 177036850 ps
CPU time 0.87 seconds
Started Aug 16 05:50:26 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 206872 kb
Host smart-f691209b-9b28-42b7-a725-87374d691dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085203064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3085203064
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2944795415
Short name T110
Test name
Test status
Simulation time 7371183634 ps
CPU time 73.07 seconds
Started Aug 16 05:51:46 PM PDT 24
Finished Aug 16 05:52:59 PM PDT 24
Peak memory 234788 kb
Host smart-280d9738-4888-4132-a75f-9d3c59157603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944795415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2944795415
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4120171350
Short name T56
Test name
Test status
Simulation time 11373495383 ps
CPU time 176.73 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:53:48 PM PDT 24
Peak memory 263404 kb
Host smart-0aa86b18-6052-41ed-9df3-19c87b95be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120171350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4120171350
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1003594829
Short name T116
Test name
Test status
Simulation time 387535360 ps
CPU time 3.61 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 215252 kb
Host smart-820d7990-32b0-40a2-a707-bdde01f4f980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003594829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1003594829
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2423765945
Short name T51
Test name
Test status
Simulation time 95698284776 ps
CPU time 44.64 seconds
Started Aug 16 05:50:42 PM PDT 24
Finished Aug 16 05:51:27 PM PDT 24
Peak memory 241728 kb
Host smart-47092977-9d0e-419e-bb39-26194ffb5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423765945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2423765945
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2337030862
Short name T259
Test name
Test status
Simulation time 2193065888 ps
CPU time 50.55 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:50:35 PM PDT 24
Peak memory 256752 kb
Host smart-0523a3c1-53e5-40a1-8916-6823e4957588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337030862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2337030862
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2535103777
Short name T198
Test name
Test status
Simulation time 112714553006 ps
CPU time 266.38 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:55:31 PM PDT 24
Peak memory 254960 kb
Host smart-e56fad69-6b5a-4d73-bda7-8ef840e103f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535103777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2535103777
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.48463689
Short name T158
Test name
Test status
Simulation time 9853120567 ps
CPU time 66.64 seconds
Started Aug 16 05:49:46 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 255552 kb
Host smart-ae372741-f57d-44d0-bb96-b609a44265e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48463689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.48463689
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2463383343
Short name T97
Test name
Test status
Simulation time 4747038788 ps
CPU time 8.43 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 225364 kb
Host smart-4e02a766-1a32-42c0-9f41-cc6f2e8ecb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463383343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2463383343
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2470529801
Short name T168
Test name
Test status
Simulation time 837586452 ps
CPU time 19.16 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:45:17 PM PDT 24
Peak memory 215740 kb
Host smart-890447eb-f703-417f-adea-bb7495eb3389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470529801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2470529801
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.85922334
Short name T171
Test name
Test status
Simulation time 10626449951 ps
CPU time 12.29 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215832 kb
Host smart-b1456837-aeb2-4652-8e13-768a448051d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85922334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.85922334
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1853935104
Short name T273
Test name
Test status
Simulation time 75176341095 ps
CPU time 724.37 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 06:01:56 PM PDT 24
Peak memory 267728 kb
Host smart-f559f79a-52fa-42fd-81be-48cfb09c6ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853935104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1853935104
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2800075627
Short name T175
Test name
Test status
Simulation time 37511860043 ps
CPU time 158.55 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:52:39 PM PDT 24
Peak memory 254212 kb
Host smart-7f33d14d-5f21-4e5b-85b8-dedb7a737ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800075627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2800075627
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.306791261
Short name T297
Test name
Test status
Simulation time 41088029059 ps
CPU time 403.17 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:56:44 PM PDT 24
Peak memory 257088 kb
Host smart-1fdca93b-52bb-494b-8a0d-b56fee50d137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306791261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.306791261
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3336962375
Short name T264
Test name
Test status
Simulation time 80918246001 ps
CPU time 566.42 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 06:00:28 PM PDT 24
Peak memory 264928 kb
Host smart-2cc389cc-7ac7-4fbd-b458-e8721565608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336962375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3336962375
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3064107094
Short name T268
Test name
Test status
Simulation time 52415873727 ps
CPU time 208.02 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:55:01 PM PDT 24
Peak memory 250220 kb
Host smart-26f592d9-e84e-40f4-b40e-1e6c103be785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064107094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3064107094
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2395971848
Short name T306
Test name
Test status
Simulation time 6911199674 ps
CPU time 89.76 seconds
Started Aug 16 05:53:01 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 252216 kb
Host smart-dfe46cfd-1fda-4fea-80fe-7fe87e631cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395971848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2395971848
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3960140006
Short name T91
Test name
Test status
Simulation time 170693016 ps
CPU time 1.38 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 206824 kb
Host smart-636cfd98-550e-4212-b630-2c5839eefb4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960140006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3960140006
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1005771992
Short name T111
Test name
Test status
Simulation time 120561104 ps
CPU time 3.28 seconds
Started Aug 16 04:44:49 PM PDT 24
Finished Aug 16 04:44:52 PM PDT 24
Peak memory 219240 kb
Host smart-8a1ec4fc-0af4-4b06-985d-bc650ea51d36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005771992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
005771992
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1408691591
Short name T1100
Test name
Test status
Simulation time 112266854 ps
CPU time 7.24 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 206752 kb
Host smart-197091b4-6090-413c-a711-410a6b734b32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408691591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1408691591
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.78603828
Short name T1022
Test name
Test status
Simulation time 1219002442 ps
CPU time 25.29 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:26 PM PDT 24
Peak memory 206800 kb
Host smart-eebc1d25-217e-4401-b6cf-83fe17f43adf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78603828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
bit_bash.78603828
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1502964064
Short name T1123
Test name
Test status
Simulation time 82829150 ps
CPU time 2.45 seconds
Started Aug 16 04:44:56 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 216488 kb
Host smart-35cd8062-4402-4a0f-8add-f92defd0bd31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502964064 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1502964064
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.796684726
Short name T1105
Test name
Test status
Simulation time 112293265 ps
CPU time 0.75 seconds
Started Aug 16 04:44:50 PM PDT 24
Finished Aug 16 04:44:50 PM PDT 24
Peak memory 203672 kb
Host smart-6451002f-6219-45a2-93d3-56eaf5f58c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796684726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.796684726
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1169670761
Short name T1051
Test name
Test status
Simulation time 253564817 ps
CPU time 1.43 seconds
Started Aug 16 04:44:48 PM PDT 24
Finished Aug 16 04:44:50 PM PDT 24
Peak memory 215020 kb
Host smart-8f2b5945-2300-49ac-b105-bdabee22c2bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169670761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1169670761
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.927896054
Short name T1111
Test name
Test status
Simulation time 10254332 ps
CPU time 0.7 seconds
Started Aug 16 04:44:48 PM PDT 24
Finished Aug 16 04:44:49 PM PDT 24
Peak memory 203576 kb
Host smart-8c7f19c3-782d-4ac2-b485-1c6872340ada
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927896054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.927896054
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3707768785
Short name T1093
Test name
Test status
Simulation time 312793665 ps
CPU time 3.98 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 215012 kb
Host smart-69ccd8b5-ba63-41ce-8e10-4bef99c5bae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707768785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3707768785
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3648953410
Short name T1083
Test name
Test status
Simulation time 1107458234 ps
CPU time 12.76 seconds
Started Aug 16 04:44:50 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 215516 kb
Host smart-67f4657d-eb78-4791-892b-712956a87fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648953410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3648953410
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3432247383
Short name T128
Test name
Test status
Simulation time 389740671 ps
CPU time 13.91 seconds
Started Aug 16 04:44:48 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 215160 kb
Host smart-f42aab32-8d7a-4cdf-8390-a52ccf73b5f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432247383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3432247383
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3892524533
Short name T1066
Test name
Test status
Simulation time 1251762109 ps
CPU time 12.66 seconds
Started Aug 16 04:44:56 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 206844 kb
Host smart-626cf124-80ba-431f-bbbf-f156bf1507dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892524533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3892524533
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3929162687
Short name T90
Test name
Test status
Simulation time 22315910 ps
CPU time 1.38 seconds
Started Aug 16 04:44:48 PM PDT 24
Finished Aug 16 04:44:50 PM PDT 24
Peak memory 215968 kb
Host smart-0af219d2-1e84-4cee-aadb-9c9306b5dc7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929162687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3929162687
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4246729796
Short name T1061
Test name
Test status
Simulation time 90174313 ps
CPU time 1.81 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 215160 kb
Host smart-55deb1ee-db8a-4779-a519-08b33b74fcec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246729796 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4246729796
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3385287399
Short name T124
Test name
Test status
Simulation time 67268365 ps
CPU time 1.7 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 206948 kb
Host smart-ae2d238f-ca8c-4ca5-8e9c-dad42beb594d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385287399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
385287399
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1631168834
Short name T1070
Test name
Test status
Simulation time 103209506 ps
CPU time 0.73 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 203736 kb
Host smart-5d9794e6-aa44-4c50-bbe9-82577421cfa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631168834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
631168834
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.918609466
Short name T120
Test name
Test status
Simulation time 41726190 ps
CPU time 1.34 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:44:52 PM PDT 24
Peak memory 215144 kb
Host smart-67d049e6-e666-4f6e-afbd-a4ff555be5b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918609466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.918609466
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1435220383
Short name T1016
Test name
Test status
Simulation time 23316702 ps
CPU time 0.64 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 203620 kb
Host smart-be1da039-065a-4389-a3d6-dfcefde77dd7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435220383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1435220383
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1450075550
Short name T1096
Test name
Test status
Simulation time 163397026 ps
CPU time 4.26 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 215032 kb
Host smart-cd7c6305-9188-41de-b860-4378f2e254e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450075550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1450075550
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2067340828
Short name T101
Test name
Test status
Simulation time 57838474 ps
CPU time 3.94 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 215216 kb
Host smart-c7061d39-8c8d-4bc4-870a-97def29a741b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067340828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
067340828
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1937730220
Short name T1102
Test name
Test status
Simulation time 131257931 ps
CPU time 3.95 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 216248 kb
Host smart-45e2f6bf-f659-4fc8-90a5-5c6f670f6fb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937730220 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1937730220
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3075375139
Short name T130
Test name
Test status
Simulation time 27848067 ps
CPU time 1.82 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 206940 kb
Host smart-46345a94-75a8-457a-b5bc-6650231c0e25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075375139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3075375139
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3193670551
Short name T1130
Test name
Test status
Simulation time 40088689 ps
CPU time 0.65 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 203652 kb
Host smart-17ef32ad-d917-4d12-8b85-5ea38281a8a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193670551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3193670551
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4151750526
Short name T1127
Test name
Test status
Simulation time 43302439 ps
CPU time 2.65 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 214988 kb
Host smart-c7db1192-688b-4ebb-9380-b86b8a11eb02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151750526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4151750526
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2804636036
Short name T1050
Test name
Test status
Simulation time 466772777 ps
CPU time 7.02 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 215276 kb
Host smart-79ea34fe-5272-4b69-9b1c-7fdc830ef712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804636036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2804636036
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4147475337
Short name T1087
Test name
Test status
Simulation time 81012361 ps
CPU time 1.93 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 216312 kb
Host smart-cec62a9b-a5ef-4981-8c60-4dd5702ff635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147475337 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4147475337
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1570790844
Short name T1072
Test name
Test status
Simulation time 91715311 ps
CPU time 2.9 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 214980 kb
Host smart-60f9b189-df10-4e09-94ad-747c4e431dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570790844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1570790844
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3620484887
Short name T1037
Test name
Test status
Simulation time 40106185 ps
CPU time 0.77 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 203984 kb
Host smart-b09f31bf-dd7d-4b67-9fe6-1285c093962d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620484887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3620484887
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1352572553
Short name T1080
Test name
Test status
Simulation time 45896284 ps
CPU time 2.87 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 214976 kb
Host smart-39e965cf-ca59-42eb-a8b0-8abe859ea310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352572553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1352572553
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3758569822
Short name T1101
Test name
Test status
Simulation time 154476049 ps
CPU time 3.8 seconds
Started Aug 16 04:44:56 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 215292 kb
Host smart-8cfff60f-e8e2-4860-a742-c6de6bdb12f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758569822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3758569822
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3832554577
Short name T1052
Test name
Test status
Simulation time 762060504 ps
CPU time 6.79 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215472 kb
Host smart-8d142a6d-56c7-4f53-826e-e9477704437e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832554577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3832554577
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3177696030
Short name T1034
Test name
Test status
Simulation time 165156370 ps
CPU time 3.26 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 218112 kb
Host smart-0f07efd3-64b7-4cc4-bdd8-d4d6228aa983
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177696030 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3177696030
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.668488741
Short name T1076
Test name
Test status
Simulation time 49104504 ps
CPU time 1.52 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 206908 kb
Host smart-a63dd51b-c3a3-4110-9db9-4e08c6af1887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668488741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.668488741
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3894630452
Short name T1033
Test name
Test status
Simulation time 20134595 ps
CPU time 0.79 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 203744 kb
Host smart-dc573cb0-4bc5-42ca-bcbb-ecdda24318e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894630452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3894630452
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.488348454
Short name T1024
Test name
Test status
Simulation time 59861239 ps
CPU time 3.78 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 215176 kb
Host smart-5a4ab4f0-5b5c-4dbd-a33c-a3acb0c2bb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488348454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.488348454
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3031951537
Short name T115
Test name
Test status
Simulation time 112574236 ps
CPU time 2.76 seconds
Started Aug 16 04:45:06 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 207176 kb
Host smart-ccdd0873-29ed-426f-9702-b85bb57daad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031951537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3031951537
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1152967591
Short name T1056
Test name
Test status
Simulation time 551129628 ps
CPU time 13.82 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:14 PM PDT 24
Peak memory 215112 kb
Host smart-c329c3e4-c48d-4f9c-a881-e50246add781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152967591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1152967591
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.314888477
Short name T117
Test name
Test status
Simulation time 195772237 ps
CPU time 1.71 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 215204 kb
Host smart-1470c99d-7076-4835-a394-42b54321bca4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314888477 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.314888477
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4066308504
Short name T1062
Test name
Test status
Simulation time 34523260 ps
CPU time 1.27 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 206788 kb
Host smart-8f152db6-256c-4f03-b42a-fc10d6019d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066308504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4066308504
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.497318309
Short name T1095
Test name
Test status
Simulation time 15447338 ps
CPU time 0.82 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 203732 kb
Host smart-06a0af1d-a8fe-405f-ada0-314cb5fd1b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497318309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.497318309
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1969832267
Short name T1046
Test name
Test status
Simulation time 117736579 ps
CPU time 3.04 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 215132 kb
Host smart-bdd970e2-fb8d-41d0-92c8-7f53cf8faaf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969832267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1969832267
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.32060634
Short name T1086
Test name
Test status
Simulation time 102807647 ps
CPU time 2.59 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 215240 kb
Host smart-1bc525b9-19ae-4afa-8686-2f8f613ceaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.32060634
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.43300182
Short name T170
Test name
Test status
Simulation time 3163985665 ps
CPU time 12.19 seconds
Started Aug 16 04:45:06 PM PDT 24
Finished Aug 16 04:45:18 PM PDT 24
Peak memory 215880 kb
Host smart-3549c066-0a81-46a9-8514-2476d46d2a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43300182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_
tl_intg_err.43300182
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.521178107
Short name T1071
Test name
Test status
Simulation time 41240357 ps
CPU time 1.56 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215164 kb
Host smart-d00fbfe2-c1c3-439f-8391-70ce95f2a369
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521178107 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.521178107
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2912073324
Short name T1082
Test name
Test status
Simulation time 89015592 ps
CPU time 1.73 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215004 kb
Host smart-81907caf-56b6-40cb-8065-99eff977a25f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912073324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2912073324
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4182229306
Short name T1060
Test name
Test status
Simulation time 29491361 ps
CPU time 0.74 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 203976 kb
Host smart-ec75c93e-7b8d-4dcf-a21e-84a3139a2d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182229306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4182229306
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3105499010
Short name T1017
Test name
Test status
Simulation time 157020044 ps
CPU time 2.92 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 214996 kb
Host smart-c19683b3-4cff-4dab-83f7-491e6eaa1a86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105499010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3105499010
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.685612028
Short name T1085
Test name
Test status
Simulation time 266048053 ps
CPU time 3.78 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 215260 kb
Host smart-9c957b48-e8b4-4722-ac8f-c7a9052a3375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685612028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.685612028
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2167983322
Short name T1122
Test name
Test status
Simulation time 554937182 ps
CPU time 3.89 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 217864 kb
Host smart-3c8d0af3-eb47-4700-9e79-f2a6a9b0bdbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167983322 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2167983322
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1244615649
Short name T1067
Test name
Test status
Simulation time 321653826 ps
CPU time 1.39 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 206996 kb
Host smart-a142d4f7-dfb9-4a43-b380-d55c848dac4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244615649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1244615649
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.805609056
Short name T1035
Test name
Test status
Simulation time 29543124 ps
CPU time 0.73 seconds
Started Aug 16 04:45:05 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 203660 kb
Host smart-d6365104-8f42-4091-8a7c-a13d81887c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805609056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.805609056
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1063177182
Short name T138
Test name
Test status
Simulation time 224556608 ps
CPU time 3.82 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215028 kb
Host smart-bad7cb8a-6286-4dba-be47-17bedfc0c0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063177182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1063177182
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1740205223
Short name T1114
Test name
Test status
Simulation time 619545581 ps
CPU time 4.66 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215348 kb
Host smart-dc670be2-0f85-4cce-a770-4469108c9dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740205223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1740205223
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3906441374
Short name T1126
Test name
Test status
Simulation time 99135063 ps
CPU time 5.72 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 215268 kb
Host smart-9ab0c0a2-2c73-4eee-9358-606d938a345b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906441374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3906441374
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3188534895
Short name T147
Test name
Test status
Simulation time 611688815 ps
CPU time 3.94 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 217040 kb
Host smart-f51728d2-2ec9-481f-ad6d-49941704ff2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188534895 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3188534895
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1701400565
Short name T137
Test name
Test status
Simulation time 110303351 ps
CPU time 1.46 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 206840 kb
Host smart-115290cc-222d-4d63-bfb3-15e3793f0de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701400565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1701400565
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.442012737
Short name T1104
Test name
Test status
Simulation time 92795744 ps
CPU time 0.75 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 203772 kb
Host smart-0c449d2c-697e-4079-823e-507ae5a35a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442012737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.442012737
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4008123768
Short name T1107
Test name
Test status
Simulation time 69580327 ps
CPU time 1.9 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 215664 kb
Host smart-740dcedb-d12b-4607-ba57-dcf9e35c24d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008123768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4008123768
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2280566682
Short name T114
Test name
Test status
Simulation time 404927334 ps
CPU time 5.08 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 216272 kb
Host smart-16efbd54-9a16-4996-88f6-5d458ac60894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280566682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2280566682
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2602871240
Short name T105
Test name
Test status
Simulation time 434862743 ps
CPU time 6.77 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 221312 kb
Host smart-a8bc3531-696e-4762-8363-3586c779914a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602871240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2602871240
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3385812396
Short name T1097
Test name
Test status
Simulation time 304634451 ps
CPU time 3.86 seconds
Started Aug 16 04:45:06 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 217716 kb
Host smart-57b27424-c1fb-4639-b5b6-0fd26a633bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385812396 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3385812396
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1296180045
Short name T118
Test name
Test status
Simulation time 73788797 ps
CPU time 2.34 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 206900 kb
Host smart-5c13b67e-21a9-4428-ae96-3137efe8cc0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296180045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1296180045
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3921442034
Short name T1099
Test name
Test status
Simulation time 25240580 ps
CPU time 0.71 seconds
Started Aug 16 04:45:07 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 203784 kb
Host smart-02b6b688-f88c-4b25-8b53-07167d061f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921442034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3921442034
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3586508079
Short name T146
Test name
Test status
Simulation time 238127637 ps
CPU time 3.32 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 215092 kb
Host smart-81f83c12-8421-47bc-919d-816670b6db40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586508079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3586508079
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3136813388
Short name T103
Test name
Test status
Simulation time 127626239 ps
CPU time 3.52 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 215400 kb
Host smart-87f7ed9c-2d5d-4e29-a9ac-4ee897350bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136813388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3136813388
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1613701283
Short name T148
Test name
Test status
Simulation time 1218722702 ps
CPU time 23.05 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:26 PM PDT 24
Peak memory 220156 kb
Host smart-710a330b-144c-489b-b4f8-9b72b2b51914
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613701283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1613701283
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.200057135
Short name T149
Test name
Test status
Simulation time 61683777 ps
CPU time 1.82 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 215140 kb
Host smart-68f54182-9090-445f-9e43-86a36a0d7ee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200057135 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.200057135
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4132605690
Short name T1018
Test name
Test status
Simulation time 70203915 ps
CPU time 1.32 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 206500 kb
Host smart-bb51ee91-4d0e-49fa-b62e-7ae9647c0d3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132605690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4132605690
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3598830847
Short name T1120
Test name
Test status
Simulation time 26879868 ps
CPU time 0.73 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 203692 kb
Host smart-74fa18f3-215b-4b6e-b7c9-a9a562001dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598830847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3598830847
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2692655987
Short name T1073
Test name
Test status
Simulation time 152835613 ps
CPU time 3.18 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 215040 kb
Host smart-001787f4-425d-411e-ae7e-6e781d26a398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692655987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2692655987
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1150237868
Short name T71
Test name
Test status
Simulation time 357080603 ps
CPU time 3.9 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215532 kb
Host smart-92ba5f22-62d5-44d9-a93c-347370dd29b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150237868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1150237868
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.497092144
Short name T1079
Test name
Test status
Simulation time 873840046 ps
CPU time 22.66 seconds
Started Aug 16 04:45:01 PM PDT 24
Finished Aug 16 04:45:24 PM PDT 24
Peak memory 215228 kb
Host smart-0df1abb3-f8e6-4154-a35e-fe189a9d430f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497092144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.497092144
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2427655562
Short name T113
Test name
Test status
Simulation time 523361247 ps
CPU time 3.95 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 218208 kb
Host smart-1bab296b-8427-4311-bf2d-1498a99d98db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427655562 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2427655562
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1596290809
Short name T1038
Test name
Test status
Simulation time 30306801 ps
CPU time 2.01 seconds
Started Aug 16 04:45:06 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 215160 kb
Host smart-025eb838-9557-479f-b27e-d09d8b474607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596290809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1596290809
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3417136800
Short name T1027
Test name
Test status
Simulation time 22100371 ps
CPU time 0.78 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 203676 kb
Host smart-f2975ac3-62ef-46cf-a0d7-ab18eb3fb597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417136800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3417136800
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1968023736
Short name T1063
Test name
Test status
Simulation time 190647534 ps
CPU time 4.17 seconds
Started Aug 16 04:45:06 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 215108 kb
Host smart-cd8dd8d1-6975-4e0b-a206-1faa99bddaf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968023736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1968023736
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2350321894
Short name T1116
Test name
Test status
Simulation time 463488475 ps
CPU time 2.51 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215428 kb
Host smart-465fb470-2e34-4945-a207-f7e5f282ce3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350321894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2350321894
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1726936264
Short name T1112
Test name
Test status
Simulation time 105022966 ps
CPU time 6.45 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:11 PM PDT 24
Peak memory 215136 kb
Host smart-509cdf08-5a3a-4b49-a86d-8b08688502e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726936264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1726936264
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2964697648
Short name T1012
Test name
Test status
Simulation time 418719751 ps
CPU time 14.54 seconds
Started Aug 16 04:44:56 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 214992 kb
Host smart-309f860f-a662-4078-89f7-77d1be04b84d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964697648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2964697648
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3238192287
Short name T119
Test name
Test status
Simulation time 1846270476 ps
CPU time 23.03 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:45:18 PM PDT 24
Peak memory 206896 kb
Host smart-b6c07fc4-ad4d-4a06-b931-627f2b01abdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238192287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3238192287
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2819887774
Short name T88
Test name
Test status
Simulation time 15302046 ps
CPU time 0.9 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:44:58 PM PDT 24
Peak memory 206716 kb
Host smart-6194c086-df16-4c9e-85e1-5da22b29b607
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819887774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2819887774
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1615180102
Short name T102
Test name
Test status
Simulation time 98234098 ps
CPU time 2.67 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 217784 kb
Host smart-69ba151d-67aa-42df-8ff8-2078d5557a8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615180102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1615180102
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3292010721
Short name T1081
Test name
Test status
Simulation time 916529171 ps
CPU time 1.84 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 206796 kb
Host smart-01ae08ac-9751-4364-bab9-d12fce84695c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292010721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
292010721
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.82929123
Short name T1118
Test name
Test status
Simulation time 15446907 ps
CPU time 0.76 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 203704 kb
Host smart-59db2be8-5806-4638-94b6-8cedc2fb7cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82929123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.82929123
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.987965469
Short name T126
Test name
Test status
Simulation time 268196168 ps
CPU time 2 seconds
Started Aug 16 04:44:52 PM PDT 24
Finished Aug 16 04:44:54 PM PDT 24
Peak memory 215152 kb
Host smart-ce2035ab-86f6-4c12-a16e-4775eff941db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987965469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.987965469
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3703698461
Short name T1084
Test name
Test status
Simulation time 36495135 ps
CPU time 0.68 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 203548 kb
Host smart-d4c2c41a-ecc9-4375-b830-2d2d7e4a8125
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703698461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3703698461
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1092922149
Short name T1049
Test name
Test status
Simulation time 194812527 ps
CPU time 2.86 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:57 PM PDT 24
Peak memory 215132 kb
Host smart-41a85eab-1663-4558-ad11-771a609d2aca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092922149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1092922149
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3188948595
Short name T166
Test name
Test status
Simulation time 2199117424 ps
CPU time 4.71 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:44:56 PM PDT 24
Peak memory 215328 kb
Host smart-373e91cc-6995-4b64-933d-2a0d0b1faf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188948595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
188948595
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2318495126
Short name T143
Test name
Test status
Simulation time 3790717217 ps
CPU time 21.56 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:45:13 PM PDT 24
Peak memory 215228 kb
Host smart-598c59d6-3448-494d-86b9-f50824a25cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318495126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2318495126
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.775898119
Short name T1014
Test name
Test status
Simulation time 15556521 ps
CPU time 0.73 seconds
Started Aug 16 04:45:02 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 204076 kb
Host smart-b57eba36-7f4d-4df5-b129-2267ac26e384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775898119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.775898119
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1206639115
Short name T1106
Test name
Test status
Simulation time 52229300 ps
CPU time 0.78 seconds
Started Aug 16 04:45:03 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 203320 kb
Host smart-7798d046-c58b-4702-97ac-824a587f6898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206639115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1206639115
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1824507785
Short name T1029
Test name
Test status
Simulation time 16537546 ps
CPU time 0.83 seconds
Started Aug 16 04:45:16 PM PDT 24
Finished Aug 16 04:45:17 PM PDT 24
Peak memory 203668 kb
Host smart-777a95dc-4e45-4b4f-8b2e-5d6d6f7d5960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824507785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1824507785
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2577858489
Short name T1019
Test name
Test status
Simulation time 32089921 ps
CPU time 0.73 seconds
Started Aug 16 04:45:14 PM PDT 24
Finished Aug 16 04:45:15 PM PDT 24
Peak memory 203760 kb
Host smart-79debccc-5558-400a-98b2-ea9c8ec426a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577858489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2577858489
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3237778064
Short name T1091
Test name
Test status
Simulation time 44374829 ps
CPU time 0.72 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203680 kb
Host smart-a0f65e06-0c7e-40e1-a8a4-0d370a0d78f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237778064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3237778064
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.704521985
Short name T1023
Test name
Test status
Simulation time 33364302 ps
CPU time 0.78 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203648 kb
Host smart-20629bd6-663f-41cd-a971-e9c0c2ceee26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704521985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.704521985
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1502124631
Short name T1040
Test name
Test status
Simulation time 16023931 ps
CPU time 0.75 seconds
Started Aug 16 04:45:07 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 203652 kb
Host smart-f2d32540-bf40-4f3e-ac25-99a74e7a57a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502124631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1502124631
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1406750584
Short name T1124
Test name
Test status
Simulation time 46468198 ps
CPU time 0.72 seconds
Started Aug 16 04:45:09 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 203760 kb
Host smart-41b9e58b-a115-40c5-823a-18e25b1ffbbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406750584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1406750584
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2992986295
Short name T1055
Test name
Test status
Simulation time 27399687 ps
CPU time 0.77 seconds
Started Aug 16 04:45:07 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 203748 kb
Host smart-bb47f122-e07e-4ad2-9561-82ffa1db8e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992986295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2992986295
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.103825368
Short name T1021
Test name
Test status
Simulation time 32056863 ps
CPU time 0.72 seconds
Started Aug 16 04:45:10 PM PDT 24
Finished Aug 16 04:45:11 PM PDT 24
Peak memory 203752 kb
Host smart-7fff4575-756f-43ce-84eb-ceea790256a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103825368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.103825368
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2115574990
Short name T142
Test name
Test status
Simulation time 1556533209 ps
CPU time 8.6 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:45:04 PM PDT 24
Peak memory 215012 kb
Host smart-825c0f45-bdef-4566-89c1-d07dfc5845e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115574990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2115574990
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2734600081
Short name T1008
Test name
Test status
Simulation time 1851013349 ps
CPU time 37.54 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:36 PM PDT 24
Peak memory 206772 kb
Host smart-d57385ea-4b7a-4618-af08-b5d875f4af4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734600081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2734600081
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1458347785
Short name T89
Test name
Test status
Simulation time 49601162 ps
CPU time 0.92 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 206740 kb
Host smart-a9de706d-9530-4679-ac5b-bdd764679291
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458347785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1458347785
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2703980498
Short name T72
Test name
Test status
Simulation time 278720697 ps
CPU time 3.83 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:58 PM PDT 24
Peak memory 216728 kb
Host smart-8857d0c8-4615-45ec-a55c-c0b7516df973
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703980498 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2703980498
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3981156714
Short name T1090
Test name
Test status
Simulation time 130126005 ps
CPU time 2.03 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 206772 kb
Host smart-917017f6-3625-429e-8600-679c9b69f3a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981156714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
981156714
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3148443119
Short name T1026
Test name
Test status
Simulation time 11000354 ps
CPU time 0.71 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:44:52 PM PDT 24
Peak memory 203736 kb
Host smart-d9320026-2944-4b4d-a1f2-56797b3678fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148443119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
148443119
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2940651809
Short name T122
Test name
Test status
Simulation time 356340036 ps
CPU time 2.11 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 215056 kb
Host smart-42880bec-c584-46d1-bd2a-89606a41528f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940651809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2940651809
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.885676375
Short name T1121
Test name
Test status
Simulation time 36731991 ps
CPU time 0.67 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:44:52 PM PDT 24
Peak memory 203492 kb
Host smart-90e23b8c-6e1a-4886-ae54-50d72bd04df3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885676375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.885676375
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1890312726
Short name T1109
Test name
Test status
Simulation time 23972200 ps
CPU time 1.64 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 215076 kb
Host smart-cfdf2b6e-c54a-4d96-8f6e-7bf93c09bbff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890312726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1890312726
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3736084000
Short name T165
Test name
Test status
Simulation time 306742596 ps
CPU time 5.04 seconds
Started Aug 16 04:44:52 PM PDT 24
Finished Aug 16 04:44:57 PM PDT 24
Peak memory 215316 kb
Host smart-4c3b1aa5-f1de-4b12-b174-eba80f42222d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736084000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
736084000
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1500195620
Short name T70
Test name
Test status
Simulation time 612016553 ps
CPU time 19.53 seconds
Started Aug 16 04:44:51 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 215128 kb
Host smart-40a50ca7-adff-4c38-8c98-5ffac7733493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500195620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1500195620
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.291668137
Short name T1011
Test name
Test status
Simulation time 13215620 ps
CPU time 0.72 seconds
Started Aug 16 04:45:13 PM PDT 24
Finished Aug 16 04:45:14 PM PDT 24
Peak memory 203740 kb
Host smart-66900a80-bbbc-44ab-bca5-887fdfe12d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291668137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.291668137
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4060395833
Short name T1048
Test name
Test status
Simulation time 52494714 ps
CPU time 0.81 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203760 kb
Host smart-4c088891-b0e1-4e25-afa7-1a58f3c29065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060395833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4060395833
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3104546519
Short name T1032
Test name
Test status
Simulation time 22707431 ps
CPU time 0.75 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203772 kb
Host smart-1c53ddb4-9a86-41e7-8287-a58b008f4420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104546519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3104546519
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1274897907
Short name T1044
Test name
Test status
Simulation time 14036220 ps
CPU time 0.68 seconds
Started Aug 16 04:45:09 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 204088 kb
Host smart-c0159ed1-d786-4804-9508-ce3ae6e8519e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274897907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1274897907
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1531702419
Short name T1065
Test name
Test status
Simulation time 42150086 ps
CPU time 0.74 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203604 kb
Host smart-7c8aae7f-83d8-4af0-9ab1-2bba33c7fd74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531702419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1531702419
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1146181109
Short name T1045
Test name
Test status
Simulation time 38164781 ps
CPU time 0.73 seconds
Started Aug 16 04:45:16 PM PDT 24
Finished Aug 16 04:45:17 PM PDT 24
Peak memory 203984 kb
Host smart-5993fd6d-76d4-4e8e-bc19-7fa945b51bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146181109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1146181109
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.169325524
Short name T1128
Test name
Test status
Simulation time 26589256 ps
CPU time 0.76 seconds
Started Aug 16 04:45:16 PM PDT 24
Finished Aug 16 04:45:17 PM PDT 24
Peak memory 203984 kb
Host smart-f8dc5481-a4fa-4976-8c71-8b0fc964599a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169325524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.169325524
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.829285793
Short name T1041
Test name
Test status
Simulation time 10883552 ps
CPU time 0.73 seconds
Started Aug 16 04:45:10 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 203720 kb
Host smart-c0ed0c93-3449-41e9-9af1-cea10437ddc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829285793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.829285793
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.373777409
Short name T1015
Test name
Test status
Simulation time 15114916 ps
CPU time 0.79 seconds
Started Aug 16 04:45:16 PM PDT 24
Finished Aug 16 04:45:17 PM PDT 24
Peak memory 203660 kb
Host smart-4193f1b4-b3cb-41d6-b665-1aeed8e684a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373777409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.373777409
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3749256274
Short name T1108
Test name
Test status
Simulation time 13886333 ps
CPU time 0.74 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 204084 kb
Host smart-7d7c9b17-9953-4416-b798-a554472d8bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749256274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3749256274
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3330260726
Short name T1057
Test name
Test status
Simulation time 4530685604 ps
CPU time 22.03 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:22 PM PDT 24
Peak memory 206948 kb
Host smart-323faaf7-f15a-4abe-a903-a59bc6a5b210
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330260726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3330260726
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.53143701
Short name T127
Test name
Test status
Simulation time 186860790 ps
CPU time 11.78 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:12 PM PDT 24
Peak memory 206808 kb
Host smart-e3f34c66-321f-4bed-aa2a-16bff98b9b10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53143701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.53143701
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3654127786
Short name T1013
Test name
Test status
Simulation time 21453210 ps
CPU time 0.97 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 206712 kb
Host smart-18edd7bd-173c-442a-a150-8cad57e0b85f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654127786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3654127786
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4035016658
Short name T100
Test name
Test status
Simulation time 26452398 ps
CPU time 1.76 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 215172 kb
Host smart-22170bb9-72a2-4eb0-a5c2-11e086a68403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035016658 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4035016658
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2474333272
Short name T1129
Test name
Test status
Simulation time 38521231 ps
CPU time 1.23 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 206844 kb
Host smart-c57d2a34-9aec-44bd-8003-f88ff23be357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474333272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
474333272
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3240758253
Short name T1028
Test name
Test status
Simulation time 17280714 ps
CPU time 0.78 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 203776 kb
Host smart-186283ca-0435-4bb6-b8a8-139c2438ea90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240758253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
240758253
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.279524679
Short name T125
Test name
Test status
Simulation time 115681430 ps
CPU time 1.4 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:00 PM PDT 24
Peak memory 215024 kb
Host smart-ffad4ada-803f-4e06-9437-b059d130b619
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279524679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.279524679
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2625699051
Short name T1030
Test name
Test status
Simulation time 12012234 ps
CPU time 0.68 seconds
Started Aug 16 04:44:52 PM PDT 24
Finished Aug 16 04:44:53 PM PDT 24
Peak memory 203460 kb
Host smart-3b7c050e-0adc-4e96-9553-3f0d9ba94792
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625699051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2625699051
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1237573292
Short name T1094
Test name
Test status
Simulation time 56912751 ps
CPU time 1.89 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 215084 kb
Host smart-87b4dffc-2432-4d35-8879-0c33b7216482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237573292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1237573292
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4216452380
Short name T1119
Test name
Test status
Simulation time 115885492 ps
CPU time 6.41 seconds
Started Aug 16 04:44:56 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 215316 kb
Host smart-3aef8b4c-7af4-4860-9700-0bbf94576236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216452380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4216452380
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2728153237
Short name T1098
Test name
Test status
Simulation time 13193720 ps
CPU time 0.77 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 204064 kb
Host smart-71c3cecc-a0b3-4167-8f3b-9b092c93d4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728153237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2728153237
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.497923028
Short name T1047
Test name
Test status
Simulation time 12461539 ps
CPU time 0.74 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203620 kb
Host smart-03b03a75-c1bd-4e10-b8e8-6fc8d5f9a23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497923028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.497923028
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.578927499
Short name T1075
Test name
Test status
Simulation time 14422548 ps
CPU time 0.76 seconds
Started Aug 16 04:45:07 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 204036 kb
Host smart-5380f0c1-5b96-4fb7-b1bb-9fed7e30d635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578927499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.578927499
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2250166976
Short name T1077
Test name
Test status
Simulation time 19639775 ps
CPU time 0.74 seconds
Started Aug 16 04:45:09 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 203716 kb
Host smart-0553a202-9f3c-4e3a-b8bb-a919895dac79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250166976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2250166976
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2784882477
Short name T1092
Test name
Test status
Simulation time 45212437 ps
CPU time 0.74 seconds
Started Aug 16 04:45:09 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203708 kb
Host smart-d57ca831-8299-44d3-9aa4-ad095595e267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784882477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2784882477
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2654913056
Short name T1020
Test name
Test status
Simulation time 88777603 ps
CPU time 0.72 seconds
Started Aug 16 04:45:09 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 203760 kb
Host smart-41ad7948-dae4-45da-be1c-8ae6017be6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654913056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2654913056
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3803147967
Short name T1059
Test name
Test status
Simulation time 18744324 ps
CPU time 0.75 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203760 kb
Host smart-53a0e74d-e326-4b36-bbf9-56caab708492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803147967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3803147967
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1087423399
Short name T1031
Test name
Test status
Simulation time 12619767 ps
CPU time 0.71 seconds
Started Aug 16 04:45:10 PM PDT 24
Finished Aug 16 04:45:10 PM PDT 24
Peak memory 203652 kb
Host smart-4ea825ad-8a3f-48ca-a388-50ebf044a85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087423399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1087423399
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2600943008
Short name T1117
Test name
Test status
Simulation time 19032962 ps
CPU time 0.69 seconds
Started Aug 16 04:45:06 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 203684 kb
Host smart-a87b9f55-3fbb-4c70-a2cc-7b687b21bd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600943008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2600943008
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3697586342
Short name T1064
Test name
Test status
Simulation time 25369364 ps
CPU time 0.79 seconds
Started Aug 16 04:45:08 PM PDT 24
Finished Aug 16 04:45:09 PM PDT 24
Peak memory 203780 kb
Host smart-1d9c0af6-0080-49df-bbbf-a9784995e523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697586342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3697586342
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3254802912
Short name T1089
Test name
Test status
Simulation time 153696836 ps
CPU time 3.91 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 217456 kb
Host smart-2fd59ab9-4b97-4089-999e-fe9127834f3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254802912 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3254802912
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1335172151
Short name T129
Test name
Test status
Simulation time 36157349 ps
CPU time 2.25 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 206820 kb
Host smart-3be87415-001f-40eb-8c5b-ac272a6b22a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335172151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
335172151
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3706278652
Short name T1042
Test name
Test status
Simulation time 80497359 ps
CPU time 0.71 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 203676 kb
Host smart-08b339f8-e1d1-4fc6-ae9a-4eb70ddaf198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706278652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
706278652
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1850375706
Short name T1043
Test name
Test status
Simulation time 57141164 ps
CPU time 3.5 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:57 PM PDT 24
Peak memory 215048 kb
Host smart-b4a211f6-5662-4fc4-a42e-d0f1c1d215f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850375706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1850375706
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2296358598
Short name T104
Test name
Test status
Simulation time 269258550 ps
CPU time 2.31 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 215272 kb
Host smart-4286e5d6-92fb-4047-bf1c-fe02201e78b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296358598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
296358598
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4175741566
Short name T106
Test name
Test status
Simulation time 883948591 ps
CPU time 19.12 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:18 PM PDT 24
Peak memory 215136 kb
Host smart-9928906a-bff6-4a39-b953-13ba6f2087c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175741566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4175741566
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3071881678
Short name T145
Test name
Test status
Simulation time 58931947 ps
CPU time 1.73 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 215076 kb
Host smart-100df01a-678b-47a4-9e33-49e63b07cc4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071881678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3071881678
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2026653507
Short name T1103
Test name
Test status
Simulation time 146945855 ps
CPU time 2.6 seconds
Started Aug 16 04:44:55 PM PDT 24
Finished Aug 16 04:44:58 PM PDT 24
Peak memory 215036 kb
Host smart-2249285f-2a55-449f-a9af-b73441d93dd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026653507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
026653507
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2495995184
Short name T1054
Test name
Test status
Simulation time 13049579 ps
CPU time 0.74 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:54 PM PDT 24
Peak memory 203664 kb
Host smart-f48f596d-4701-4b89-a450-743cb1f08607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495995184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
495995184
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2611139635
Short name T1088
Test name
Test status
Simulation time 76462301 ps
CPU time 1.93 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:44:59 PM PDT 24
Peak memory 215140 kb
Host smart-79fd6496-9890-4156-acc8-ae2702a1422f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611139635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2611139635
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4076657061
Short name T1053
Test name
Test status
Simulation time 34885286 ps
CPU time 2.14 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 215280 kb
Host smart-58a010d3-633d-4942-b7b2-0a712c046f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076657061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
076657061
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3745096230
Short name T1113
Test name
Test status
Simulation time 210306799 ps
CPU time 12.39 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:45:06 PM PDT 24
Peak memory 215248 kb
Host smart-144299e4-223c-4b55-b39d-c98d8cf95247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745096230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3745096230
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2194719627
Short name T1115
Test name
Test status
Simulation time 1063235628 ps
CPU time 2.6 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 217800 kb
Host smart-d301a74d-5a18-47f3-80ab-1836cd9ece25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194719627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2194719627
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3568302214
Short name T123
Test name
Test status
Simulation time 76046281 ps
CPU time 2.02 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:55 PM PDT 24
Peak memory 215088 kb
Host smart-494f5353-8f59-4917-9442-eafd4c942314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568302214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
568302214
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2217353562
Short name T1009
Test name
Test status
Simulation time 39130168 ps
CPU time 0.74 seconds
Started Aug 16 04:44:54 PM PDT 24
Finished Aug 16 04:44:54 PM PDT 24
Peak memory 203716 kb
Host smart-8357b927-6aba-4fba-a366-bf75d0371560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217353562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
217353562
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2997484993
Short name T1069
Test name
Test status
Simulation time 73126684 ps
CPU time 3.5 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 214984 kb
Host smart-b0e9bf23-dba7-436b-9d44-bc99b8ac19f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997484993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2997484993
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1415110719
Short name T1125
Test name
Test status
Simulation time 690909251 ps
CPU time 4.32 seconds
Started Aug 16 04:44:53 PM PDT 24
Finished Aug 16 04:44:57 PM PDT 24
Peak memory 215384 kb
Host smart-55ea8fb8-440a-4589-8be3-d3e5a8bd2e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415110719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
415110719
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2025038384
Short name T169
Test name
Test status
Simulation time 555961156 ps
CPU time 14.63 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:12 PM PDT 24
Peak memory 215772 kb
Host smart-db733bf9-6d61-4832-9da1-8d1636996250
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025038384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2025038384
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4214998313
Short name T1068
Test name
Test status
Simulation time 234759236 ps
CPU time 2 seconds
Started Aug 16 04:44:56 PM PDT 24
Finished Aug 16 04:44:58 PM PDT 24
Peak memory 206820 kb
Host smart-7c3924cd-d86c-45f7-9286-cd54ded49f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214998313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
214998313
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1284288202
Short name T1074
Test name
Test status
Simulation time 51416165 ps
CPU time 0.76 seconds
Started Aug 16 04:44:57 PM PDT 24
Finished Aug 16 04:44:58 PM PDT 24
Peak memory 203764 kb
Host smart-db9cb846-91fd-4c79-89a1-1d3045034b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284288202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
284288202
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4189235882
Short name T1036
Test name
Test status
Simulation time 102487962 ps
CPU time 2.72 seconds
Started Aug 16 04:45:00 PM PDT 24
Finished Aug 16 04:45:03 PM PDT 24
Peak memory 215000 kb
Host smart-cffb47d5-4b68-4ac5-9bd6-db8c9aa5b9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189235882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4189235882
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3311531999
Short name T1078
Test name
Test status
Simulation time 664057765 ps
CPU time 3.43 seconds
Started Aug 16 04:44:58 PM PDT 24
Finished Aug 16 04:45:02 PM PDT 24
Peak memory 215224 kb
Host smart-78b087ea-6316-4db5-995d-ded1e8ec4887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311531999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
311531999
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2369878670
Short name T1039
Test name
Test status
Simulation time 232400486 ps
CPU time 3.64 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 217348 kb
Host smart-54b66211-9f56-4ebe-aadd-bab4591f7018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369878670 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2369878670
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.54053102
Short name T1110
Test name
Test status
Simulation time 121141191 ps
CPU time 1.73 seconds
Started Aug 16 04:44:59 PM PDT 24
Finished Aug 16 04:45:01 PM PDT 24
Peak memory 206796 kb
Host smart-25d5c49f-5b06-4c51-896a-1fb8d5ff63a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54053102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.54053102
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.491572379
Short name T1010
Test name
Test status
Simulation time 44586365 ps
CPU time 0.71 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:05 PM PDT 24
Peak memory 203652 kb
Host smart-f61e2bea-f873-4fe9-b9c4-028791d29e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491572379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.491572379
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2891757144
Short name T1025
Test name
Test status
Simulation time 48181757 ps
CPU time 2.79 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:07 PM PDT 24
Peak memory 214948 kb
Host smart-ea2d429a-a955-4090-a013-ef824dd7092d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891757144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2891757144
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1001806799
Short name T1058
Test name
Test status
Simulation time 153104881 ps
CPU time 3.8 seconds
Started Aug 16 04:45:04 PM PDT 24
Finished Aug 16 04:45:08 PM PDT 24
Peak memory 215252 kb
Host smart-6a404b8e-04a3-4f22-8039-8851b43f7318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001806799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
001806799
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.265667458
Short name T920
Test name
Test status
Simulation time 18482902 ps
CPU time 0.73 seconds
Started Aug 16 05:49:16 PM PDT 24
Finished Aug 16 05:49:17 PM PDT 24
Peak memory 206348 kb
Host smart-9b671a42-297b-4f10-a8ee-49b77b172eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265667458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.265667458
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1730769730
Short name T172
Test name
Test status
Simulation time 268909802 ps
CPU time 3.69 seconds
Started Aug 16 05:50:24 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 225304 kb
Host smart-f4844e5f-8e75-412a-9de4-4208be6c86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730769730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1730769730
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.398145850
Short name T792
Test name
Test status
Simulation time 15092963 ps
CPU time 0.8 seconds
Started Aug 16 05:49:18 PM PDT 24
Finished Aug 16 05:49:19 PM PDT 24
Peak memory 207408 kb
Host smart-8e2d21eb-623d-4ceb-a5a4-2176989ca1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398145850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.398145850
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3190662188
Short name T919
Test name
Test status
Simulation time 30092267395 ps
CPU time 142.57 seconds
Started Aug 16 05:49:20 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 258352 kb
Host smart-057c6d3e-fcb4-4b36-ae28-8bf65ca14b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190662188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3190662188
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.760115041
Short name T795
Test name
Test status
Simulation time 3457114398 ps
CPU time 40.78 seconds
Started Aug 16 05:49:19 PM PDT 24
Finished Aug 16 05:50:00 PM PDT 24
Peak memory 250176 kb
Host smart-57a7149e-cfbf-4b4f-8046-4f08287af4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760115041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
760115041
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2452889420
Short name T506
Test name
Test status
Simulation time 3093321291 ps
CPU time 13.82 seconds
Started Aug 16 05:49:17 PM PDT 24
Finished Aug 16 05:49:31 PM PDT 24
Peak memory 225420 kb
Host smart-759832b0-fb2c-4af6-b450-1e40d309cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452889420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2452889420
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3430940402
Short name T258
Test name
Test status
Simulation time 114597359289 ps
CPU time 152.54 seconds
Started Aug 16 05:49:18 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 250060 kb
Host smart-8da6916c-9839-423f-8e38-65fdd5363de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430940402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3430940402
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.440301085
Short name T773
Test name
Test status
Simulation time 212647127 ps
CPU time 2.71 seconds
Started Aug 16 05:50:30 PM PDT 24
Finished Aug 16 05:50:33 PM PDT 24
Peak memory 225316 kb
Host smart-606d9a86-e059-4ad3-9c0c-4e8770a9790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440301085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.440301085
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3713691392
Short name T700
Test name
Test status
Simulation time 1548731187 ps
CPU time 20.04 seconds
Started Aug 16 05:49:18 PM PDT 24
Finished Aug 16 05:49:38 PM PDT 24
Peak memory 233604 kb
Host smart-e035f0e1-7ac5-4b34-9fc5-0f1fe7bd2052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713691392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3713691392
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3753394909
Short name T906
Test name
Test status
Simulation time 13691928817 ps
CPU time 11.96 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:50:04 PM PDT 24
Peak memory 233688 kb
Host smart-3b5011c0-84d2-40a4-bf69-ec80252ab2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753394909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3753394909
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1625810119
Short name T23
Test name
Test status
Simulation time 2178150007 ps
CPU time 9.22 seconds
Started Aug 16 05:49:18 PM PDT 24
Finished Aug 16 05:49:27 PM PDT 24
Peak memory 241528 kb
Host smart-1cad7a66-0a0e-4db3-a0eb-f08da5751a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625810119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1625810119
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1702892318
Short name T416
Test name
Test status
Simulation time 235786753 ps
CPU time 4.91 seconds
Started Aug 16 05:52:05 PM PDT 24
Finished Aug 16 05:52:10 PM PDT 24
Peak memory 219556 kb
Host smart-da9db350-45ee-4ce2-8137-80770ea789c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1702892318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1702892318
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1262064518
Short name T717
Test name
Test status
Simulation time 14833919371 ps
CPU time 12.94 seconds
Started Aug 16 05:49:19 PM PDT 24
Finished Aug 16 05:49:33 PM PDT 24
Peak memory 217256 kb
Host smart-ed26a7c7-b4ec-45ed-a597-04158b28866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262064518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1262064518
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3515592209
Short name T528
Test name
Test status
Simulation time 549911563 ps
CPU time 3.41 seconds
Started Aug 16 05:49:19 PM PDT 24
Finished Aug 16 05:49:22 PM PDT 24
Peak memory 217180 kb
Host smart-5a000820-6ba5-4325-bb61-27a8582b2e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515592209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3515592209
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1168782443
Short name T157
Test name
Test status
Simulation time 42623287 ps
CPU time 0.74 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 207204 kb
Host smart-1c8b95ff-dc57-487a-8ccc-d2379f1bbe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168782443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1168782443
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1062378039
Short name T626
Test name
Test status
Simulation time 33077183 ps
CPU time 0.8 seconds
Started Aug 16 05:49:53 PM PDT 24
Finished Aug 16 05:49:54 PM PDT 24
Peak memory 206812 kb
Host smart-a31d683a-a5c3-4c18-aa12-0d02d95859f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062378039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1062378039
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2068478609
Short name T200
Test name
Test status
Simulation time 436297171 ps
CPU time 6.72 seconds
Started Aug 16 05:49:36 PM PDT 24
Finished Aug 16 05:49:43 PM PDT 24
Peak memory 233628 kb
Host smart-5cba2d40-084a-4983-9463-c1dc2aeb3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068478609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2068478609
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2448202385
Short name T845
Test name
Test status
Simulation time 13184089 ps
CPU time 0.77 seconds
Started Aug 16 05:49:30 PM PDT 24
Finished Aug 16 05:49:31 PM PDT 24
Peak memory 205596 kb
Host smart-352a0dbf-3833-4dcb-be59-e94b177ed2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448202385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
448202385
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2212597714
Short name T222
Test name
Test status
Simulation time 11876018545 ps
CPU time 9.43 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:50:02 PM PDT 24
Peak memory 233628 kb
Host smart-8b31e517-38e0-4afd-8c9c-d2f71a75bb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212597714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2212597714
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.239811104
Short name T968
Test name
Test status
Simulation time 17400551 ps
CPU time 0.8 seconds
Started Aug 16 05:49:18 PM PDT 24
Finished Aug 16 05:49:20 PM PDT 24
Peak memory 207380 kb
Host smart-b8b92db6-2276-4c1d-9d11-135f8b2c9956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239811104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.239811104
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3866233665
Short name T768
Test name
Test status
Simulation time 726871629 ps
CPU time 8.42 seconds
Started Aug 16 05:49:30 PM PDT 24
Finished Aug 16 05:49:39 PM PDT 24
Peak memory 233608 kb
Host smart-18f45556-23d9-48b4-be4c-0a822053a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866233665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3866233665
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.761917661
Short name T641
Test name
Test status
Simulation time 218454313184 ps
CPU time 292.45 seconds
Started Aug 16 05:50:12 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 255168 kb
Host smart-62a044bf-db1d-4215-b221-b945353be887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761917661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.761917661
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2300978111
Short name T951
Test name
Test status
Simulation time 70820451136 ps
CPU time 42.11 seconds
Started Aug 16 05:50:21 PM PDT 24
Finished Aug 16 05:51:04 PM PDT 24
Peak memory 249480 kb
Host smart-5565310d-b66e-45c0-be13-f9e30f376cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300978111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2300978111
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2272336044
Short name T489
Test name
Test status
Simulation time 425717487 ps
CPU time 3.93 seconds
Started Aug 16 05:49:26 PM PDT 24
Finished Aug 16 05:49:30 PM PDT 24
Peak memory 234332 kb
Host smart-e1138a3f-366e-4871-807c-0d2ae9c50246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272336044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2272336044
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.630922109
Short name T688
Test name
Test status
Simulation time 7883804134 ps
CPU time 78.08 seconds
Started Aug 16 05:49:27 PM PDT 24
Finished Aug 16 05:50:45 PM PDT 24
Peak memory 262900 kb
Host smart-8c8a1d06-090d-4aef-9473-eb1b5fb525fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630922109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
630922109
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3190067475
Short name T59
Test name
Test status
Simulation time 2034540353 ps
CPU time 11.85 seconds
Started Aug 16 05:49:19 PM PDT 24
Finished Aug 16 05:49:31 PM PDT 24
Peak memory 225336 kb
Host smart-6d70959b-393b-4b01-8e4e-a2efd63aa441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190067475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3190067475
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1727348728
Short name T164
Test name
Test status
Simulation time 7431563505 ps
CPU time 24.81 seconds
Started Aug 16 05:49:42 PM PDT 24
Finished Aug 16 05:50:07 PM PDT 24
Peak memory 225472 kb
Host smart-72e4339e-4ae2-44f4-9d54-d895e47dec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727348728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1727348728
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4152440446
Short name T545
Test name
Test status
Simulation time 191846044 ps
CPU time 3.93 seconds
Started Aug 16 05:49:42 PM PDT 24
Finished Aug 16 05:49:47 PM PDT 24
Peak memory 225288 kb
Host smart-17f96f28-b748-45de-aea2-adabd91519f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152440446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4152440446
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3077146922
Short name T884
Test name
Test status
Simulation time 3874391669 ps
CPU time 5.3 seconds
Started Aug 16 05:49:34 PM PDT 24
Finished Aug 16 05:49:39 PM PDT 24
Peak memory 225492 kb
Host smart-8e0d07db-34ae-447f-810d-4979006d69b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077146922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3077146922
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2133127345
Short name T987
Test name
Test status
Simulation time 1901862676 ps
CPU time 9 seconds
Started Aug 16 05:49:30 PM PDT 24
Finished Aug 16 05:49:39 PM PDT 24
Peak memory 222616 kb
Host smart-75b81f16-ec18-4719-b8f1-2b6b70fcc64b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2133127345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2133127345
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.403648480
Short name T74
Test name
Test status
Simulation time 99528919 ps
CPU time 1.17 seconds
Started Aug 16 05:49:32 PM PDT 24
Finished Aug 16 05:49:34 PM PDT 24
Peak memory 236596 kb
Host smart-87cbbe7c-f31d-444f-9c69-54f178f2e096
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403648480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.403648480
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2649060259
Short name T504
Test name
Test status
Simulation time 111911622148 ps
CPU time 287.14 seconds
Started Aug 16 05:49:30 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 258204 kb
Host smart-72f03f64-d612-43e6-8555-69eb9d2bd466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649060259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2649060259
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.750660680
Short name T1001
Test name
Test status
Simulation time 6398854532 ps
CPU time 36.73 seconds
Started Aug 16 05:50:22 PM PDT 24
Finished Aug 16 05:50:59 PM PDT 24
Peak memory 217260 kb
Host smart-c31988b8-6b60-428e-b882-22eb6ee1b4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750660680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.750660680
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3129591765
Short name T60
Test name
Test status
Simulation time 1473714274 ps
CPU time 5.91 seconds
Started Aug 16 05:49:43 PM PDT 24
Finished Aug 16 05:49:49 PM PDT 24
Peak memory 217196 kb
Host smart-6973fbfd-73aa-4acb-8546-6baebb2baeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129591765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3129591765
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2769779470
Short name T372
Test name
Test status
Simulation time 90308272 ps
CPU time 2.16 seconds
Started Aug 16 05:49:16 PM PDT 24
Finished Aug 16 05:49:18 PM PDT 24
Peak memory 217352 kb
Host smart-36c48a72-f8bd-4ee2-8ab5-6618fd51f9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769779470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2769779470
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1975899600
Short name T556
Test name
Test status
Simulation time 274981787 ps
CPU time 0.78 seconds
Started Aug 16 05:49:42 PM PDT 24
Finished Aug 16 05:49:43 PM PDT 24
Peak memory 206796 kb
Host smart-88718998-8954-4eac-b8de-6a643ad64264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975899600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1975899600
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.281965809
Short name T335
Test name
Test status
Simulation time 1359063059 ps
CPU time 2.25 seconds
Started Aug 16 05:49:27 PM PDT 24
Finished Aug 16 05:49:30 PM PDT 24
Peak memory 225032 kb
Host smart-bdcd5652-a3f4-4db3-a58a-0bfbfbe98734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281965809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.281965809
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1985870617
Short name T464
Test name
Test status
Simulation time 65136654 ps
CPU time 0.7 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 206100 kb
Host smart-6210e8ea-b418-4e52-bd17-8bbe0e3935a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985870617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1985870617
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2143602970
Short name T751
Test name
Test status
Simulation time 180719453 ps
CPU time 2.94 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 233424 kb
Host smart-03fa7c6e-d761-4054-8f6f-809c0f75a252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143602970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2143602970
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.704086991
Short name T770
Test name
Test status
Simulation time 20325784 ps
CPU time 0.72 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:38 PM PDT 24
Peak memory 206184 kb
Host smart-3325bd53-2f99-4241-8fb4-02916907c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704086991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.704086991
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.163322559
Short name T16
Test name
Test status
Simulation time 18252723806 ps
CPU time 73.4 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:51:15 PM PDT 24
Peak memory 251104 kb
Host smart-a144b3be-bfe4-46ec-95bd-abf51479aa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163322559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.163322559
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.620388949
Short name T744
Test name
Test status
Simulation time 9751674608 ps
CPU time 87.52 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:53:01 PM PDT 24
Peak memory 257264 kb
Host smart-e1630e18-0539-43de-b79c-e376cfa6bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620388949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.620388949
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1075273119
Short name T293
Test name
Test status
Simulation time 2449160611 ps
CPU time 9.74 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:47 PM PDT 24
Peak memory 220208 kb
Host smart-c8ceff3d-13ae-4e3c-9449-cb7beac0e5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075273119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1075273119
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3335915352
Short name T552
Test name
Test status
Simulation time 7726956216 ps
CPU time 61.61 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:52:52 PM PDT 24
Peak memory 249908 kb
Host smart-af2de2ff-a6e3-46b5-b010-ab0243b3b38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335915352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3335915352
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.239880646
Short name T723
Test name
Test status
Simulation time 764395080 ps
CPU time 3.18 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:12 PM PDT 24
Peak memory 223812 kb
Host smart-93cd7aee-89e5-49c0-a031-79718022c555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239880646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.239880646
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2799179962
Short name T638
Test name
Test status
Simulation time 13004288989 ps
CPU time 25.85 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:50:33 PM PDT 24
Peak memory 225440 kb
Host smart-01a19787-d4c3-4bb0-84e1-70b5e58e3cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799179962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2799179962
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1347372273
Short name T672
Test name
Test status
Simulation time 3358217128 ps
CPU time 8.13 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:11 PM PDT 24
Peak memory 238484 kb
Host smart-73c09430-6527-478c-a8d5-7144451b1acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347372273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1347372273
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1619006344
Short name T348
Test name
Test status
Simulation time 27359409283 ps
CPU time 6.79 seconds
Started Aug 16 05:49:56 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 225480 kb
Host smart-4e56cc7b-8ace-4770-8ca2-f396bc4e277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619006344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1619006344
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.941259697
Short name T140
Test name
Test status
Simulation time 366843909 ps
CPU time 3.32 seconds
Started Aug 16 05:50:00 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 223968 kb
Host smart-77c2affb-ff2d-495c-a4e8-c669ff5d18e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=941259697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.941259697
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2724729007
Short name T277
Test name
Test status
Simulation time 28271440740 ps
CPU time 257.78 seconds
Started Aug 16 05:50:00 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 250128 kb
Host smart-aadc3291-9618-47f7-99f9-28b51e067ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724729007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2724729007
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2753487470
Short name T303
Test name
Test status
Simulation time 2765619402 ps
CPU time 21.59 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:50:20 PM PDT 24
Peak memory 217340 kb
Host smart-ee310424-4519-4209-8cbd-1a0ecfe7b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753487470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2753487470
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3516608298
Short name T985
Test name
Test status
Simulation time 8483877614 ps
CPU time 6.57 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:05 PM PDT 24
Peak memory 218400 kb
Host smart-639f1200-a932-48ce-a60b-82206ec1cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516608298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3516608298
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1632219910
Short name T775
Test name
Test status
Simulation time 109710483 ps
CPU time 2.03 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:01 PM PDT 24
Peak memory 217140 kb
Host smart-ff9fc6f1-8f12-4e84-a0e2-de2a10ab02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632219910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1632219910
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2357370603
Short name T632
Test name
Test status
Simulation time 31820726 ps
CPU time 0.87 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 207836 kb
Host smart-de6e6367-758a-40f4-b44f-27a5244f5b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357370603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2357370603
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2895973295
Short name T38
Test name
Test status
Simulation time 530092254 ps
CPU time 7.04 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 233580 kb
Host smart-43f1dcb6-4a65-4240-ae4f-b7d5fe2713b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895973295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2895973295
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3265846136
Short name T578
Test name
Test status
Simulation time 90244115 ps
CPU time 0.7 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 205504 kb
Host smart-55fb001e-49d5-4d58-b60c-ca331b3d4155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265846136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3265846136
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2901253674
Short name T946
Test name
Test status
Simulation time 71216261 ps
CPU time 2.19 seconds
Started Aug 16 05:50:00 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 225324 kb
Host smart-8206eb3f-9c1b-4213-afdc-54c9c3afe481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901253674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2901253674
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1836888554
Short name T314
Test name
Test status
Simulation time 48725863 ps
CPU time 0.82 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:49:59 PM PDT 24
Peak memory 207396 kb
Host smart-f9afa210-aa8d-4932-9918-85f14678249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836888554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1836888554
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2935866025
Short name T760
Test name
Test status
Simulation time 16616586901 ps
CPU time 103.94 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:53:12 PM PDT 24
Peak memory 249944 kb
Host smart-48d804c4-bf76-4c6c-a40c-4a3f0d85a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935866025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2935866025
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3064598931
Short name T896
Test name
Test status
Simulation time 13421762345 ps
CPU time 131.41 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:52:11 PM PDT 24
Peak memory 241988 kb
Host smart-b7889ba5-f541-493c-82d9-2f701e88bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064598931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3064598931
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4194775854
Short name T586
Test name
Test status
Simulation time 751201004 ps
CPU time 8.69 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 233428 kb
Host smart-70b51c20-66c8-480a-b578-70dd68cdbcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194775854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4194775854
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3565313740
Short name T642
Test name
Test status
Simulation time 2000968563 ps
CPU time 7.55 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:09 PM PDT 24
Peak memory 225288 kb
Host smart-5d08d5e5-574f-4854-b224-5e76edc47b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565313740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3565313740
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2658311976
Short name T937
Test name
Test status
Simulation time 7538215611 ps
CPU time 56.02 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:58 PM PDT 24
Peak memory 241428 kb
Host smart-36da6c1a-4305-4191-81eb-ab5e9928f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658311976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2658311976
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2997854546
Short name T591
Test name
Test status
Simulation time 2747245775 ps
CPU time 10.45 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:10 PM PDT 24
Peak memory 233708 kb
Host smart-14c4b657-6af2-4dc9-837f-1b22340cc345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997854546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2997854546
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1257189946
Short name T14
Test name
Test status
Simulation time 2007048100 ps
CPU time 4.31 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 233544 kb
Host smart-8abb7816-42b8-4fe7-82ff-bcbf2ce6f27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257189946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1257189946
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1159874924
Short name T694
Test name
Test status
Simulation time 953707688 ps
CPU time 4.97 seconds
Started Aug 16 05:49:55 PM PDT 24
Finished Aug 16 05:50:00 PM PDT 24
Peak memory 219988 kb
Host smart-2747ac14-3808-4001-9558-61a604f72af1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159874924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1159874924
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4247854206
Short name T727
Test name
Test status
Simulation time 3082113380 ps
CPU time 17.42 seconds
Started Aug 16 05:51:32 PM PDT 24
Finished Aug 16 05:51:50 PM PDT 24
Peak memory 217188 kb
Host smart-de4125ad-d18e-426a-bacf-3a3c5ce692aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247854206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4247854206
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1131170979
Short name T562
Test name
Test status
Simulation time 22995051828 ps
CPU time 13.36 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:15 PM PDT 24
Peak memory 218872 kb
Host smart-3c8977aa-759c-4ba3-a445-2ecff3f9eea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131170979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1131170979
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2320869724
Short name T804
Test name
Test status
Simulation time 26800615 ps
CPU time 0.76 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:37 PM PDT 24
Peak memory 206636 kb
Host smart-e795391c-a3ba-40a4-aecb-582e674c013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320869724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2320869724
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1235467807
Short name T974
Test name
Test status
Simulation time 22754299 ps
CPU time 0.77 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:02 PM PDT 24
Peak memory 206996 kb
Host smart-a27944dd-bfb4-4705-b65d-95b361e01b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235467807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1235467807
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2754695936
Short name T708
Test name
Test status
Simulation time 1507572135 ps
CPU time 7.27 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:16 PM PDT 24
Peak memory 223996 kb
Host smart-89f930d8-9a26-4b10-95d1-ad6b621c515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754695936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2754695936
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2431041266
Short name T379
Test name
Test status
Simulation time 12790314 ps
CPU time 0.72 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:50:08 PM PDT 24
Peak memory 206248 kb
Host smart-2307d3fb-5c2f-41dc-ad0e-10156ad4e276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431041266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2431041266
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2383173370
Short name T346
Test name
Test status
Simulation time 1666879463 ps
CPU time 6.67 seconds
Started Aug 16 05:50:35 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 225420 kb
Host smart-cb180072-b3cc-44d1-accd-079b87db31d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383173370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2383173370
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.82410149
Short name T455
Test name
Test status
Simulation time 24905677 ps
CPU time 0.75 seconds
Started Aug 16 05:50:30 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 205108 kb
Host smart-7789bf07-de86-4337-84a4-426bc4800c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82410149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.82410149
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.534074822
Short name T217
Test name
Test status
Simulation time 20774696275 ps
CPU time 152.91 seconds
Started Aug 16 05:50:37 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 258264 kb
Host smart-bc3cb83b-590c-41ae-90a6-f346ff472f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534074822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.534074822
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1544863622
Short name T882
Test name
Test status
Simulation time 17325689251 ps
CPU time 114.15 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 252228 kb
Host smart-30da1a8e-d30e-43fb-b714-b45b844f6331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544863622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1544863622
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1679743078
Short name T45
Test name
Test status
Simulation time 9594295909 ps
CPU time 23.91 seconds
Started Aug 16 05:50:05 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 250188 kb
Host smart-55e56bf3-4731-426e-acb6-b0b395a070b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679743078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1679743078
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2265000525
Short name T408
Test name
Test status
Simulation time 314755299 ps
CPU time 4.56 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:04 PM PDT 24
Peak memory 233484 kb
Host smart-c18966a9-c6e7-45f0-869d-cc0724a6de63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265000525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2265000525
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.43581174
Short name T407
Test name
Test status
Simulation time 2323601370 ps
CPU time 19.18 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:21 PM PDT 24
Peak memory 236728 kb
Host smart-926373d6-1851-4d5e-8db7-1d1b8daf6bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43581174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.43581174
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1499461459
Short name T80
Test name
Test status
Simulation time 1812746391 ps
CPU time 11.74 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:50:41 PM PDT 24
Peak memory 233600 kb
Host smart-eaf3ffd2-f5bd-4a2f-adbb-3eaae1d9b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499461459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1499461459
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2656009321
Short name T469
Test name
Test status
Simulation time 17515880395 ps
CPU time 44.54 seconds
Started Aug 16 05:50:34 PM PDT 24
Finished Aug 16 05:51:19 PM PDT 24
Peak memory 237348 kb
Host smart-680ac3d5-d218-4f11-9559-e843565b5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656009321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2656009321
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.982712862
Short name T246
Test name
Test status
Simulation time 117871209 ps
CPU time 2.71 seconds
Started Aug 16 05:50:04 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 225280 kb
Host smart-b4775a7c-c29e-4e37-8ed8-06d85bf35a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982712862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.982712862
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2475314153
Short name T998
Test name
Test status
Simulation time 371629013 ps
CPU time 3.75 seconds
Started Aug 16 05:50:00 PM PDT 24
Finished Aug 16 05:50:04 PM PDT 24
Peak memory 233492 kb
Host smart-09be23a8-f4a0-42b2-8d7e-e458d4047773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475314153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2475314153
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3279159257
Short name T152
Test name
Test status
Simulation time 3963940670 ps
CPU time 83.41 seconds
Started Aug 16 05:50:10 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 256288 kb
Host smart-b6c72fe5-03a1-4932-ad46-29f1e8177e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279159257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3279159257
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1179097789
Short name T594
Test name
Test status
Simulation time 5199975643 ps
CPU time 25.89 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:35 PM PDT 24
Peak memory 215960 kb
Host smart-09e709b4-5cee-457e-a1c5-633bea1f31cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179097789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1179097789
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3456312457
Short name T657
Test name
Test status
Simulation time 30746371 ps
CPU time 0.69 seconds
Started Aug 16 05:50:04 PM PDT 24
Finished Aug 16 05:50:05 PM PDT 24
Peak memory 206504 kb
Host smart-3e4a3a97-1df6-4726-a488-34b9073ef457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456312457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3456312457
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3986465562
Short name T351
Test name
Test status
Simulation time 173554293 ps
CPU time 2.31 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:40 PM PDT 24
Peak memory 216996 kb
Host smart-c24575f7-ab5b-4865-a093-a591c2a0ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986465562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3986465562
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_upload.1513817204
Short name T196
Test name
Test status
Simulation time 1695734685 ps
CPU time 6.54 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:50:05 PM PDT 24
Peak memory 225388 kb
Host smart-96e987a9-4c61-45da-93d6-e89a16174186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513817204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1513817204
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3937993269
Short name T947
Test name
Test status
Simulation time 14298036 ps
CPU time 0.71 seconds
Started Aug 16 05:50:06 PM PDT 24
Finished Aug 16 05:50:07 PM PDT 24
Peak memory 205664 kb
Host smart-6f8b8208-f09f-4888-895f-4ad8c24502b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937993269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3937993269
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3506357547
Short name T48
Test name
Test status
Simulation time 82085344 ps
CPU time 2.43 seconds
Started Aug 16 05:50:12 PM PDT 24
Finished Aug 16 05:50:14 PM PDT 24
Peak memory 225428 kb
Host smart-ee37cafa-3564-4816-8ba7-951479ade102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506357547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3506357547
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3449382708
Short name T380
Test name
Test status
Simulation time 21088439 ps
CPU time 0.79 seconds
Started Aug 16 05:50:04 PM PDT 24
Finished Aug 16 05:50:05 PM PDT 24
Peak memory 207724 kb
Host smart-bb326698-fb06-43eb-9280-4e803b83b586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449382708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3449382708
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1432600794
Short name T661
Test name
Test status
Simulation time 59608331837 ps
CPU time 72.14 seconds
Started Aug 16 05:50:24 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 250052 kb
Host smart-4d7b15eb-8507-494f-95d3-9d50703d48ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432600794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1432600794
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3123757307
Short name T784
Test name
Test status
Simulation time 58127778176 ps
CPU time 152.59 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:52:40 PM PDT 24
Peak memory 258400 kb
Host smart-a53f12a2-0a85-459f-9152-ac9db92ce2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123757307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3123757307
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2570675024
Short name T819
Test name
Test status
Simulation time 55557261780 ps
CPU time 271.75 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:54:39 PM PDT 24
Peak memory 254620 kb
Host smart-ecd72361-74ad-4188-94b5-bd4d3fbd1402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570675024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2570675024
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2598910329
Short name T519
Test name
Test status
Simulation time 1715496079 ps
CPU time 5.86 seconds
Started Aug 16 05:50:08 PM PDT 24
Finished Aug 16 05:50:14 PM PDT 24
Peak memory 233568 kb
Host smart-6b5a0620-33d6-4f1d-b025-63b4116efcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598910329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2598910329
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3025989892
Short name T454
Test name
Test status
Simulation time 315429994 ps
CPU time 4.04 seconds
Started Aug 16 05:50:20 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 233504 kb
Host smart-e90af9f4-bc49-4c41-877d-9f60a4d60bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025989892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3025989892
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1306343890
Short name T836
Test name
Test status
Simulation time 7472164461 ps
CPU time 9.92 seconds
Started Aug 16 05:50:31 PM PDT 24
Finished Aug 16 05:50:41 PM PDT 24
Peak memory 225544 kb
Host smart-cbaf1c2e-edbf-412c-8ae5-0c8b46934126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306343890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1306343890
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2608553836
Short name T689
Test name
Test status
Simulation time 6973314498 ps
CPU time 15.72 seconds
Started Aug 16 05:50:37 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 240048 kb
Host smart-9547303b-5d4d-4548-a011-42402cadd2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608553836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2608553836
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4139733463
Short name T392
Test name
Test status
Simulation time 2404514496 ps
CPU time 6.22 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:08 PM PDT 24
Peak memory 241836 kb
Host smart-22752810-171f-4c8c-8c49-0d201a723416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139733463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4139733463
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1297378280
Short name T557
Test name
Test status
Simulation time 1921495785 ps
CPU time 7.52 seconds
Started Aug 16 05:50:08 PM PDT 24
Finished Aug 16 05:50:16 PM PDT 24
Peak memory 223512 kb
Host smart-9246b372-6d4a-4da7-b232-7465b5387e16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1297378280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1297378280
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3014019865
Short name T907
Test name
Test status
Simulation time 9826572427 ps
CPU time 58.39 seconds
Started Aug 16 05:50:35 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 241996 kb
Host smart-bf1f4671-5f62-42d4-8bdb-24eeb27ac635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014019865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3014019865
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3857767723
Short name T406
Test name
Test status
Simulation time 1167753485 ps
CPU time 6.59 seconds
Started Aug 16 05:50:04 PM PDT 24
Finished Aug 16 05:50:11 PM PDT 24
Peak memory 217596 kb
Host smart-2fec82ec-448b-4c6e-b32c-667c884254df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857767723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3857767723
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.314788116
Short name T496
Test name
Test status
Simulation time 2570892616 ps
CPU time 10.17 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:52:00 PM PDT 24
Peak memory 217164 kb
Host smart-1a25c2df-65a6-4106-b261-940dc7d55dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314788116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.314788116
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4201104966
Short name T435
Test name
Test status
Simulation time 612907303 ps
CPU time 2.89 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:40 PM PDT 24
Peak memory 216232 kb
Host smart-1fdc8c7a-b172-4656-9ab8-f797dd902244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201104966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4201104966
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2826688022
Short name T131
Test name
Test status
Simulation time 115032784 ps
CPU time 0.78 seconds
Started Aug 16 05:50:06 PM PDT 24
Finished Aug 16 05:50:07 PM PDT 24
Peak memory 206808 kb
Host smart-d9b17abd-300a-451f-b943-7d6422f147ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826688022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2826688022
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.518380487
Short name T888
Test name
Test status
Simulation time 354960727 ps
CPU time 3.84 seconds
Started Aug 16 05:50:35 PM PDT 24
Finished Aug 16 05:50:39 PM PDT 24
Peak memory 225352 kb
Host smart-ae5263af-c059-45a0-9816-6adca7f3f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518380487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.518380487
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2792131168
Short name T924
Test name
Test status
Simulation time 11787655 ps
CPU time 0.69 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:03 PM PDT 24
Peak memory 206108 kb
Host smart-396c764d-24dc-4bc7-b4b1-8b75fdc18892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792131168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2792131168
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.532334713
Short name T505
Test name
Test status
Simulation time 2624699968 ps
CPU time 9.69 seconds
Started Aug 16 05:50:18 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 233684 kb
Host smart-ad457b28-e465-490d-ac4d-01b88cb76008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532334713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.532334713
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.451912831
Short name T66
Test name
Test status
Simulation time 66258240 ps
CPU time 0.79 seconds
Started Aug 16 05:50:11 PM PDT 24
Finished Aug 16 05:50:12 PM PDT 24
Peak memory 207364 kb
Host smart-5e0bef6b-e4c7-4ebe-ba36-28edc1b8155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451912831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.451912831
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2631698045
Short name T874
Test name
Test status
Simulation time 2335984914 ps
CPU time 53.39 seconds
Started Aug 16 05:50:16 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 250964 kb
Host smart-b4b1ef4c-4f79-4309-a0dc-6ab18baadb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631698045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2631698045
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.702599129
Short name T892
Test name
Test status
Simulation time 153586573782 ps
CPU time 722.87 seconds
Started Aug 16 05:50:13 PM PDT 24
Finished Aug 16 06:02:21 PM PDT 24
Peak memory 264972 kb
Host smart-2c48eede-37c1-4666-967c-54ecd7f1b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702599129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.702599129
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3283577968
Short name T423
Test name
Test status
Simulation time 175999000848 ps
CPU time 256.86 seconds
Started Aug 16 05:50:09 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 260332 kb
Host smart-10e2c13b-948d-482e-be17-e7d287b96cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283577968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3283577968
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2559456499
Short name T526
Test name
Test status
Simulation time 7470626949 ps
CPU time 18.79 seconds
Started Aug 16 05:50:09 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 233680 kb
Host smart-9d829fe4-ee07-4f3e-920a-0a1399538bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559456499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2559456499
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3445218671
Short name T262
Test name
Test status
Simulation time 24689772083 ps
CPU time 76.84 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:51:24 PM PDT 24
Peak memory 241544 kb
Host smart-b49c9592-b7cf-4261-9941-4739329467c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445218671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3445218671
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3958204506
Short name T738
Test name
Test status
Simulation time 1076157593 ps
CPU time 9.9 seconds
Started Aug 16 05:50:34 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 225312 kb
Host smart-f0f48394-754c-44e1-a132-24572cf97a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958204506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3958204506
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2887129842
Short name T802
Test name
Test status
Simulation time 11398732237 ps
CPU time 18.83 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:21 PM PDT 24
Peak memory 225300 kb
Host smart-b9dee32c-040b-4371-815f-f25032222af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887129842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2887129842
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.432351519
Short name T904
Test name
Test status
Simulation time 4296391484 ps
CPU time 14.52 seconds
Started Aug 16 05:50:05 PM PDT 24
Finished Aug 16 05:50:20 PM PDT 24
Peak memory 249988 kb
Host smart-4004d138-0590-4b05-ac08-4bf309f4c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432351519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.432351519
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.156613310
Short name T441
Test name
Test status
Simulation time 398669173 ps
CPU time 3.48 seconds
Started Aug 16 05:50:16 PM PDT 24
Finished Aug 16 05:50:20 PM PDT 24
Peak memory 233512 kb
Host smart-11958d02-3cbf-461c-9d82-9de0b5d1915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156613310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.156613310
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1497033277
Short name T486
Test name
Test status
Simulation time 407275416 ps
CPU time 4.7 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:50:12 PM PDT 24
Peak memory 223792 kb
Host smart-def87a56-649d-47aa-b6f2-c6d91a10d83c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1497033277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1497033277
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2496877416
Short name T665
Test name
Test status
Simulation time 1250686010 ps
CPU time 9.32 seconds
Started Aug 16 05:50:33 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 217192 kb
Host smart-64a3dddb-0314-485d-b2bf-d16cd84fd57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496877416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2496877416
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.300303856
Short name T745
Test name
Test status
Simulation time 27518876813 ps
CPU time 19.94 seconds
Started Aug 16 05:50:11 PM PDT 24
Finished Aug 16 05:50:31 PM PDT 24
Peak memory 218908 kb
Host smart-1e68b2c9-04f4-4089-b99f-b1f972e9521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300303856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.300303856
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2031716820
Short name T687
Test name
Test status
Simulation time 211289127 ps
CPU time 3.48 seconds
Started Aug 16 05:50:14 PM PDT 24
Finished Aug 16 05:50:18 PM PDT 24
Peak memory 217152 kb
Host smart-54308ef1-0089-4c22-b42e-cfb1fadf7c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031716820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2031716820
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3722604267
Short name T614
Test name
Test status
Simulation time 48708965 ps
CPU time 0.71 seconds
Started Aug 16 05:50:24 PM PDT 24
Finished Aug 16 05:50:25 PM PDT 24
Peak memory 206840 kb
Host smart-bd81dddd-044e-4ed4-9c86-e0387ff241d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722604267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3722604267
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1218724120
Short name T982
Test name
Test status
Simulation time 3030496341 ps
CPU time 12.55 seconds
Started Aug 16 05:50:31 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 253376 kb
Host smart-6cd90611-b054-4f16-a070-57a3e3bd1503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218724120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1218724120
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1505208284
Short name T612
Test name
Test status
Simulation time 14401260 ps
CPU time 0.75 seconds
Started Aug 16 05:50:09 PM PDT 24
Finished Aug 16 05:50:10 PM PDT 24
Peak memory 206516 kb
Host smart-28f3f815-0939-4abf-8f51-435450318ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505208284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1505208284
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1232897563
Short name T433
Test name
Test status
Simulation time 5290436738 ps
CPU time 6.84 seconds
Started Aug 16 05:50:15 PM PDT 24
Finished Aug 16 05:50:22 PM PDT 24
Peak memory 233696 kb
Host smart-b6bc96af-6f8c-48c9-bce3-da052ccdec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232897563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1232897563
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1406251293
Short name T508
Test name
Test status
Simulation time 51841649 ps
CPU time 0.76 seconds
Started Aug 16 05:50:11 PM PDT 24
Finished Aug 16 05:50:12 PM PDT 24
Peak memory 207400 kb
Host smart-610b0d83-9d61-4254-b1fa-26e9aa8747ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406251293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1406251293
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1282334119
Short name T852
Test name
Test status
Simulation time 16875104112 ps
CPU time 42.17 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 249924 kb
Host smart-85d9e80b-f292-49b3-8029-9f755d585eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282334119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1282334119
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3888165826
Short name T816
Test name
Test status
Simulation time 15445373286 ps
CPU time 48.28 seconds
Started Aug 16 05:50:10 PM PDT 24
Finished Aug 16 05:50:59 PM PDT 24
Peak memory 250216 kb
Host smart-3328c582-1d24-4435-9393-d1a7ee41ea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888165826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3888165826
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1960026316
Short name T515
Test name
Test status
Simulation time 20248302032 ps
CPU time 202.53 seconds
Started Aug 16 05:50:42 PM PDT 24
Finished Aug 16 05:54:05 PM PDT 24
Peak memory 251720 kb
Host smart-3f7a0d48-bd09-402c-993a-4cc74a39f872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960026316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1960026316
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1194433971
Short name T644
Test name
Test status
Simulation time 94130885 ps
CPU time 2.78 seconds
Started Aug 16 05:50:12 PM PDT 24
Finished Aug 16 05:50:20 PM PDT 24
Peak memory 225360 kb
Host smart-311b419f-444c-4b26-8e3b-30fb0369aae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194433971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1194433971
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3242981590
Short name T735
Test name
Test status
Simulation time 3848714534 ps
CPU time 48.81 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 258220 kb
Host smart-332c7125-288f-4896-8b41-155ebcb3fce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242981590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3242981590
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1652536319
Short name T855
Test name
Test status
Simulation time 188702568 ps
CPU time 5.86 seconds
Started Aug 16 05:50:10 PM PDT 24
Finished Aug 16 05:50:16 PM PDT 24
Peak memory 233620 kb
Host smart-2a99fc80-b45b-4bac-81df-df1d3c022c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652536319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1652536319
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.597223075
Short name T805
Test name
Test status
Simulation time 1673024163 ps
CPU time 7.4 seconds
Started Aug 16 05:50:37 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 225312 kb
Host smart-f6e09895-6b9c-45bf-a080-f6a8189a2e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597223075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.597223075
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.53535694
Short name T52
Test name
Test status
Simulation time 353140345 ps
CPU time 3.76 seconds
Started Aug 16 05:50:41 PM PDT 24
Finished Aug 16 05:50:45 PM PDT 24
Peak memory 225384 kb
Host smart-3a24bf63-f570-4ddd-b2d0-3c6e31af9039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53535694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.53535694
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3148583236
Short name T748
Test name
Test status
Simulation time 2108299444 ps
CPU time 11.23 seconds
Started Aug 16 05:50:38 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 239756 kb
Host smart-160c7bbc-8743-471b-812a-06b862f70058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148583236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3148583236
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3550226237
Short name T370
Test name
Test status
Simulation time 1221684242 ps
CPU time 11.09 seconds
Started Aug 16 05:50:10 PM PDT 24
Finished Aug 16 05:50:21 PM PDT 24
Peak memory 222792 kb
Host smart-042f67d9-3fd3-40e6-941a-89def8f9b70e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3550226237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3550226237
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1927499037
Short name T267
Test name
Test status
Simulation time 26755199997 ps
CPU time 123.66 seconds
Started Aug 16 05:50:34 PM PDT 24
Finished Aug 16 05:52:38 PM PDT 24
Peak memory 250296 kb
Host smart-cac45427-5a92-4e06-9a8f-e3234a59bfe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927499037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1927499037
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3167251684
Short name T291
Test name
Test status
Simulation time 1962546105 ps
CPU time 24.74 seconds
Started Aug 16 05:50:11 PM PDT 24
Finished Aug 16 05:50:36 PM PDT 24
Peak memory 217124 kb
Host smart-91dae86e-bc1f-4cc5-928a-4355c30e3ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167251684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3167251684
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.814374562
Short name T383
Test name
Test status
Simulation time 12374883423 ps
CPU time 6.46 seconds
Started Aug 16 05:50:10 PM PDT 24
Finished Aug 16 05:50:17 PM PDT 24
Peak memory 217408 kb
Host smart-bb7289a6-fc62-44ac-a412-7879902ce8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814374562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.814374562
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3151291617
Short name T909
Test name
Test status
Simulation time 146271217 ps
CPU time 1.5 seconds
Started Aug 16 05:50:15 PM PDT 24
Finished Aug 16 05:50:16 PM PDT 24
Peak memory 217208 kb
Host smart-f7d916ae-2e5a-459b-9517-c655ec0b31d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151291617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3151291617
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1566112639
Short name T720
Test name
Test status
Simulation time 353240277 ps
CPU time 0.84 seconds
Started Aug 16 05:50:32 PM PDT 24
Finished Aug 16 05:50:32 PM PDT 24
Peak memory 206864 kb
Host smart-da7ed993-a93b-4e63-9356-1b0aaa1abfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566112639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1566112639
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3070450946
Short name T966
Test name
Test status
Simulation time 2921026646 ps
CPU time 6.01 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:50:45 PM PDT 24
Peak memory 225516 kb
Host smart-5997102a-b24d-461e-8bae-9a42303bbd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070450946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3070450946
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3129584028
Short name T349
Test name
Test status
Simulation time 11878742 ps
CPU time 0.74 seconds
Started Aug 16 05:50:33 PM PDT 24
Finished Aug 16 05:50:33 PM PDT 24
Peak memory 206244 kb
Host smart-ebbdd006-836f-445d-9dce-34f4ae536a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129584028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3129584028
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3146425805
Short name T705
Test name
Test status
Simulation time 100578565 ps
CPU time 2.63 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 225340 kb
Host smart-f35fec5a-1611-4660-ac91-4f042c79318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146425805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3146425805
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1403967726
Short name T809
Test name
Test status
Simulation time 66621543 ps
CPU time 0.8 seconds
Started Aug 16 05:50:16 PM PDT 24
Finished Aug 16 05:50:17 PM PDT 24
Peak memory 207420 kb
Host smart-eebfd827-d6c6-4f86-81af-55cb2b101b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403967726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1403967726
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2749862387
Short name T229
Test name
Test status
Simulation time 13837223753 ps
CPU time 59.15 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:51:28 PM PDT 24
Peak memory 250096 kb
Host smart-b4e0c640-3641-4131-a57a-322362ef8b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749862387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2749862387
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1195635225
Short name T161
Test name
Test status
Simulation time 12239377415 ps
CPU time 138.5 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:52:58 PM PDT 24
Peak memory 257212 kb
Host smart-fcbaaf9d-43ef-4b60-a3e2-3e2167ed5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195635225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1195635225
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.945063419
Short name T654
Test name
Test status
Simulation time 5703676401 ps
CPU time 19.58 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:50:49 PM PDT 24
Peak memory 225636 kb
Host smart-8dcf6518-3673-43a3-8b88-9ac64301707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945063419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.945063419
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2371151114
Short name T984
Test name
Test status
Simulation time 940104641 ps
CPU time 8.51 seconds
Started Aug 16 05:50:15 PM PDT 24
Finished Aug 16 05:50:24 PM PDT 24
Peak memory 240440 kb
Host smart-360a70e8-cc1f-42b2-a194-dc08fb6df107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371151114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2371151114
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.208614440
Short name T220
Test name
Test status
Simulation time 16753113285 ps
CPU time 81.26 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 254512 kb
Host smart-dc357469-c153-46a5-9518-147bc9403112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208614440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.208614440
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1644359474
Short name T756
Test name
Test status
Simulation time 4625301643 ps
CPU time 5.33 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 225456 kb
Host smart-34f88d81-ffb0-4b9b-a832-bf67b1ad2203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644359474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1644359474
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3055602581
Short name T95
Test name
Test status
Simulation time 2310256661 ps
CPU time 14.48 seconds
Started Aug 16 05:50:22 PM PDT 24
Finished Aug 16 05:50:36 PM PDT 24
Peak memory 241620 kb
Host smart-e2a1dde0-9034-4df5-999b-bfb312b90db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055602581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3055602581
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2674225218
Short name T583
Test name
Test status
Simulation time 4583000731 ps
CPU time 21.93 seconds
Started Aug 16 05:50:43 PM PDT 24
Finished Aug 16 05:51:05 PM PDT 24
Peak memory 233624 kb
Host smart-2db7cdab-32fd-4987-ba4d-b612b7bb1f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674225218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2674225218
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1713671772
Short name T523
Test name
Test status
Simulation time 10704692150 ps
CPU time 37.37 seconds
Started Aug 16 05:50:41 PM PDT 24
Finished Aug 16 05:51:18 PM PDT 24
Peak memory 249848 kb
Host smart-e29f97f1-958a-4e33-bbe8-cd103255f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713671772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1713671772
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.843168744
Short name T347
Test name
Test status
Simulation time 725293688 ps
CPU time 4.52 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 221136 kb
Host smart-efc5e7f0-1b6d-47b4-b116-b2245c900ea3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=843168744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.843168744
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2080535535
Short name T613
Test name
Test status
Simulation time 17087073951 ps
CPU time 74 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 252440 kb
Host smart-f77b17a3-5b20-4f11-94d0-95572d61a317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080535535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2080535535
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.151354254
Short name T84
Test name
Test status
Simulation time 545740177 ps
CPU time 7.94 seconds
Started Aug 16 05:50:09 PM PDT 24
Finished Aug 16 05:50:17 PM PDT 24
Peak memory 217212 kb
Host smart-54c58250-a982-40ba-90e7-8f7209efc384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151354254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.151354254
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3114284677
Short name T350
Test name
Test status
Simulation time 5364930835 ps
CPU time 3.51 seconds
Started Aug 16 05:50:16 PM PDT 24
Finished Aug 16 05:50:19 PM PDT 24
Peak memory 217304 kb
Host smart-0715e502-4284-4bec-bf48-12aac53a8fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114284677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3114284677
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2531402064
Short name T308
Test name
Test status
Simulation time 33733912 ps
CPU time 0.68 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:50:37 PM PDT 24
Peak memory 206440 kb
Host smart-8e25fe6c-b6b6-4f0a-b167-9c7c09f2c94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531402064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2531402064
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2102207223
Short name T377
Test name
Test status
Simulation time 323108267 ps
CPU time 0.84 seconds
Started Aug 16 05:50:25 PM PDT 24
Finished Aug 16 05:50:26 PM PDT 24
Peak memory 206812 kb
Host smart-a3dd2092-67fb-4432-8571-6b485ca67dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102207223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2102207223
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1024605636
Short name T254
Test name
Test status
Simulation time 1029837167 ps
CPU time 5.85 seconds
Started Aug 16 05:50:23 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 233604 kb
Host smart-c712636f-0559-4486-bd98-8844c878bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024605636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1024605636
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.190834045
Short name T893
Test name
Test status
Simulation time 1353095661 ps
CPU time 5.1 seconds
Started Aug 16 05:50:24 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 225336 kb
Host smart-fe67204b-9a67-4f67-ae7e-706e8214aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190834045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.190834045
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3952669864
Short name T627
Test name
Test status
Simulation time 41700931 ps
CPU time 0.75 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:50:37 PM PDT 24
Peak memory 207400 kb
Host smart-dcb18096-7f7d-40c5-920e-c19adca7ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952669864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3952669864
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2658164944
Short name T212
Test name
Test status
Simulation time 1895709019 ps
CPU time 14.18 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:55 PM PDT 24
Peak memory 233624 kb
Host smart-7d8b7414-4e1d-4dc1-bd2b-d7b17db22032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658164944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2658164944
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3167111195
Short name T278
Test name
Test status
Simulation time 26652306713 ps
CPU time 80.04 seconds
Started Aug 16 05:50:38 PM PDT 24
Finished Aug 16 05:51:59 PM PDT 24
Peak memory 258072 kb
Host smart-21e722f8-5d34-4ed3-a347-e6fd94648ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167111195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3167111195
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3762033163
Short name T603
Test name
Test status
Simulation time 38400074000 ps
CPU time 125.74 seconds
Started Aug 16 05:50:26 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 253384 kb
Host smart-94f66c47-d841-4729-becd-8945f04bbf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762033163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3762033163
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3407564978
Short name T910
Test name
Test status
Simulation time 14909468758 ps
CPU time 57.86 seconds
Started Aug 16 05:50:38 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 230852 kb
Host smart-1621afd9-db5a-4508-86f7-6a5c04cf41c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407564978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3407564978
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.657062945
Short name T235
Test name
Test status
Simulation time 6283969148 ps
CPU time 8.64 seconds
Started Aug 16 05:50:38 PM PDT 24
Finished Aug 16 05:50:47 PM PDT 24
Peak memory 225456 kb
Host smart-61e683fe-40dc-4517-bd92-6c48eb20094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657062945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.657062945
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.822215850
Short name T467
Test name
Test status
Simulation time 9496175756 ps
CPU time 32.06 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:51:08 PM PDT 24
Peak memory 240608 kb
Host smart-9fd01561-607f-4c93-b3e6-4ee1ad86e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822215850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.822215850
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.315067860
Short name T669
Test name
Test status
Simulation time 104831842 ps
CPU time 1.99 seconds
Started Aug 16 05:50:41 PM PDT 24
Finished Aug 16 05:50:43 PM PDT 24
Peak memory 224444 kb
Host smart-763e80f4-bbb7-4345-b92b-6ee7a18f5ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315067860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.315067860
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2137552498
Short name T823
Test name
Test status
Simulation time 701860214 ps
CPU time 8.53 seconds
Started Aug 16 05:50:38 PM PDT 24
Finished Aug 16 05:50:46 PM PDT 24
Peak memory 223968 kb
Host smart-be61bc7f-f9cd-4cf9-8207-441909ce740a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2137552498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2137552498
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.107563930
Short name T1000
Test name
Test status
Simulation time 66588167 ps
CPU time 1.03 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 207780 kb
Host smart-478e7660-00b2-4efb-9246-3db3aaaba9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107563930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.107563930
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1014143698
Short name T305
Test name
Test status
Simulation time 12516210737 ps
CPU time 25.7 seconds
Started Aug 16 05:50:41 PM PDT 24
Finished Aug 16 05:51:07 PM PDT 24
Peak memory 217236 kb
Host smart-2cd970fb-6dca-421b-988f-1ad2412ca54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014143698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1014143698
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3297694072
Short name T365
Test name
Test status
Simulation time 198864551 ps
CPU time 1.99 seconds
Started Aug 16 05:50:37 PM PDT 24
Finished Aug 16 05:50:39 PM PDT 24
Peak memory 216968 kb
Host smart-017df775-32c5-4b7c-ba1f-d6338cdbaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297694072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3297694072
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2953342274
Short name T917
Test name
Test status
Simulation time 65001542 ps
CPU time 1.09 seconds
Started Aug 16 05:50:32 PM PDT 24
Finished Aug 16 05:50:33 PM PDT 24
Peak memory 208284 kb
Host smart-ecd362da-cf56-437d-97e0-82ef0800b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953342274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2953342274
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.24755470
Short name T550
Test name
Test status
Simulation time 46814092 ps
CPU time 0.87 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:50:37 PM PDT 24
Peak memory 206828 kb
Host smart-d312cfd5-01af-4ba7-a5be-65dc49c678ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24755470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.24755470
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.642087360
Short name T797
Test name
Test status
Simulation time 3530214202 ps
CPU time 13.9 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:54 PM PDT 24
Peak memory 225444 kb
Host smart-6a3f18a0-b494-4e47-9a1b-7a15040751d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642087360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.642087360
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.610749634
Short name T8
Test name
Test status
Simulation time 11556624 ps
CPU time 0.71 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:50:46 PM PDT 24
Peak memory 206296 kb
Host smart-530be9af-3a65-4ef6-a49f-0030902de99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610749634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.610749634
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1739727746
Short name T820
Test name
Test status
Simulation time 2477235159 ps
CPU time 8.73 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:50:38 PM PDT 24
Peak memory 225436 kb
Host smart-ab7dc471-1565-4df0-9567-27fe4fd9dcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739727746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1739727746
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4114993334
Short name T313
Test name
Test status
Simulation time 13959287 ps
CPU time 0.79 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:41 PM PDT 24
Peak memory 207404 kb
Host smart-534c1ca6-4854-47b1-a4c6-d4a9095935a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114993334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4114993334
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2027673373
Short name T509
Test name
Test status
Simulation time 87456798532 ps
CPU time 116.86 seconds
Started Aug 16 05:50:22 PM PDT 24
Finished Aug 16 05:52:19 PM PDT 24
Peak memory 262412 kb
Host smart-c9923b73-04fa-464a-9afd-005055148135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027673373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2027673373
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3971632240
Short name T78
Test name
Test status
Simulation time 5413212787 ps
CPU time 41.84 seconds
Started Aug 16 05:50:44 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 258396 kb
Host smart-f2b77b60-09c2-4cd9-8cc7-4390e6d8e205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971632240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3971632240
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1565999705
Short name T535
Test name
Test status
Simulation time 259787936 ps
CPU time 9.66 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 250020 kb
Host smart-beab07cd-c937-49db-9363-5f7dcebf14f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565999705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1565999705
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.282939981
Short name T343
Test name
Test status
Simulation time 48047928 ps
CPU time 0.94 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:41 PM PDT 24
Peak memory 216912 kb
Host smart-cf9aedad-44ea-4400-8479-21d487cbf895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282939981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.282939981
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.842131853
Short name T931
Test name
Test status
Simulation time 339919096 ps
CPU time 5.6 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 233544 kb
Host smart-7d4e0707-b94b-41b7-9294-0211b97a7c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842131853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.842131853
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2489204331
Short name T673
Test name
Test status
Simulation time 319280390 ps
CPU time 2.03 seconds
Started Aug 16 05:50:42 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 223852 kb
Host smart-4b32a2f6-5842-4f6b-8b7c-1bc3746cc126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489204331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2489204331
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1039546843
Short name T812
Test name
Test status
Simulation time 52871072 ps
CPU time 2.87 seconds
Started Aug 16 05:50:42 PM PDT 24
Finished Aug 16 05:50:45 PM PDT 24
Peak memory 233528 kb
Host smart-3a8633f3-b6ae-4ec4-af88-bf0b318daf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039546843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1039546843
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1532569630
Short name T251
Test name
Test status
Simulation time 1533898986 ps
CPU time 6.22 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:47 PM PDT 24
Peak memory 233540 kb
Host smart-266f943e-9b86-4a92-92ce-71456894d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532569630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1532569630
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.435018105
Short name T736
Test name
Test status
Simulation time 78082641 ps
CPU time 3.92 seconds
Started Aug 16 05:50:38 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 223980 kb
Host smart-b7cd440a-9519-4958-966b-5409e689bea0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=435018105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.435018105
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3476293624
Short name T934
Test name
Test status
Simulation time 18013114678 ps
CPU time 179.42 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:54:00 PM PDT 24
Peak memory 255732 kb
Host smart-cae86924-5703-4563-8db0-636624130a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476293624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3476293624
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3577194586
Short name T776
Test name
Test status
Simulation time 4724421522 ps
CPU time 7.59 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:50:47 PM PDT 24
Peak memory 217320 kb
Host smart-1a32a22c-8ebc-444d-af27-45dfae2e0fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577194586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3577194586
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3697435810
Short name T595
Test name
Test status
Simulation time 654282451 ps
CPU time 1.91 seconds
Started Aug 16 05:50:31 PM PDT 24
Finished Aug 16 05:50:33 PM PDT 24
Peak memory 217108 kb
Host smart-b42592d1-133b-48a6-b3d7-508044693750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697435810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3697435810
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4110496198
Short name T764
Test name
Test status
Simulation time 157289880 ps
CPU time 3.99 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 217140 kb
Host smart-c21363bb-3971-4a4d-a6a2-46e2e2bc8b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110496198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4110496198
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.874986609
Short name T712
Test name
Test status
Simulation time 159500300 ps
CPU time 1.14 seconds
Started Aug 16 05:50:39 PM PDT 24
Finished Aug 16 05:50:41 PM PDT 24
Peak memory 207848 kb
Host smart-da1700f9-cf77-474b-ad69-d8b5df8a264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874986609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.874986609
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1970258554
Short name T828
Test name
Test status
Simulation time 3314650984 ps
CPU time 3.98 seconds
Started Aug 16 05:50:40 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 225376 kb
Host smart-a8cbca18-dbd9-4c5e-a415-108ee3edd78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970258554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1970258554
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1864040935
Short name T354
Test name
Test status
Simulation time 13194246 ps
CPU time 0.74 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:50:47 PM PDT 24
Peak memory 205692 kb
Host smart-b18ea75d-be10-4d7e-8ea0-e3475a29f84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864040935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1864040935
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2598115341
Short name T524
Test name
Test status
Simulation time 826445491 ps
CPU time 12.94 seconds
Started Aug 16 05:50:44 PM PDT 24
Finished Aug 16 05:50:57 PM PDT 24
Peak memory 225292 kb
Host smart-2f91da61-ecee-45f6-bd70-dfef30f3b8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598115341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2598115341
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.94595030
Short name T415
Test name
Test status
Simulation time 31150053 ps
CPU time 0.73 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:28 PM PDT 24
Peak memory 207244 kb
Host smart-854bff86-ebf2-496f-9f34-eb6bc1bd0593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94595030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.94595030
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1215479159
Short name T86
Test name
Test status
Simulation time 21297296313 ps
CPU time 171.49 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:53:39 PM PDT 24
Peak memory 257624 kb
Host smart-8a69973a-6238-46bf-befd-a1457375fbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215479159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1215479159
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4034879385
Short name T883
Test name
Test status
Simulation time 4424338770 ps
CPU time 90.07 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:52:16 PM PDT 24
Peak memory 252164 kb
Host smart-7c492e80-9a58-447c-b02e-99f581afb433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034879385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4034879385
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2185209302
Short name T740
Test name
Test status
Simulation time 573417075 ps
CPU time 3.03 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:50:54 PM PDT 24
Peak memory 233580 kb
Host smart-8218197c-7c42-4ffc-bcaa-89a448d50e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185209302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2185209302
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1977229285
Short name T83
Test name
Test status
Simulation time 11340259211 ps
CPU time 72.9 seconds
Started Aug 16 05:50:54 PM PDT 24
Finished Aug 16 05:52:07 PM PDT 24
Peak memory 258292 kb
Host smart-a0600a1b-dc3e-4ec0-8706-4afc7a4c5aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977229285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1977229285
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3728845812
Short name T192
Test name
Test status
Simulation time 1263355435 ps
CPU time 4.26 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:32 PM PDT 24
Peak memory 233420 kb
Host smart-7da46c71-4477-474b-a357-9b920eca34ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728845812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3728845812
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1649593752
Short name T374
Test name
Test status
Simulation time 239995287 ps
CPU time 2.21 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 224668 kb
Host smart-3c18931a-31c2-4439-8db1-82d5ce944cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649593752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1649593752
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.629662547
Short name T692
Test name
Test status
Simulation time 31821928 ps
CPU time 2.24 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 233116 kb
Host smart-a8b26d4f-b753-49c2-bcf7-1a9d8f81e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629662547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.629662547
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3932043187
Short name T674
Test name
Test status
Simulation time 689595261 ps
CPU time 4.98 seconds
Started Aug 16 05:50:43 PM PDT 24
Finished Aug 16 05:50:48 PM PDT 24
Peak memory 225332 kb
Host smart-6ed1ec73-cd17-4c6f-9e55-c0920ed17ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932043187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3932043187
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2998286640
Short name T695
Test name
Test status
Simulation time 1148125974 ps
CPU time 12.43 seconds
Started Aug 16 05:50:57 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 219800 kb
Host smart-caefa5df-e009-45b5-8254-f170533adc90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2998286640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2998286640
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3649299422
Short name T561
Test name
Test status
Simulation time 4101292183 ps
CPU time 110.12 seconds
Started Aug 16 05:51:11 PM PDT 24
Finished Aug 16 05:53:02 PM PDT 24
Peak memory 257924 kb
Host smart-fe7ae0ee-dd8b-41ab-88bb-e31c3708e2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649299422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3649299422
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.851709675
Short name T759
Test name
Test status
Simulation time 5120273505 ps
CPU time 26.53 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:41 PM PDT 24
Peak memory 217236 kb
Host smart-ed23e5de-330e-417e-9c7c-5f2fc189a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851709675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.851709675
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.677423178
Short name T953
Test name
Test status
Simulation time 678072920 ps
CPU time 4.01 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 217192 kb
Host smart-0943a2b7-4daa-4298-b4e3-f60a2a40529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677423178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.677423178
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2134664173
Short name T450
Test name
Test status
Simulation time 224643323 ps
CPU time 3.52 seconds
Started Aug 16 05:50:56 PM PDT 24
Finished Aug 16 05:51:00 PM PDT 24
Peak memory 217244 kb
Host smart-5f4f85f1-7157-4f69-85b7-dafe0c5dee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134664173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2134664173
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2439928642
Short name T488
Test name
Test status
Simulation time 12348956 ps
CPU time 0.75 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:49 PM PDT 24
Peak memory 206836 kb
Host smart-d53141e4-6a56-4387-8739-8267d6ac6a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439928642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2439928642
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.70442239
Short name T446
Test name
Test status
Simulation time 14073411761 ps
CPU time 7.82 seconds
Started Aug 16 05:50:43 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 233636 kb
Host smart-e6b533f3-3377-45b3-afd6-76e4b91b57f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70442239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.70442239
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3265620016
Short name T324
Test name
Test status
Simulation time 41385045 ps
CPU time 0.85 seconds
Started Aug 16 05:49:32 PM PDT 24
Finished Aug 16 05:49:33 PM PDT 24
Peak memory 206588 kb
Host smart-e5a93778-29f8-4435-9a27-f39dfe067aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265620016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
265620016
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2097721496
Short name T420
Test name
Test status
Simulation time 1095097258 ps
CPU time 6.43 seconds
Started Aug 16 05:49:28 PM PDT 24
Finished Aug 16 05:49:34 PM PDT 24
Peak memory 225444 kb
Host smart-1cfec273-ff24-4bd3-aa26-f257bd4f324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097721496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2097721496
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3660219031
Short name T846
Test name
Test status
Simulation time 21158646 ps
CPU time 0.82 seconds
Started Aug 16 05:50:36 PM PDT 24
Finished Aug 16 05:50:37 PM PDT 24
Peak memory 207356 kb
Host smart-8d20d759-5d6b-432a-9e6d-674f84e41162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660219031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3660219031
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2330105640
Short name T301
Test name
Test status
Simulation time 79918715865 ps
CPU time 167.41 seconds
Started Aug 16 05:49:51 PM PDT 24
Finished Aug 16 05:52:38 PM PDT 24
Peak memory 250228 kb
Host smart-7e86f4ed-cd08-423e-8174-c1f4b8f3d1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330105640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2330105640
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4282678565
Short name T465
Test name
Test status
Simulation time 53638705650 ps
CPU time 78.94 seconds
Started Aug 16 05:49:31 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 254264 kb
Host smart-3d6aac31-1921-4b63-ba20-e43a1e76c5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282678565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4282678565
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.156456832
Short name T554
Test name
Test status
Simulation time 363849347 ps
CPU time 11.11 seconds
Started Aug 16 05:49:30 PM PDT 24
Finished Aug 16 05:49:42 PM PDT 24
Peak memory 239676 kb
Host smart-b0073831-be22-4eb3-b177-49936b10315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156456832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.156456832
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2868215392
Short name T272
Test name
Test status
Simulation time 17980782167 ps
CPU time 131.73 seconds
Started Aug 16 05:49:49 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 266452 kb
Host smart-feae7ad3-823d-4e7a-a8d5-84e7846fd3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868215392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2868215392
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2824348221
Short name T954
Test name
Test status
Simulation time 7157697006 ps
CPU time 37.2 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 225364 kb
Host smart-7c5327f0-4775-4c55-8d99-b1d3b0af7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824348221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2824348221
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1363750027
Short name T247
Test name
Test status
Simulation time 4238498718 ps
CPU time 35.49 seconds
Started Aug 16 05:51:22 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 232776 kb
Host smart-25782146-3c8f-4f03-be9d-1af833cf8708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363750027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1363750027
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3143425299
Short name T3
Test name
Test status
Simulation time 4745771108 ps
CPU time 10.65 seconds
Started Aug 16 05:49:30 PM PDT 24
Finished Aug 16 05:49:41 PM PDT 24
Peak memory 233680 kb
Host smart-01af1bd2-30e9-4bce-8bbb-d0517fc669e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143425299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3143425299
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3155364500
Short name T713
Test name
Test status
Simulation time 4893371467 ps
CPU time 13.42 seconds
Started Aug 16 05:49:27 PM PDT 24
Finished Aug 16 05:49:41 PM PDT 24
Peak memory 241580 kb
Host smart-f8962b43-7b3e-4835-bf31-2c2265572a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155364500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3155364500
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.26873578
Short name T975
Test name
Test status
Simulation time 100490568 ps
CPU time 3.26 seconds
Started Aug 16 05:50:20 PM PDT 24
Finished Aug 16 05:50:23 PM PDT 24
Peak memory 220116 kb
Host smart-89686ed0-16ef-4249-af85-0918dc4ff07c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=26873578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct
.26873578
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3409144223
Short name T76
Test name
Test status
Simulation time 972251560 ps
CPU time 1.35 seconds
Started Aug 16 05:49:25 PM PDT 24
Finished Aug 16 05:49:26 PM PDT 24
Peak memory 236664 kb
Host smart-83fc7da1-342b-44e5-99e7-3491d9c335a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409144223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3409144223
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1569431650
Short name T870
Test name
Test status
Simulation time 5169083003 ps
CPU time 44.46 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:52:13 PM PDT 24
Peak memory 253948 kb
Host smart-ef501c2c-4cec-4e61-bdcc-476fe778acaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569431650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1569431650
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2920028358
Short name T696
Test name
Test status
Simulation time 6745196133 ps
CPU time 13.26 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 217508 kb
Host smart-97c78131-f6d5-4fd6-84ab-ed3aed3b1622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920028358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2920028358
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1934114157
Short name T685
Test name
Test status
Simulation time 5306759873 ps
CPU time 5.27 seconds
Started Aug 16 05:49:27 PM PDT 24
Finished Aug 16 05:49:32 PM PDT 24
Peak memory 217316 kb
Host smart-871a0545-d385-410f-8d1c-455ec816508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934114157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1934114157
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.772524068
Short name T31
Test name
Test status
Simulation time 234391030 ps
CPU time 1.18 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:28 PM PDT 24
Peak memory 216856 kb
Host smart-4df5aa0c-781e-4926-9683-b88ce6b35cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772524068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.772524068
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1586619543
Short name T542
Test name
Test status
Simulation time 75606604 ps
CPU time 0.8 seconds
Started Aug 16 05:49:27 PM PDT 24
Finished Aug 16 05:49:27 PM PDT 24
Peak memory 206832 kb
Host smart-bf21b748-65f5-4e10-b05e-030eb10a1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586619543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1586619543
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2317980398
Short name T573
Test name
Test status
Simulation time 1815921693 ps
CPU time 10.79 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:51:37 PM PDT 24
Peak memory 233172 kb
Host smart-78908f79-686c-4bc5-835e-7ca591a20fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317980398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2317980398
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3300412993
Short name T421
Test name
Test status
Simulation time 38545253 ps
CPU time 0.74 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 205636 kb
Host smart-d50495ec-7523-4786-86e3-eef9e1540b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300412993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3300412993
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.866578837
Short name T914
Test name
Test status
Simulation time 91904366 ps
CPU time 2.88 seconds
Started Aug 16 05:50:53 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 233512 kb
Host smart-5dd06c7f-0681-4f89-999f-72a2bf5e3a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866578837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.866578837
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2355700727
Short name T649
Test name
Test status
Simulation time 46587345 ps
CPU time 0.79 seconds
Started Aug 16 05:51:19 PM PDT 24
Finished Aug 16 05:51:20 PM PDT 24
Peak memory 207480 kb
Host smart-e6e8e100-5c94-450e-8484-8646836f37b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355700727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2355700727
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1113801174
Short name T442
Test name
Test status
Simulation time 6073102838 ps
CPU time 41.03 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 241868 kb
Host smart-a9ecbf22-5195-4b59-a5c6-aa90dfe7571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113801174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1113801174
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4291487603
Short name T749
Test name
Test status
Simulation time 37237029897 ps
CPU time 113.35 seconds
Started Aug 16 05:50:32 PM PDT 24
Finished Aug 16 05:52:25 PM PDT 24
Peak memory 254072 kb
Host smart-5fb4b139-abe6-47ac-8a54-5ba1269fc946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291487603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4291487603
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.241809952
Short name T280
Test name
Test status
Simulation time 282746371 ps
CPU time 8.79 seconds
Started Aug 16 05:50:54 PM PDT 24
Finished Aug 16 05:51:03 PM PDT 24
Peak memory 225332 kb
Host smart-a3981a85-dbbe-4dc9-87eb-1bc790b714dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241809952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.241809952
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1498161146
Short name T668
Test name
Test status
Simulation time 321491076 ps
CPU time 6.22 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:55 PM PDT 24
Peak memory 234768 kb
Host smart-9e0e56b0-8ffd-494f-9f03-7309c0f0dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498161146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1498161146
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3106527227
Short name T382
Test name
Test status
Simulation time 2289398255 ps
CPU time 13.55 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:51:01 PM PDT 24
Peak memory 225412 kb
Host smart-a169caff-7cd4-4c84-8721-117300f6109b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106527227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3106527227
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2264958179
Short name T225
Test name
Test status
Simulation time 745891239 ps
CPU time 14.77 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:51:02 PM PDT 24
Peak memory 241828 kb
Host smart-c810c436-7bce-45ca-a4bc-012f3d677231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264958179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2264958179
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2236512816
Short name T199
Test name
Test status
Simulation time 1009942791 ps
CPU time 4.24 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 233420 kb
Host smart-afb1ac1d-2c6d-47ba-a10d-fa0ac462251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236512816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2236512816
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3934120643
Short name T214
Test name
Test status
Simulation time 41933479529 ps
CPU time 33.96 seconds
Started Aug 16 05:50:44 PM PDT 24
Finished Aug 16 05:51:18 PM PDT 24
Peak memory 251352 kb
Host smart-9c94ab94-fa13-46dc-987f-aa0d7901e0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934120643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3934120643
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.498816541
Short name T344
Test name
Test status
Simulation time 693426952 ps
CPU time 5.75 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:50:57 PM PDT 24
Peak memory 221352 kb
Host smart-a5660a88-1e26-492d-807a-07f450687151
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=498816541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.498816541
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.156976108
Short name T279
Test name
Test status
Simulation time 25457153708 ps
CPU time 72.97 seconds
Started Aug 16 05:50:45 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 257520 kb
Host smart-72ae9989-1b38-4fae-bf20-46f5e7dd267d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156976108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.156976108
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3573778695
Short name T294
Test name
Test status
Simulation time 38105217238 ps
CPU time 22.61 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:46 PM PDT 24
Peak memory 214828 kb
Host smart-1b408305-b937-49ff-9621-c00061e70ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573778695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3573778695
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3207870280
Short name T936
Test name
Test status
Simulation time 15410210967 ps
CPU time 17.58 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:51:06 PM PDT 24
Peak memory 217248 kb
Host smart-34747c3d-af07-4845-b595-db081e64f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207870280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3207870280
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.869361820
Short name T646
Test name
Test status
Simulation time 146106344 ps
CPU time 1.24 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:15 PM PDT 24
Peak memory 216960 kb
Host smart-10178814-3970-4f70-a802-7fd3fc46b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869361820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.869361820
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2304681060
Short name T587
Test name
Test status
Simulation time 92484456 ps
CPU time 1.06 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 206800 kb
Host smart-aba72fe0-329f-4b3f-a69d-ad8d6775ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304681060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2304681060
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1111285000
Short name T905
Test name
Test status
Simulation time 504613286 ps
CPU time 2.85 seconds
Started Aug 16 05:50:43 PM PDT 24
Finished Aug 16 05:50:46 PM PDT 24
Peak memory 233536 kb
Host smart-d7042925-520e-4ede-9835-7fd926dd7466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111285000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1111285000
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1822475525
Short name T69
Test name
Test status
Simulation time 24987490 ps
CPU time 0.75 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 206260 kb
Host smart-bb91e53a-9bdf-4463-8bd3-348f8485f5ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822475525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1822475525
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1787129551
Short name T631
Test name
Test status
Simulation time 44955041 ps
CPU time 0.77 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:50:48 PM PDT 24
Peak memory 206360 kb
Host smart-f9e5b60f-7b71-42e8-abcd-65a168752fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787129551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1787129551
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3459772139
Short name T743
Test name
Test status
Simulation time 30272495927 ps
CPU time 206.6 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 253640 kb
Host smart-e7e2adfa-b1b3-45f9-abbf-f5fd4082d1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459772139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3459772139
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.937317054
Short name T952
Test name
Test status
Simulation time 45031377874 ps
CPU time 183.6 seconds
Started Aug 16 05:50:57 PM PDT 24
Finished Aug 16 05:54:01 PM PDT 24
Peak memory 269548 kb
Host smart-590a503d-4bb9-416d-bbac-d1ea1bc92405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937317054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.937317054
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1786050049
Short name T87
Test name
Test status
Simulation time 236690735324 ps
CPU time 319.81 seconds
Started Aug 16 05:50:52 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 257472 kb
Host smart-ed2b58b5-d3f0-46b5-a9a3-42bb311f99d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786050049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1786050049
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.692750297
Short name T13
Test name
Test status
Simulation time 68699135 ps
CPU time 3.76 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 233536 kb
Host smart-49b53b6c-f370-4371-829a-3b3f6fad9b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692750297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.692750297
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.561085003
Short name T461
Test name
Test status
Simulation time 32873596595 ps
CPU time 82.52 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 258212 kb
Host smart-22330a2d-a977-4a3c-8db4-a6e8484c3527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561085003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.561085003
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3436856611
Short name T522
Test name
Test status
Simulation time 10486565296 ps
CPU time 27.43 seconds
Started Aug 16 05:51:01 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 225368 kb
Host smart-1a4fda6c-7f4f-454c-8288-d3b8b6d24d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436856611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3436856611
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.363242980
Short name T338
Test name
Test status
Simulation time 49177821 ps
CPU time 2.49 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 233272 kb
Host smart-a21b2672-96a8-4511-bc5b-400c0bc0c757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363242980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.363242980
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.103797302
Short name T973
Test name
Test status
Simulation time 244535019 ps
CPU time 2.58 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 233456 kb
Host smart-96f418c6-f53a-4c67-95c4-345f694cf89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103797302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.103797302
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.453546010
Short name T922
Test name
Test status
Simulation time 13479764559 ps
CPU time 7.94 seconds
Started Aug 16 05:50:45 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 225492 kb
Host smart-4b7b5172-1b93-4adf-a128-9e0ffc64a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453546010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.453546010
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1297436596
Short name T667
Test name
Test status
Simulation time 147382197 ps
CPU time 4.91 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:19 PM PDT 24
Peak memory 223480 kb
Host smart-b7973a6e-172e-4ef6-b38d-ca123c598410
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1297436596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1297436596
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3135544243
Short name T660
Test name
Test status
Simulation time 21765559 ps
CPU time 0.82 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 206824 kb
Host smart-bfb96551-43cb-4502-9fa8-06981056e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135544243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3135544243
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.623648663
Short name T555
Test name
Test status
Simulation time 5005222090 ps
CPU time 4.54 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 217324 kb
Host smart-1dd62ea1-9795-49a4-9bca-2ee40f393a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623648663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.623648663
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3115285009
Short name T781
Test name
Test status
Simulation time 466804043 ps
CPU time 1.78 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 217200 kb
Host smart-07400535-aaff-479a-b473-57c8f590add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115285009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3115285009
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1938048958
Short name T546
Test name
Test status
Simulation time 46056960 ps
CPU time 0.84 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:50:48 PM PDT 24
Peak memory 206752 kb
Host smart-f3746c00-ebac-40e9-ba2d-e17e8fd51b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938048958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1938048958
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1786112206
Short name T55
Test name
Test status
Simulation time 1057342583 ps
CPU time 3.61 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:50:55 PM PDT 24
Peak memory 225340 kb
Host smart-72934794-319a-4fcb-a932-f230478c4c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786112206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1786112206
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.601406832
Short name T569
Test name
Test status
Simulation time 13522577 ps
CPU time 0.73 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 205660 kb
Host smart-77fdc079-f78e-464c-b06a-c21a0d70c524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601406832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.601406832
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1641509384
Short name T918
Test name
Test status
Simulation time 81982375 ps
CPU time 2.35 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 225128 kb
Host smart-b23d9732-2065-4152-8ec7-ba53205390ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641509384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1641509384
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.870484745
Short name T570
Test name
Test status
Simulation time 18997643 ps
CPU time 0.72 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:15 PM PDT 24
Peak memory 206528 kb
Host smart-6ba0b9eb-45f0-4df7-851d-a1100ef4066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870484745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.870484745
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1897803114
Short name T444
Test name
Test status
Simulation time 1038289547 ps
CPU time 7.13 seconds
Started Aug 16 05:51:03 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 225260 kb
Host smart-17086fa7-e6f7-4252-9ae5-0aa09cdebb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897803114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1897803114
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4047263452
Short name T950
Test name
Test status
Simulation time 25176597374 ps
CPU time 106.29 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:53:04 PM PDT 24
Peak memory 240320 kb
Host smart-0bdbc6f2-5e3c-41c6-86e7-e6977afc29dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047263452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4047263452
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2455164785
Short name T686
Test name
Test status
Simulation time 2552673300 ps
CPU time 19.74 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:27 PM PDT 24
Peak memory 225500 kb
Host smart-fd67041e-5165-4312-8cdf-a3289570bee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455164785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2455164785
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2818610883
Short name T311
Test name
Test status
Simulation time 39505939 ps
CPU time 0.74 seconds
Started Aug 16 05:51:05 PM PDT 24
Finished Aug 16 05:51:06 PM PDT 24
Peak memory 216568 kb
Host smart-fa8a7273-d892-4d3f-ab62-7bbf9a0b505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818610883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2818610883
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.369674790
Short name T928
Test name
Test status
Simulation time 735108543 ps
CPU time 4.54 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 233260 kb
Host smart-e77acd0e-0b22-4cd2-ad50-5e6dbe2c9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369674790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.369674790
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.21877406
Short name T981
Test name
Test status
Simulation time 8701421937 ps
CPU time 16.29 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:51:07 PM PDT 24
Peak memory 225420 kb
Host smart-36490740-1016-4d46-a9ce-21fa3b85a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21877406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.21877406
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4252985386
Short name T976
Test name
Test status
Simulation time 1715464602 ps
CPU time 4.2 seconds
Started Aug 16 05:51:01 PM PDT 24
Finished Aug 16 05:51:06 PM PDT 24
Peak memory 233576 kb
Host smart-3eacfa2b-cb44-462c-9a24-29c6d32d2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252985386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4252985386
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1131539574
Short name T180
Test name
Test status
Simulation time 1271777970 ps
CPU time 4.85 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:32 PM PDT 24
Peak memory 234804 kb
Host smart-13cbb526-2ec5-4cae-9b8e-33a63b099527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131539574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1131539574
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.102730220
Short name T46
Test name
Test status
Simulation time 1234270924 ps
CPU time 8.54 seconds
Started Aug 16 05:51:22 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 221820 kb
Host smart-39f24943-671b-47f1-a46f-7479ce168814
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=102730220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.102730220
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1078439527
Short name T21
Test name
Test status
Simulation time 482715170 ps
CPU time 1.07 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 207900 kb
Host smart-ed86722a-9bc0-403c-95b6-35363917e7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078439527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1078439527
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3743037324
Short name T426
Test name
Test status
Simulation time 162167619 ps
CPU time 2.71 seconds
Started Aug 16 05:50:44 PM PDT 24
Finished Aug 16 05:50:46 PM PDT 24
Peak memory 217488 kb
Host smart-23840874-5606-49c6-be70-ab7e0f7b0dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743037324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3743037324
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2786283496
Short name T92
Test name
Test status
Simulation time 970091528 ps
CPU time 5.57 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 216952 kb
Host smart-d42c9978-c46d-42cd-84f4-57017a067619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786283496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2786283496
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2618925621
Short name T1002
Test name
Test status
Simulation time 418125961 ps
CPU time 2.81 seconds
Started Aug 16 05:52:24 PM PDT 24
Finished Aug 16 05:52:27 PM PDT 24
Peak memory 216740 kb
Host smart-9238629a-f4df-4e7b-90cf-42c8dab10812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618925621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2618925621
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1207363287
Short name T912
Test name
Test status
Simulation time 79101848 ps
CPU time 0.76 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 206844 kb
Host smart-8af1ae30-b845-465f-a136-1564f23204e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207363287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1207363287
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1081638486
Short name T806
Test name
Test status
Simulation time 2112290847 ps
CPU time 9.89 seconds
Started Aug 16 05:50:58 PM PDT 24
Finished Aug 16 05:51:08 PM PDT 24
Peak memory 234480 kb
Host smart-30bb3398-3462-4fa3-8a7e-c0a0f912ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081638486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1081638486
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3938015431
Short name T417
Test name
Test status
Simulation time 83971306 ps
CPU time 0.78 seconds
Started Aug 16 05:51:16 PM PDT 24
Finished Aug 16 05:51:17 PM PDT 24
Peak memory 206264 kb
Host smart-f46fa1f9-d383-4f6f-929a-33697fedea98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938015431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3938015431
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.483806158
Short name T174
Test name
Test status
Simulation time 224005234 ps
CPU time 2.59 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:11 PM PDT 24
Peak memory 233540 kb
Host smart-28ebc1a4-8261-46ae-b4e9-9d7eef43f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483806158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.483806158
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2032088774
Short name T394
Test name
Test status
Simulation time 61377824 ps
CPU time 0.76 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 207640 kb
Host smart-0830d993-2a73-4f0e-bc08-7e4be6d36702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032088774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2032088774
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.412571477
Short name T637
Test name
Test status
Simulation time 78551486327 ps
CPU time 140.94 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 253240 kb
Host smart-444538bf-92f0-41ba-9dd5-b7bd88ec5e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412571477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.412571477
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.451910533
Short name T134
Test name
Test status
Simulation time 137628533139 ps
CPU time 458.48 seconds
Started Aug 16 05:50:54 PM PDT 24
Finished Aug 16 05:58:33 PM PDT 24
Peak memory 266060 kb
Host smart-c4a4017b-413f-42c0-b304-3573283d682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451910533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.451910533
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4087428459
Short name T679
Test name
Test status
Simulation time 11521011994 ps
CPU time 64.94 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 250156 kb
Host smart-eebd2340-9bc1-4132-959e-84d37ec06d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087428459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4087428459
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.290503180
Short name T58
Test name
Test status
Simulation time 1342338866 ps
CPU time 15.66 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:51:05 PM PDT 24
Peak memory 238400 kb
Host smart-d82f619e-21d6-478f-afd8-d9241d730fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290503180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.290503180
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2096400566
Short name T521
Test name
Test status
Simulation time 87216065566 ps
CPU time 112.82 seconds
Started Aug 16 05:50:45 PM PDT 24
Finished Aug 16 05:52:38 PM PDT 24
Peak memory 240144 kb
Host smart-6a81b19f-6b04-47ea-b852-45c68eff390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096400566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2096400566
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.457499887
Short name T61
Test name
Test status
Simulation time 213627216 ps
CPU time 4.55 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:04 PM PDT 24
Peak memory 219536 kb
Host smart-fbf29724-82f8-485c-bba3-e30aeef3f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457499887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.457499887
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2508419834
Short name T499
Test name
Test status
Simulation time 8217804023 ps
CPU time 80.76 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 241664 kb
Host smart-06799cde-c1c6-482c-aa5b-d93ffc9148d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508419834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2508419834
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.86038499
Short name T628
Test name
Test status
Simulation time 781843034 ps
CPU time 3.2 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:26 PM PDT 24
Peak memory 222720 kb
Host smart-582976d4-c9cf-430c-a1ac-1be70d552cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86038499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.86038499
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4099327324
Short name T389
Test name
Test status
Simulation time 2493170446 ps
CPU time 3.89 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:54 PM PDT 24
Peak memory 225420 kb
Host smart-2f5f31ac-c05d-431a-b475-03329894a1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099327324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4099327324
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2991583910
Short name T139
Test name
Test status
Simulation time 1088758516 ps
CPU time 11.85 seconds
Started Aug 16 05:51:18 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 221496 kb
Host smart-71d6405b-a514-4ae0-b8df-93ab792b8d5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2991583910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2991583910
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2409482322
Short name T798
Test name
Test status
Simulation time 36245211614 ps
CPU time 416.22 seconds
Started Aug 16 05:50:45 PM PDT 24
Finished Aug 16 05:57:41 PM PDT 24
Peak memory 269776 kb
Host smart-236f7990-ce70-4428-abe9-5c1981ee246d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409482322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2409482322
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1266662735
Short name T716
Test name
Test status
Simulation time 2199700812 ps
CPU time 26.71 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:51:17 PM PDT 24
Peak memory 217576 kb
Host smart-3653eb05-459e-49a8-920c-21a15e389860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266662735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1266662735
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1204600894
Short name T699
Test name
Test status
Simulation time 2665283212 ps
CPU time 7.28 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:07 PM PDT 24
Peak memory 217248 kb
Host smart-908fd9e1-c0aa-4a92-ad3a-7f4c6252ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204600894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1204600894
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.408158363
Short name T445
Test name
Test status
Simulation time 94649255 ps
CPU time 1.04 seconds
Started Aug 16 05:51:12 PM PDT 24
Finished Aug 16 05:51:13 PM PDT 24
Peak memory 208364 kb
Host smart-6f78f488-de67-4d21-bea1-3974bbdda7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408158363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.408158363
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3869035146
Short name T337
Test name
Test status
Simulation time 357239396 ps
CPU time 0.8 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:15 PM PDT 24
Peak memory 206876 kb
Host smart-a1365301-1225-4587-a34f-8f5304f434b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869035146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3869035146
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3720258304
Short name T997
Test name
Test status
Simulation time 471443788 ps
CPU time 3.84 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:08 PM PDT 24
Peak memory 233600 kb
Host smart-5f31f580-ddf5-49bf-81cb-7582986201f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720258304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3720258304
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1554372377
Short name T316
Test name
Test status
Simulation time 19497606 ps
CPU time 0.69 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:00 PM PDT 24
Peak memory 205552 kb
Host smart-f07c80b0-0f3a-4fc8-a4e0-58ebace8e76d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554372377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1554372377
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1828592805
Short name T479
Test name
Test status
Simulation time 442557925 ps
CPU time 3.86 seconds
Started Aug 16 05:50:44 PM PDT 24
Finished Aug 16 05:50:48 PM PDT 24
Peak memory 225384 kb
Host smart-f5dccefe-f272-4f2f-b664-4a50c2bb8387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828592805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1828592805
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.902829151
Short name T800
Test name
Test status
Simulation time 46236748 ps
CPU time 0.79 seconds
Started Aug 16 05:50:44 PM PDT 24
Finished Aug 16 05:50:45 PM PDT 24
Peak memory 207452 kb
Host smart-ad185d45-20f8-46cb-ab06-b612485f5d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902829151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.902829151
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2627204773
Short name T929
Test name
Test status
Simulation time 9610023226 ps
CPU time 52.36 seconds
Started Aug 16 05:51:17 PM PDT 24
Finished Aug 16 05:52:10 PM PDT 24
Peak memory 218820 kb
Host smart-82688fbc-a1e1-4a78-9466-633fbf86852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627204773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2627204773
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1077373648
Short name T621
Test name
Test status
Simulation time 4732729982 ps
CPU time 73.66 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 236808 kb
Host smart-50681198-8b79-49e5-84a0-6b0e79f2995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077373648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1077373648
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.59920681
Short name T323
Test name
Test status
Simulation time 675827048 ps
CPU time 7.57 seconds
Started Aug 16 05:50:43 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 225424 kb
Host smart-352c75bd-4a36-4570-a0fb-08582a235a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59920681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.59920681
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2933276745
Short name T900
Test name
Test status
Simulation time 32467379 ps
CPU time 0.7 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:50:47 PM PDT 24
Peak memory 216296 kb
Host smart-00528dd4-0c49-4d06-bbd3-098028ebb3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933276745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2933276745
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4025319480
Short name T428
Test name
Test status
Simulation time 4497582804 ps
CPU time 19.38 seconds
Started Aug 16 05:51:07 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 225512 kb
Host smart-fc652e38-150a-4d4c-badc-0b85fd02848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025319480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4025319480
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.575073528
Short name T398
Test name
Test status
Simulation time 692447875 ps
CPU time 12.42 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:38 PM PDT 24
Peak memory 239512 kb
Host smart-c09fbedb-cc25-4cbb-89d4-fbc286440077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575073528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.575073528
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1859160169
Short name T538
Test name
Test status
Simulation time 5596206315 ps
CPU time 9.61 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:51:01 PM PDT 24
Peak memory 225444 kb
Host smart-144f3b5c-8149-4a43-b61f-72b6984832fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859160169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1859160169
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2041775400
Short name T899
Test name
Test status
Simulation time 1503277035 ps
CPU time 2.93 seconds
Started Aug 16 05:51:11 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 225328 kb
Host smart-5696daec-b623-48f9-ba23-a52e7e958fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041775400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2041775400
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4272451355
Short name T319
Test name
Test status
Simulation time 2926101970 ps
CPU time 7.25 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 222012 kb
Host smart-135bd8d5-30a6-4cb4-8264-bba697115c35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4272451355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4272451355
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4290160525
Short name T964
Test name
Test status
Simulation time 8847218385 ps
CPU time 64.93 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 250180 kb
Host smart-ab22e938-0187-426a-9ead-4e497020967e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290160525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4290160525
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.31710324
Short name T986
Test name
Test status
Simulation time 1024579498 ps
CPU time 9.34 seconds
Started Aug 16 05:50:46 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 217352 kb
Host smart-8502fc33-9560-4831-a48b-4abf49abd30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31710324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.31710324
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2420322103
Short name T625
Test name
Test status
Simulation time 882697864 ps
CPU time 3.32 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 217100 kb
Host smart-f4c1e5ee-e423-4faf-a5da-8ebc89e282ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420322103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2420322103
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3070601381
Short name T396
Test name
Test status
Simulation time 212505281 ps
CPU time 1.18 seconds
Started Aug 16 05:50:47 PM PDT 24
Finished Aug 16 05:50:49 PM PDT 24
Peak memory 208296 kb
Host smart-bf823177-b1d1-498b-a98d-50ae6636a148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070601381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3070601381
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1995280911
Short name T358
Test name
Test status
Simulation time 187218622 ps
CPU time 0.88 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 206840 kb
Host smart-9ce92675-6207-41cf-b5da-236b8ef7d0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995280911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1995280911
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3786818420
Short name T553
Test name
Test status
Simulation time 1246907984 ps
CPU time 8.2 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 233540 kb
Host smart-9cd9c455-da6d-46d2-a81e-46e3662eac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786818420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3786818420
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3868462949
Short name T514
Test name
Test status
Simulation time 43156387 ps
CPU time 0.7 seconds
Started Aug 16 05:52:23 PM PDT 24
Finished Aug 16 05:52:24 PM PDT 24
Peak memory 204516 kb
Host smart-88d593c3-f355-425e-9c5e-3796ca5599b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868462949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3868462949
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.216704948
Short name T718
Test name
Test status
Simulation time 5392228845 ps
CPU time 6.83 seconds
Started Aug 16 05:52:52 PM PDT 24
Finished Aug 16 05:52:59 PM PDT 24
Peak memory 225248 kb
Host smart-83756069-ecef-4848-b428-835d925f7563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216704948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.216704948
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.820698392
Short name T762
Test name
Test status
Simulation time 14090505 ps
CPU time 0.77 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 207396 kb
Host smart-d14d1641-5506-407a-8b4d-b652d8733e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820698392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.820698392
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.609898926
Short name T237
Test name
Test status
Simulation time 3806747042 ps
CPU time 65.3 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 256444 kb
Host smart-f68b7fb6-c260-4c41-b179-6da3aeced9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609898926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.609898926
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3022995302
Short name T808
Test name
Test status
Simulation time 123499806870 ps
CPU time 126.69 seconds
Started Aug 16 05:50:55 PM PDT 24
Finished Aug 16 05:53:02 PM PDT 24
Peak memory 254288 kb
Host smart-1e2d21a4-8155-48a3-aac0-e141abe90d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022995302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3022995302
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3104036033
Short name T619
Test name
Test status
Simulation time 38164085727 ps
CPU time 208.42 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:54:28 PM PDT 24
Peak memory 258264 kb
Host smart-8e3c1157-c5e0-4418-aafa-90499e1f1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104036033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3104036033
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3540949004
Short name T967
Test name
Test status
Simulation time 1094189708 ps
CPU time 21.39 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:51:11 PM PDT 24
Peak memory 241596 kb
Host smart-dd7ed737-b9a0-44d5-ae11-6019f51e0730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540949004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3540949004
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2520364537
Short name T250
Test name
Test status
Simulation time 245172776420 ps
CPU time 220.95 seconds
Started Aug 16 05:50:56 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 258016 kb
Host smart-645b0949-6fb3-4063-ab23-057ec5fa634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520364537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2520364537
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2458493803
Short name T663
Test name
Test status
Simulation time 1967042619 ps
CPU time 23.38 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:46 PM PDT 24
Peak memory 223104 kb
Host smart-852f67d6-9e28-4871-ad5f-41406d47bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458493803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2458493803
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3091784527
Short name T309
Test name
Test status
Simulation time 6231967706 ps
CPU time 5.83 seconds
Started Aug 16 05:52:24 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 225248 kb
Host smart-bd07a8d8-d925-496d-b5ee-8f2b3c5e3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091784527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3091784527
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3818052891
Short name T640
Test name
Test status
Simulation time 496569980 ps
CPU time 6.3 seconds
Started Aug 16 05:52:24 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 233368 kb
Host smart-0ca92699-d574-4a46-85cf-dd995f409cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818052891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3818052891
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1288312076
Short name T602
Test name
Test status
Simulation time 770891485 ps
CPU time 9.46 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:51:00 PM PDT 24
Peak memory 249080 kb
Host smart-9c073815-2b0f-4b78-8ad1-e0920474543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288312076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1288312076
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4278599056
Short name T676
Test name
Test status
Simulation time 686584804 ps
CPU time 4.43 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 224076 kb
Host smart-8a977fba-3778-4e98-b1d9-040ca4e51c53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4278599056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4278599056
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2372890227
Short name T889
Test name
Test status
Simulation time 1486824819 ps
CPU time 9.35 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:59 PM PDT 24
Peak memory 217168 kb
Host smart-c98ed6ab-ff08-4a6f-9adc-0a94de8f8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372890227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2372890227
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1704144176
Short name T958
Test name
Test status
Simulation time 2049182407 ps
CPU time 1.73 seconds
Started Aug 16 05:52:43 PM PDT 24
Finished Aug 16 05:52:44 PM PDT 24
Peak memory 216736 kb
Host smart-e84e2330-9e78-4ae8-8dc2-5501bda5b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704144176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1704144176
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1447140338
Short name T1003
Test name
Test status
Simulation time 441213615 ps
CPU time 1.93 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 217220 kb
Host smart-fec3effc-d274-4476-879d-2115f9f216b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447140338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1447140338
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1647477083
Short name T321
Test name
Test status
Simulation time 400397093 ps
CPU time 0.91 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 207836 kb
Host smart-6ccb185b-0a13-4076-a858-66b7354a4cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647477083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1647477083
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1453254983
Short name T193
Test name
Test status
Simulation time 359157953 ps
CPU time 7.24 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:57 PM PDT 24
Peak memory 233516 kb
Host smart-6978a9ee-334a-46eb-ae7e-bf5fc90059e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453254983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1453254983
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1546570404
Short name T733
Test name
Test status
Simulation time 47124074 ps
CPU time 0.76 seconds
Started Aug 16 05:50:52 PM PDT 24
Finished Aug 16 05:50:52 PM PDT 24
Peak memory 206432 kb
Host smart-7b1be0ca-47a4-4562-bf88-96955afbc26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546570404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1546570404
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2132341536
Short name T842
Test name
Test status
Simulation time 6731443257 ps
CPU time 18.46 seconds
Started Aug 16 05:52:04 PM PDT 24
Finished Aug 16 05:52:22 PM PDT 24
Peak memory 233756 kb
Host smart-76c78542-d808-455d-8100-0d3519188302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132341536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2132341536
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2128160777
Short name T796
Test name
Test status
Simulation time 14589614 ps
CPU time 0.77 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:00 PM PDT 24
Peak memory 207392 kb
Host smart-5602af0a-d8ae-409f-8bcc-1553fec0bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128160777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2128160777
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3235710032
Short name T944
Test name
Test status
Simulation time 44200037957 ps
CPU time 223.51 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 257168 kb
Host smart-caaa3ae3-86d4-4427-b61e-283d05b8200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235710032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3235710032
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1122859836
Short name T284
Test name
Test status
Simulation time 256512434 ps
CPU time 8.7 seconds
Started Aug 16 05:52:19 PM PDT 24
Finished Aug 16 05:52:27 PM PDT 24
Peak memory 234728 kb
Host smart-0e2197fe-35a7-4dc9-8d33-d2203fc6b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122859836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1122859836
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.590851694
Short name T507
Test name
Test status
Simulation time 94420542793 ps
CPU time 84.43 seconds
Started Aug 16 05:51:31 PM PDT 24
Finished Aug 16 05:52:55 PM PDT 24
Peak memory 252236 kb
Host smart-0b08f98d-265c-4750-a2f5-79631921a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590851694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.590851694
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4187479721
Short name T472
Test name
Test status
Simulation time 1089153496 ps
CPU time 5.54 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 225340 kb
Host smart-cf2cd68e-ff9a-4c57-b846-0bed508f51fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187479721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4187479721
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4247521875
Short name T747
Test name
Test status
Simulation time 4149506143 ps
CPU time 25.83 seconds
Started Aug 16 05:50:52 PM PDT 24
Finished Aug 16 05:51:18 PM PDT 24
Peak memory 233568 kb
Host smart-fc8cbf4f-3d8b-4a99-a0d2-0b61762a0c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247521875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4247521875
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4260934783
Short name T558
Test name
Test status
Simulation time 3308813705 ps
CPU time 15.89 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:51:05 PM PDT 24
Peak memory 241568 kb
Host smart-e4be20f1-7ba5-4443-b677-601ea38fdf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260934783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4260934783
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4145895817
Short name T593
Test name
Test status
Simulation time 6904693606 ps
CPU time 8.46 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 233692 kb
Host smart-8e9610ef-4514-452a-8ab1-94d95a0bbeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145895817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4145895817
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2778331051
Short name T774
Test name
Test status
Simulation time 4704892638 ps
CPU time 13.45 seconds
Started Aug 16 05:50:56 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 219908 kb
Host smart-6eaf0aae-a0a7-4835-b727-abf7895b89d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2778331051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2778331051
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3367207398
Short name T295
Test name
Test status
Simulation time 11094786712 ps
CPU time 13.98 seconds
Started Aug 16 05:50:58 PM PDT 24
Finished Aug 16 05:51:12 PM PDT 24
Peak memory 221264 kb
Host smart-56622496-387c-4be2-abbc-84132463f703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367207398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3367207398
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1721634234
Short name T610
Test name
Test status
Simulation time 9897930093 ps
CPU time 14.5 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 217152 kb
Host smart-8369c13a-24f1-4ec3-b52f-ebd25a5b6cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721634234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1721634234
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3640708728
Short name T355
Test name
Test status
Simulation time 397583796 ps
CPU time 3 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:16 PM PDT 24
Peak memory 217216 kb
Host smart-436f8131-01c3-472d-ab4a-f51267cfe95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640708728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3640708728
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3219331352
Short name T939
Test name
Test status
Simulation time 67369152 ps
CPU time 0.83 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:49 PM PDT 24
Peak memory 206828 kb
Host smart-671b0f0d-6c16-4e2e-ac7c-d8a65fb75d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219331352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3219331352
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.325536016
Short name T701
Test name
Test status
Simulation time 17467600627 ps
CPU time 17.42 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 223168 kb
Host smart-62f7f3f7-2a65-41ae-b8f8-661877226c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325536016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.325536016
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1871442116
Short name T63
Test name
Test status
Simulation time 12912319 ps
CPU time 0.75 seconds
Started Aug 16 05:50:52 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 206136 kb
Host smart-df9769f2-b0b5-4b18-ab73-b4867879f85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871442116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1871442116
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1012675356
Short name T155
Test name
Test status
Simulation time 375043441 ps
CPU time 3.19 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 233484 kb
Host smart-f1c704d5-9727-4f14-b6d0-92dad346f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012675356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1012675356
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1781112434
Short name T622
Test name
Test status
Simulation time 12895217 ps
CPU time 0.73 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 207496 kb
Host smart-3528dbf8-4a9b-4587-b0ab-aafbde43a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781112434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1781112434
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3699495767
Short name T209
Test name
Test status
Simulation time 4831085530 ps
CPU time 20.03 seconds
Started Aug 16 05:51:10 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 249976 kb
Host smart-b83cc533-8746-433c-b5cc-d0c0e994c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699495767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3699495767
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.667007404
Short name T876
Test name
Test status
Simulation time 12387230775 ps
CPU time 45.73 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:51:37 PM PDT 24
Peak memory 239988 kb
Host smart-f839a34e-4fc2-45b0-9860-c5a10842148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667007404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.667007404
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4062237803
Short name T600
Test name
Test status
Simulation time 37101763780 ps
CPU time 72.43 seconds
Started Aug 16 05:50:53 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 250188 kb
Host smart-9a2d0b79-6c0c-4977-8769-0612dfee8bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062237803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4062237803
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1043515425
Short name T897
Test name
Test status
Simulation time 1405033475 ps
CPU time 11.66 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:51:13 PM PDT 24
Peak memory 225292 kb
Host smart-fbeee264-5c80-45c0-b472-15448c720857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043515425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1043515425
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2395221777
Short name T249
Test name
Test status
Simulation time 39737579566 ps
CPU time 265.18 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 251148 kb
Host smart-c6b81da0-ff92-4c6a-a616-f7a35197eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395221777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2395221777
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3735446433
Short name T670
Test name
Test status
Simulation time 2119818613 ps
CPU time 4.05 seconds
Started Aug 16 05:50:56 PM PDT 24
Finished Aug 16 05:51:00 PM PDT 24
Peak memory 228744 kb
Host smart-64d226f3-1933-44d5-8944-935feb9a8d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735446433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3735446433
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2623813119
Short name T979
Test name
Test status
Simulation time 11581446494 ps
CPU time 23.25 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:52:25 PM PDT 24
Peak memory 232872 kb
Host smart-ffc3bcb2-bb5a-4f80-90e8-2edd6430306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623813119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2623813119
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4068770850
Short name T790
Test name
Test status
Simulation time 6543601568 ps
CPU time 9.33 seconds
Started Aug 16 05:52:19 PM PDT 24
Finished Aug 16 05:52:31 PM PDT 24
Peak memory 239208 kb
Host smart-6d9331eb-ceab-4393-af01-841065628013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068770850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4068770850
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2844510086
Short name T777
Test name
Test status
Simulation time 35092960 ps
CPU time 2.33 seconds
Started Aug 16 05:52:20 PM PDT 24
Finished Aug 16 05:52:23 PM PDT 24
Peak memory 233376 kb
Host smart-83942039-5eff-4a33-83bb-10f88923187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844510086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2844510086
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3468414286
Short name T345
Test name
Test status
Simulation time 4484470260 ps
CPU time 4.93 seconds
Started Aug 16 05:50:56 PM PDT 24
Finished Aug 16 05:51:01 PM PDT 24
Peak memory 220984 kb
Host smart-1fe6be18-4dc3-45ae-9899-14dcc865bbd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3468414286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3468414286
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4142299354
Short name T153
Test name
Test status
Simulation time 28827792317 ps
CPU time 171.69 seconds
Started Aug 16 05:51:22 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 257100 kb
Host smart-517da7a6-4039-44d2-aa33-aac6e3c3d533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142299354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4142299354
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2194162796
Short name T970
Test name
Test status
Simulation time 34952539 ps
CPU time 0.68 seconds
Started Aug 16 05:52:18 PM PDT 24
Finished Aug 16 05:52:19 PM PDT 24
Peak memory 206280 kb
Host smart-f7769934-3fa5-4059-b4e1-5cca0e9f8f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194162796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2194162796
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3837653748
Short name T810
Test name
Test status
Simulation time 5338726826 ps
CPU time 5.17 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:52:08 PM PDT 24
Peak memory 216900 kb
Host smart-ee59a15b-3408-4d8b-9521-a3a311393ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837653748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3837653748
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.632459046
Short name T325
Test name
Test status
Simulation time 573535604 ps
CPU time 2.39 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 214208 kb
Host smart-ac4bf49c-5819-4470-9dbc-528278c527b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632459046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.632459046
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.433580708
Short name T482
Test name
Test status
Simulation time 13210490 ps
CPU time 0.68 seconds
Started Aug 16 05:50:54 PM PDT 24
Finished Aug 16 05:50:55 PM PDT 24
Peak memory 206396 kb
Host smart-99a069c5-ba9d-49e5-8bd1-5b485cce9f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433580708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.433580708
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2591861152
Short name T590
Test name
Test status
Simulation time 3051216984 ps
CPU time 4.62 seconds
Started Aug 16 05:50:53 PM PDT 24
Finished Aug 16 05:50:57 PM PDT 24
Peak memory 225404 kb
Host smart-917a7c4e-f816-4f69-85d9-b75733704122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591861152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2591861152
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3852953891
Short name T312
Test name
Test status
Simulation time 14833643 ps
CPU time 0.73 seconds
Started Aug 16 05:50:49 PM PDT 24
Finished Aug 16 05:50:50 PM PDT 24
Peak memory 206212 kb
Host smart-c6dc9991-40ef-4bb4-a165-3aef29a8ba53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852953891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3852953891
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2710059562
Short name T395
Test name
Test status
Simulation time 152605671 ps
CPU time 2.81 seconds
Started Aug 16 05:50:54 PM PDT 24
Finished Aug 16 05:50:57 PM PDT 24
Peak memory 233468 kb
Host smart-1e5a12f2-24df-4dac-9665-337799ebcaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710059562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2710059562
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1048739163
Short name T871
Test name
Test status
Simulation time 50243519 ps
CPU time 0.85 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 207404 kb
Host smart-6f0cd3aa-c585-4b5f-919a-a9dcb5699ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048739163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1048739163
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3710608565
Short name T473
Test name
Test status
Simulation time 27597315570 ps
CPU time 108.05 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:53:49 PM PDT 24
Peak memory 253184 kb
Host smart-73aa1efb-b9f0-43b0-8a0f-6c90bc4e1944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710608565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3710608565
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.126347325
Short name T475
Test name
Test status
Simulation time 523542876 ps
CPU time 10.13 seconds
Started Aug 16 05:51:19 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 238416 kb
Host smart-5d5becb8-7419-4cad-93a3-99cb9ef488ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126347325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.126347325
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1797451852
Short name T822
Test name
Test status
Simulation time 4093059044 ps
CPU time 26.2 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:28 PM PDT 24
Peak memory 218372 kb
Host smart-284728dd-40e5-4336-aaaa-a38ecce9e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797451852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1797451852
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2450704736
Short name T282
Test name
Test status
Simulation time 7088497304 ps
CPU time 29.19 seconds
Started Aug 16 05:50:57 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 225500 kb
Host smart-9eaa7ef1-2af1-44a5-9615-c46b45f7c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450704736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2450704736
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.194956411
Short name T599
Test name
Test status
Simulation time 43368997088 ps
CPU time 154.11 seconds
Started Aug 16 05:51:07 PM PDT 24
Finished Aug 16 05:53:41 PM PDT 24
Peak memory 250044 kb
Host smart-802166e2-7b4a-45c4-8bce-a0c7e3b72408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194956411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.194956411
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3395039285
Short name T962
Test name
Test status
Simulation time 342927451 ps
CPU time 3.6 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 223804 kb
Host smart-6b17d6d8-e251-4ad0-a456-8ac9303c7bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395039285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3395039285
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2091788919
Short name T315
Test name
Test status
Simulation time 35847744 ps
CPU time 2.31 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:50:53 PM PDT 24
Peak memory 225344 kb
Host smart-a3a8d969-9503-4e96-bcfc-f9632dd4daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091788919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2091788919
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1839013914
Short name T541
Test name
Test status
Simulation time 1223747182 ps
CPU time 3.56 seconds
Started Aug 16 05:52:20 PM PDT 24
Finished Aug 16 05:52:26 PM PDT 24
Peak memory 225132 kb
Host smart-b4cad7b0-c8cd-4ccc-962f-f5bf4079bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839013914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1839013914
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1190852924
Short name T885
Test name
Test status
Simulation time 118549201 ps
CPU time 3 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 233552 kb
Host smart-1138b89f-a55a-4196-b6df-26ae49115eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190852924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1190852924
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4256530033
Short name T850
Test name
Test status
Simulation time 670700127 ps
CPU time 4.54 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:04 PM PDT 24
Peak memory 221148 kb
Host smart-3bc67cd9-0e76-4b7d-b52e-aa8f2b2dbc8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256530033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4256530033
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1385976958
Short name T634
Test name
Test status
Simulation time 1987962848 ps
CPU time 26.71 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 225240 kb
Host smart-71b247a0-c2fe-40b6-8892-49a53c663ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385976958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1385976958
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.229628350
Short name T292
Test name
Test status
Simulation time 2615160789 ps
CPU time 26.74 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 217300 kb
Host smart-dbc56fab-c1c0-4932-9a73-8e7eabf9322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229628350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.229628350
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.731904589
Short name T581
Test name
Test status
Simulation time 1569389208 ps
CPU time 2.72 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 217020 kb
Host smart-d2d74a54-5abc-445e-bcce-d93c1b3bc95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731904589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.731904589
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1593173540
Short name T560
Test name
Test status
Simulation time 37136970 ps
CPU time 1.54 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 216964 kb
Host smart-a9c922e9-c201-453a-b9f6-3b091c993866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593173540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1593173540
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3298683676
Short name T789
Test name
Test status
Simulation time 137132094 ps
CPU time 0.79 seconds
Started Aug 16 05:50:48 PM PDT 24
Finished Aug 16 05:50:49 PM PDT 24
Peak memory 206672 kb
Host smart-527e7e3f-6fba-4318-8806-94ecbdb8947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298683676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3298683676
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3275055987
Short name T257
Test name
Test status
Simulation time 3332809593 ps
CPU time 6.99 seconds
Started Aug 16 05:50:59 PM PDT 24
Finished Aug 16 05:51:07 PM PDT 24
Peak memory 249880 kb
Host smart-21e6dc01-e07e-41ac-9f6c-61bedd620153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275055987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3275055987
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1225504849
Short name T618
Test name
Test status
Simulation time 33971042 ps
CPU time 0.71 seconds
Started Aug 16 05:50:55 PM PDT 24
Finished Aug 16 05:50:55 PM PDT 24
Peak memory 206232 kb
Host smart-f57fa320-f4fd-4e1d-a56f-6d0ce8c590ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225504849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1225504849
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2834388345
Short name T457
Test name
Test status
Simulation time 103708122 ps
CPU time 2.47 seconds
Started Aug 16 05:50:53 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 233356 kb
Host smart-8657eb01-6490-4cc7-900b-bae528c997ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834388345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2834388345
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3814105440
Short name T761
Test name
Test status
Simulation time 13225255 ps
CPU time 0.81 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 207464 kb
Host smart-fff30b8c-b033-43b5-977e-3d4654c106e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814105440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3814105440
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2969335317
Short name T832
Test name
Test status
Simulation time 29542188562 ps
CPU time 69.2 seconds
Started Aug 16 05:50:52 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 250200 kb
Host smart-accd7d9c-6fea-4a05-a559-a59907709c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969335317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2969335317
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.990242440
Short name T529
Test name
Test status
Simulation time 15369520072 ps
CPU time 83.32 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:53:26 PM PDT 24
Peak memory 265156 kb
Host smart-4aa6e334-9eee-4896-a69c-2c6ccfa974ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990242440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.990242440
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2816817798
Short name T422
Test name
Test status
Simulation time 8599218309 ps
CPU time 13.62 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:52:15 PM PDT 24
Peak memory 216388 kb
Host smart-18ce7da6-89cf-40b5-ac82-f0ae08b96736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816817798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2816817798
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4081336811
Short name T757
Test name
Test status
Simulation time 187987745 ps
CPU time 4.89 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 235244 kb
Host smart-1db220c7-cb54-4787-8697-6a349ef3427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081336811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4081336811
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2546740744
Short name T880
Test name
Test status
Simulation time 33876900548 ps
CPU time 240.1 seconds
Started Aug 16 05:52:20 PM PDT 24
Finished Aug 16 05:56:20 PM PDT 24
Peak memory 265688 kb
Host smart-1f6ccb89-594b-40d2-8cd4-c39a97374c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546740744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2546740744
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.714588963
Short name T5
Test name
Test status
Simulation time 196621464 ps
CPU time 3.37 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:06 PM PDT 24
Peak memory 223080 kb
Host smart-1f9c2a7c-62c1-4148-8abb-3d97d97540ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714588963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.714588963
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3702957300
Short name T427
Test name
Test status
Simulation time 4603421684 ps
CPU time 13.88 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:51:04 PM PDT 24
Peak memory 225584 kb
Host smart-6196aee1-847b-4c85-a34c-1adda57a4874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702957300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3702957300
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2821065071
Short name T579
Test name
Test status
Simulation time 241848591 ps
CPU time 4.14 seconds
Started Aug 16 05:50:51 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 233444 kb
Host smart-04586e7d-690f-4419-8d32-62daf32cac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821065071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2821065071
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3739860713
Short name T608
Test name
Test status
Simulation time 31448650315 ps
CPU time 44.53 seconds
Started Aug 16 05:50:58 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 251136 kb
Host smart-4a5dec94-e576-4b4e-be7f-3085fb97f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739860713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3739860713
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.266766594
Short name T988
Test name
Test status
Simulation time 287944672 ps
CPU time 5.48 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 223252 kb
Host smart-068cb714-7a09-41b7-aed9-21f76bd5f4e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=266766594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.266766594
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.931050712
Short name T42
Test name
Test status
Simulation time 6279548804 ps
CPU time 145.58 seconds
Started Aug 16 05:50:56 PM PDT 24
Finished Aug 16 05:53:22 PM PDT 24
Peak memory 285832 kb
Host smart-4b74cb74-4989-4276-a507-00dcfad9e977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931050712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.931050712
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3237843177
Short name T698
Test name
Test status
Simulation time 6402029491 ps
CPU time 10.92 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 214668 kb
Host smart-3d2d7990-b7f0-41b8-8cba-242a2257e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237843177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3237843177
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2790890470
Short name T387
Test name
Test status
Simulation time 2756662506 ps
CPU time 7.13 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:10 PM PDT 24
Peak memory 214504 kb
Host smart-90656c5d-694a-424b-abfb-9b553ba34b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790890470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2790890470
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2947393269
Short name T540
Test name
Test status
Simulation time 476378199 ps
CPU time 1.81 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:25 PM PDT 24
Peak memory 214520 kb
Host smart-5e49fe35-6675-47b0-9596-c82a08755212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947393269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2947393269
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.617248472
Short name T81
Test name
Test status
Simulation time 11642641 ps
CPU time 0.71 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:03 PM PDT 24
Peak memory 204232 kb
Host smart-39d84ce7-7a55-4553-b8ec-d166825f7fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617248472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.617248472
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.545931174
Short name T183
Test name
Test status
Simulation time 718250561 ps
CPU time 3.77 seconds
Started Aug 16 05:50:50 PM PDT 24
Finished Aug 16 05:50:55 PM PDT 24
Peak memory 233584 kb
Host smart-b14b3d7d-ca5a-4261-ad12-335ae8e30b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545931174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.545931174
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2950180436
Short name T333
Test name
Test status
Simulation time 40265799 ps
CPU time 0.73 seconds
Started Aug 16 05:49:51 PM PDT 24
Finished Aug 16 05:49:52 PM PDT 24
Peak memory 206204 kb
Host smart-6183de2a-1b4f-4e90-afff-7491c0ecb01f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950180436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
950180436
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2563879100
Short name T520
Test name
Test status
Simulation time 12559071303 ps
CPU time 24.42 seconds
Started Aug 16 05:49:35 PM PDT 24
Finished Aug 16 05:50:00 PM PDT 24
Peak memory 225360 kb
Host smart-09947414-4fae-409d-bdf5-9cbb74d22223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563879100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2563879100
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4253549912
Short name T82
Test name
Test status
Simulation time 19505580 ps
CPU time 0.75 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:51:27 PM PDT 24
Peak memory 207376 kb
Host smart-13e109b1-6890-4db3-9de6-748fd3083d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253549912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4253549912
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2510166221
Short name T431
Test name
Test status
Simulation time 10207657303 ps
CPU time 18.21 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 05:52:26 PM PDT 24
Peak memory 235428 kb
Host smart-6bfacab6-e99a-4a98-b1a1-a05df09eb0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510166221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2510166221
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4190293113
Short name T261
Test name
Test status
Simulation time 45974078169 ps
CPU time 108.05 seconds
Started Aug 16 05:49:34 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 250192 kb
Host smart-21ea4454-9fc4-47d8-b7db-546094142cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190293113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4190293113
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4061707419
Short name T959
Test name
Test status
Simulation time 27315432232 ps
CPU time 105.18 seconds
Started Aug 16 05:52:11 PM PDT 24
Finished Aug 16 05:53:56 PM PDT 24
Peak memory 268392 kb
Host smart-9d31c862-9a2d-47e0-8817-ecacf482bb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061707419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4061707419
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3271814971
Short name T859
Test name
Test status
Simulation time 3477734012 ps
CPU time 60.65 seconds
Started Aug 16 05:49:35 PM PDT 24
Finished Aug 16 05:50:36 PM PDT 24
Peak memory 225420 kb
Host smart-c4e1ab93-8ebe-4c9e-9acb-c1f052f2e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271814971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3271814971
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1515338801
Short name T978
Test name
Test status
Simulation time 7667728652 ps
CPU time 72.51 seconds
Started Aug 16 05:52:10 PM PDT 24
Finished Aug 16 05:53:23 PM PDT 24
Peak memory 255244 kb
Host smart-7970f7a3-3ce7-4892-9918-b4f7ae4b6cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515338801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1515338801
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.318422888
Short name T412
Test name
Test status
Simulation time 115995624 ps
CPU time 3.78 seconds
Started Aug 16 05:49:34 PM PDT 24
Finished Aug 16 05:49:38 PM PDT 24
Peak memory 233576 kb
Host smart-e4b104d8-eaa2-40ef-b0c8-4752b4df8ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318422888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.318422888
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4292981898
Short name T957
Test name
Test status
Simulation time 3951162463 ps
CPU time 14.25 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 233544 kb
Host smart-c6b2dbca-d4ec-40e8-9767-235981178d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292981898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4292981898
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2486181037
Short name T611
Test name
Test status
Simulation time 26964045041 ps
CPU time 20.06 seconds
Started Aug 16 05:49:35 PM PDT 24
Finished Aug 16 05:49:56 PM PDT 24
Peak memory 225420 kb
Host smart-c40f3f4d-f9b7-447e-8a1a-39f3355d7d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486181037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2486181037
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2277100673
Short name T835
Test name
Test status
Simulation time 4062966494 ps
CPU time 12.92 seconds
Started Aug 16 05:49:38 PM PDT 24
Finished Aug 16 05:49:51 PM PDT 24
Peak memory 225416 kb
Host smart-fccbbe45-fb1b-45bf-856f-c0a41d3bcd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277100673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2277100673
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2142553342
Short name T11
Test name
Test status
Simulation time 349102381 ps
CPU time 4.09 seconds
Started Aug 16 05:51:52 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 223516 kb
Host smart-1a48d0fd-6a65-47f0-b59f-98fcbf292c68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2142553342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2142553342
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2370794426
Short name T35
Test name
Test status
Simulation time 166576675 ps
CPU time 0.95 seconds
Started Aug 16 05:52:13 PM PDT 24
Finished Aug 16 05:52:14 PM PDT 24
Peak memory 236976 kb
Host smart-8255bc62-f047-43ea-85e7-9c2322650c52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370794426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2370794426
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3606575496
Short name T869
Test name
Test status
Simulation time 42207576894 ps
CPU time 131.65 seconds
Started Aug 16 05:49:36 PM PDT 24
Finished Aug 16 05:51:48 PM PDT 24
Peak memory 250224 kb
Host smart-f598e6ac-8f0e-4b5c-813a-0ee0a8229df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606575496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3606575496
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3306221140
Short name T289
Test name
Test status
Simulation time 2721894196 ps
CPU time 10.84 seconds
Started Aug 16 05:52:04 PM PDT 24
Finished Aug 16 05:52:15 PM PDT 24
Peak memory 217480 kb
Host smart-9d7cf78c-aad6-4dd8-9576-dfc47eb600be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306221140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3306221140
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.718775701
Short name T794
Test name
Test status
Simulation time 8716043518 ps
CPU time 25.48 seconds
Started Aug 16 05:50:09 PM PDT 24
Finished Aug 16 05:50:34 PM PDT 24
Peak memory 217304 kb
Host smart-e0b16056-2e13-4f45-aeda-e3485eeb2a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718775701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.718775701
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.451622620
Short name T636
Test name
Test status
Simulation time 38086809 ps
CPU time 0.72 seconds
Started Aug 16 05:49:37 PM PDT 24
Finished Aug 16 05:49:37 PM PDT 24
Peak memory 206364 kb
Host smart-505396d8-607d-4243-a62f-2ef349a65863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451622620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.451622620
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.854333455
Short name T651
Test name
Test status
Simulation time 1210063242 ps
CPU time 0.87 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 05:52:08 PM PDT 24
Peak memory 206668 kb
Host smart-d7a82736-71e9-4830-bab6-2fb34123788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854333455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.854333455
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2022073066
Short name T203
Test name
Test status
Simulation time 52096374 ps
CPU time 2.74 seconds
Started Aug 16 05:49:54 PM PDT 24
Finished Aug 16 05:49:57 PM PDT 24
Peak memory 241748 kb
Host smart-bf9dec31-16fa-41d5-b643-5943fe7bfaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022073066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2022073066
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.210216351
Short name T715
Test name
Test status
Simulation time 55087369 ps
CPU time 0.81 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:51:03 PM PDT 24
Peak memory 205668 kb
Host smart-e5849922-b8ba-4151-ac4f-8712e5fd4460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210216351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.210216351
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1156475428
Short name T485
Test name
Test status
Simulation time 806522298 ps
CPU time 7.79 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 225332 kb
Host smart-3f70d402-6c03-4bea-b32a-fef307dc55d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156475428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1156475428
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.120760763
Short name T588
Test name
Test status
Simulation time 17497111 ps
CPU time 0.79 seconds
Started Aug 16 05:50:55 PM PDT 24
Finished Aug 16 05:50:56 PM PDT 24
Peak memory 207372 kb
Host smart-00a37c42-2dd6-477b-998e-31998fca6b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120760763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.120760763
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.836498542
Short name T330
Test name
Test status
Simulation time 18176938569 ps
CPU time 58.28 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 235188 kb
Host smart-a5306b57-96d2-4f0f-8c6f-e0619c7eaec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836498542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.836498542
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2510908955
Short name T533
Test name
Test status
Simulation time 4620936214 ps
CPU time 36.03 seconds
Started Aug 16 05:51:23 PM PDT 24
Finished Aug 16 05:51:59 PM PDT 24
Peak memory 218464 kb
Host smart-975e2d03-67aa-4469-807c-f80b0af073ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510908955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2510908955
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.446967160
Short name T726
Test name
Test status
Simulation time 2754634868 ps
CPU time 18.02 seconds
Started Aug 16 05:51:03 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 250096 kb
Host smart-57e674a7-f381-4ecb-a3ed-ba1161fa573b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446967160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.446967160
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3870724433
Short name T1006
Test name
Test status
Simulation time 6433877580 ps
CPU time 66.48 seconds
Started Aug 16 05:51:22 PM PDT 24
Finished Aug 16 05:52:28 PM PDT 24
Peak memory 250024 kb
Host smart-3bb2ba1c-1d55-4fee-b219-f82e15e93690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870724433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3870724433
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2456557334
Short name T652
Test name
Test status
Simulation time 6465311742 ps
CPU time 24.85 seconds
Started Aug 16 05:51:12 PM PDT 24
Finished Aug 16 05:51:37 PM PDT 24
Peak memory 229984 kb
Host smart-5699cf70-86be-4ebb-a34c-69ea208b8ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456557334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2456557334
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1586791434
Short name T403
Test name
Test status
Simulation time 66744107 ps
CPU time 2.83 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:17 PM PDT 24
Peak memory 233528 kb
Host smart-ee4c4d4b-8c0a-4fd8-9bde-206c6203b985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586791434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1586791434
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1292803067
Short name T109
Test name
Test status
Simulation time 4615431376 ps
CPU time 9.04 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 225464 kb
Host smart-743fafb8-4e42-419f-bb3a-a478c7132e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292803067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1292803067
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1019712848
Short name T873
Test name
Test status
Simulation time 89051474 ps
CPU time 2.18 seconds
Started Aug 16 05:51:01 PM PDT 24
Finished Aug 16 05:51:04 PM PDT 24
Peak memory 224768 kb
Host smart-a04d8278-4d84-496d-bb27-df16a40267b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019712848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1019712848
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3491353174
Short name T839
Test name
Test status
Simulation time 356930671 ps
CPU time 5.81 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:35 PM PDT 24
Peak memory 221380 kb
Host smart-05e09833-d73c-4203-a2b0-e1619ba46ec4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3491353174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3491353174
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4121204542
Short name T706
Test name
Test status
Simulation time 326542022128 ps
CPU time 805.11 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 06:04:52 PM PDT 24
Peak memory 284948 kb
Host smart-e5e21b77-227f-4850-b6d1-b680f6515bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121204542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4121204542
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1515458332
Short name T824
Test name
Test status
Simulation time 84502614750 ps
CPU time 41.86 seconds
Started Aug 16 05:51:23 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 217280 kb
Host smart-3593184c-d46d-46bf-bec9-874267ab8294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515458332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1515458332
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2100915569
Short name T495
Test name
Test status
Simulation time 1580243738 ps
CPU time 4.9 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:19 PM PDT 24
Peak memory 217220 kb
Host smart-cbe9ee03-c209-464b-84c8-bb68443b8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100915569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2100915569
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.366004867
Short name T815
Test name
Test status
Simulation time 137987494 ps
CPU time 1.18 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 207984 kb
Host smart-e57cef60-d9a6-44f0-b5a1-58cab066abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366004867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.366004867
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3929006663
Short name T361
Test name
Test status
Simulation time 661920373 ps
CPU time 1.03 seconds
Started Aug 16 05:51:32 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 207788 kb
Host smart-7230d2e4-afa7-472a-824a-c46d52fa8b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929006663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3929006663
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2152896906
Short name T659
Test name
Test status
Simulation time 8182335599 ps
CPU time 15.03 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 225500 kb
Host smart-786964cf-be34-4f9f-a74a-cfa3a742a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152896906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2152896906
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3061640080
Short name T539
Test name
Test status
Simulation time 22241980 ps
CPU time 0.73 seconds
Started Aug 16 05:51:03 PM PDT 24
Finished Aug 16 05:51:03 PM PDT 24
Peak memory 206260 kb
Host smart-2dfa1edc-2c87-4be2-b91e-a169d41496c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061640080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3061640080
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1999679647
Short name T877
Test name
Test status
Simulation time 619135140 ps
CPU time 2.42 seconds
Started Aug 16 05:51:21 PM PDT 24
Finished Aug 16 05:51:24 PM PDT 24
Peak memory 225296 kb
Host smart-817db072-9028-4eb9-8d13-2cde26fef962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999679647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1999679647
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2168103217
Short name T913
Test name
Test status
Simulation time 27755333 ps
CPU time 0.8 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:51:03 PM PDT 24
Peak memory 207688 kb
Host smart-068e287c-ecb9-424a-883a-355ad83682ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168103217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2168103217
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2471296305
Short name T176
Test name
Test status
Simulation time 41911723184 ps
CPU time 276.27 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:56:06 PM PDT 24
Peak memory 255600 kb
Host smart-ec00a832-4a58-402f-8e84-47820323bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471296305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2471296305
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.989271210
Short name T923
Test name
Test status
Simulation time 78506779259 ps
CPU time 102.81 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 241920 kb
Host smart-6ad6e965-2410-4c81-bea7-015b11c1fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989271210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.989271210
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1701017794
Short name T215
Test name
Test status
Simulation time 1088197400 ps
CPU time 21.75 seconds
Started Aug 16 05:51:03 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 249988 kb
Host smart-024023ea-ffb8-41de-9c3d-6ea058f34177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701017794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1701017794
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2799839298
Short name T492
Test name
Test status
Simulation time 388642084 ps
CPU time 8.27 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:12 PM PDT 24
Peak memory 225364 kb
Host smart-169e1264-6289-42d5-810a-90fcf90250df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799839298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2799839298
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1159827519
Short name T99
Test name
Test status
Simulation time 10889107315 ps
CPU time 88.18 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 250240 kb
Host smart-6319ba93-3d57-4acc-98d4-fd974104da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159827519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1159827519
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3347688494
Short name T466
Test name
Test status
Simulation time 1156924733 ps
CPU time 5.13 seconds
Started Aug 16 05:51:01 PM PDT 24
Finished Aug 16 05:51:06 PM PDT 24
Peak memory 225276 kb
Host smart-1fc10ba1-6c9f-4e24-b059-ffdeb590e66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347688494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3347688494
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2585457809
Short name T471
Test name
Test status
Simulation time 2112995700 ps
CPU time 21.47 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 249536 kb
Host smart-422f0e00-8153-454b-bd8b-a0d033db384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585457809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2585457809
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3697960075
Short name T260
Test name
Test status
Simulation time 3774909217 ps
CPU time 10.43 seconds
Started Aug 16 05:51:01 PM PDT 24
Finished Aug 16 05:51:12 PM PDT 24
Peak memory 225492 kb
Host smart-0bdd52b4-956a-49ff-995a-6cdce8c5a3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697960075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3697960075
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1177277819
Short name T178
Test name
Test status
Simulation time 2288462173 ps
CPU time 9.87 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 233640 kb
Host smart-6aa9abb5-c094-473a-b235-430e6f8dc164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177277819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1177277819
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3051457312
Short name T841
Test name
Test status
Simulation time 665363657 ps
CPU time 8.49 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 223024 kb
Host smart-aeb2f74c-cecb-435b-b3fd-9a245dcde467
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3051457312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3051457312
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.354143631
Short name T150
Test name
Test status
Simulation time 29494645426 ps
CPU time 303.56 seconds
Started Aug 16 05:51:03 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 258308 kb
Host smart-45071657-0295-4cfa-a908-87426a7d9126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354143631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.354143631
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.831100661
Short name T754
Test name
Test status
Simulation time 4788605494 ps
CPU time 6.6 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:51:07 PM PDT 24
Peak memory 217392 kb
Host smart-6b2d8bd9-d4c6-49ae-81d8-5ed1774b4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831100661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.831100661
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.309358036
Short name T29
Test name
Test status
Simulation time 3586535378 ps
CPU time 3.5 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 217264 kb
Host smart-3524dcb9-eb8f-4825-8360-0f28be81ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309358036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.309358036
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1787220172
Short name T362
Test name
Test status
Simulation time 223134471 ps
CPU time 1.73 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 217152 kb
Host smart-49073819-9b48-45a8-b98c-2a97a4babbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787220172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1787220172
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1848897278
Short name T746
Test name
Test status
Simulation time 78991510 ps
CPU time 0.94 seconds
Started Aug 16 05:51:00 PM PDT 24
Finished Aug 16 05:51:01 PM PDT 24
Peak memory 206828 kb
Host smart-e29b1cd5-4515-4ace-8838-d6becd317fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848897278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1848897278
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.56175090
Short name T894
Test name
Test status
Simulation time 3394037823 ps
CPU time 5.03 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 233684 kb
Host smart-56e4ae2c-5c90-4556-97c4-161c5c87eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56175090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.56175090
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3468664610
Short name T411
Test name
Test status
Simulation time 18732114 ps
CPU time 0.71 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 206204 kb
Host smart-3648369f-b909-44b0-b886-3d54c50486ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468664610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3468664610
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.753694350
Short name T948
Test name
Test status
Simulation time 203025673 ps
CPU time 5.21 seconds
Started Aug 16 05:51:03 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 233668 kb
Host smart-687147cd-55b2-4402-afed-5c961eaf3633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753694350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.753694350
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1643577972
Short name T449
Test name
Test status
Simulation time 38415115 ps
CPU time 0.81 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 207412 kb
Host smart-87477e8d-494d-43df-953c-4cf7ea9e8986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643577972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1643577972
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.371383934
Short name T468
Test name
Test status
Simulation time 5135094934 ps
CPU time 30.05 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 236868 kb
Host smart-7a38b1f9-8c08-480f-bf86-3161d01c4fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371383934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.371383934
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2972632480
Short name T645
Test name
Test status
Simulation time 13096508376 ps
CPU time 78.24 seconds
Started Aug 16 05:51:19 PM PDT 24
Finished Aug 16 05:52:37 PM PDT 24
Peak memory 258364 kb
Host smart-5523672f-195a-409d-88ad-43201cf3f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972632480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2972632480
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1135595214
Short name T517
Test name
Test status
Simulation time 38822542022 ps
CPU time 111.93 seconds
Started Aug 16 05:51:22 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 250212 kb
Host smart-d2b1ae97-ff64-4c5e-a973-98a911a679fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135595214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1135595214
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1877639175
Short name T285
Test name
Test status
Simulation time 1005138271 ps
CPU time 4.99 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 233544 kb
Host smart-974f7cee-de6d-429a-926c-3fcb8d32f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877639175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1877639175
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2521513918
Short name T414
Test name
Test status
Simulation time 11912808661 ps
CPU time 42.56 seconds
Started Aug 16 05:51:17 PM PDT 24
Finished Aug 16 05:52:00 PM PDT 24
Peak memory 241880 kb
Host smart-6a3440af-e603-4496-8417-e27394bcc901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521513918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2521513918
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.310994569
Short name T963
Test name
Test status
Simulation time 1197650202 ps
CPU time 4.44 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 225320 kb
Host smart-0a450e89-d679-4ab4-9a69-5e2966d367f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310994569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.310994569
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1634472451
Short name T833
Test name
Test status
Simulation time 42861232025 ps
CPU time 94.99 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:53:04 PM PDT 24
Peak memory 233708 kb
Host smart-79400ee6-41fd-4e2f-a9cf-ebdd54a59189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634472451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1634472451
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2947113861
Short name T911
Test name
Test status
Simulation time 183716669 ps
CPU time 2.99 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:07 PM PDT 24
Peak memory 225264 kb
Host smart-6bccd6a8-4df8-4970-9513-d10e874d058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947113861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2947113861
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4248117454
Short name T434
Test name
Test status
Simulation time 56917584 ps
CPU time 2.66 seconds
Started Aug 16 05:51:42 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 233296 kb
Host smart-66a5db3d-bc08-453d-8965-1cfce565593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248117454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4248117454
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1449042744
Short name T664
Test name
Test status
Simulation time 1706266952 ps
CPU time 5.38 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 221300 kb
Host smart-ac7d8311-d45c-40ad-8a85-c957bef4a71b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449042744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1449042744
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1534789537
Short name T186
Test name
Test status
Simulation time 5762940131 ps
CPU time 119.59 seconds
Started Aug 16 05:51:32 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 265676 kb
Host smart-4120969e-12b9-4216-aefc-766001b73e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534789537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1534789537
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2641892110
Short name T385
Test name
Test status
Simulation time 14124377 ps
CPU time 0.71 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:51:03 PM PDT 24
Peak memory 206524 kb
Host smart-6eb37990-4662-4023-bb83-a47965bc20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641892110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2641892110
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1894554207
Short name T693
Test name
Test status
Simulation time 29215852737 ps
CPU time 7.24 seconds
Started Aug 16 05:51:02 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 217368 kb
Host smart-c8af4b7c-def3-48f4-903e-06ea36b36ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894554207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1894554207
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.22986558
Short name T317
Test name
Test status
Simulation time 161685935 ps
CPU time 1.41 seconds
Started Aug 16 05:51:47 PM PDT 24
Finished Aug 16 05:51:48 PM PDT 24
Peak memory 217140 kb
Host smart-de77e4b8-7852-4c12-a3d2-da9fe32bbe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22986558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.22986558
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.314268040
Short name T543
Test name
Test status
Simulation time 86498545 ps
CPU time 0.95 seconds
Started Aug 16 05:51:04 PM PDT 24
Finished Aug 16 05:51:05 PM PDT 24
Peak memory 206948 kb
Host smart-c0865c54-28f3-477a-9ed2-46c41f454298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314268040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.314268040
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.934327758
Short name T818
Test name
Test status
Simulation time 2294325523 ps
CPU time 3.02 seconds
Started Aug 16 05:51:41 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 218028 kb
Host smart-11123814-13ae-451e-902e-185e97cdee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934327758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.934327758
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2521514073
Short name T916
Test name
Test status
Simulation time 40938392 ps
CPU time 0.74 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 206552 kb
Host smart-95d9620a-832c-4b47-b021-4b1daf606ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521514073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2521514073
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3966057644
Short name T615
Test name
Test status
Simulation time 1973776973 ps
CPU time 12.87 seconds
Started Aug 16 05:51:54 PM PDT 24
Finished Aug 16 05:52:07 PM PDT 24
Peak memory 225328 kb
Host smart-1f1e9a13-cc86-4746-8ff5-0ff282a00f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966057644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3966057644
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.675904911
Short name T813
Test name
Test status
Simulation time 89763335 ps
CPU time 0.76 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 207420 kb
Host smart-dd6d4e38-8ae1-49ed-a25d-419c75cf39fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675904911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.675904911
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.115186272
Short name T992
Test name
Test status
Simulation time 24071669629 ps
CPU time 71.87 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:52:46 PM PDT 24
Peak memory 251508 kb
Host smart-98d5a3b4-50bb-466f-be18-a819d6ee9c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115186272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.115186272
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.88261198
Short name T201
Test name
Test status
Simulation time 329263989186 ps
CPU time 629.18 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 06:02:08 PM PDT 24
Peak memory 266632 kb
Host smart-5d2b9dd7-6e1d-4973-9dd9-197a35b4b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88261198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.88261198
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4104664650
Short name T710
Test name
Test status
Simulation time 546461136 ps
CPU time 4.45 seconds
Started Aug 16 05:51:54 PM PDT 24
Finished Aug 16 05:51:59 PM PDT 24
Peak memory 225364 kb
Host smart-13682d6e-2c44-4b4a-8b47-08018f40392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104664650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4104664650
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3687301998
Short name T960
Test name
Test status
Simulation time 3355544733 ps
CPU time 12.69 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 225444 kb
Host smart-e95d08e3-50de-4572-b629-8df6c3411638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687301998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3687301998
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3728304875
Short name T230
Test name
Test status
Simulation time 687298538 ps
CPU time 8.2 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 05:51:47 PM PDT 24
Peak memory 225392 kb
Host smart-5cf185a5-a2d6-4cc1-8fbc-40a6e51b989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728304875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3728304875
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2388716691
Short name T623
Test name
Test status
Simulation time 28268530557 ps
CPU time 35.11 seconds
Started Aug 16 05:51:10 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 233624 kb
Host smart-e8e1a8c2-7f29-4dc9-9cb0-28e3a769239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388716691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2388716691
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3780083793
Short name T630
Test name
Test status
Simulation time 227767013 ps
CPU time 4.91 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 225356 kb
Host smart-9b3e121f-9fb4-487d-bf56-a244dddde88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780083793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3780083793
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2355657997
Short name T393
Test name
Test status
Simulation time 1869683355 ps
CPU time 5.37 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 233516 kb
Host smart-76348f9a-22ef-4d11-bc00-0d8af4e461e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355657997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2355657997
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.416120643
Short name T969
Test name
Test status
Simulation time 1211379712 ps
CPU time 9.48 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:18 PM PDT 24
Peak memory 219700 kb
Host smart-7a4dff0c-6946-456a-8f2b-7b19e67ccbea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=416120643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.416120643
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2359269949
Short name T304
Test name
Test status
Simulation time 64294119752 ps
CPU time 48.16 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:52:40 PM PDT 24
Peak memory 221044 kb
Host smart-1ab77500-cb3c-466f-a22d-9abdeb1edad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359269949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2359269949
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3604163093
Short name T729
Test name
Test status
Simulation time 5372617867 ps
CPU time 19.2 seconds
Started Aug 16 05:52:11 PM PDT 24
Finished Aug 16 05:52:30 PM PDT 24
Peak memory 217276 kb
Host smart-3dcd87d1-0e88-4db7-950e-12cd401ec342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604163093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3604163093
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1699563294
Short name T300
Test name
Test status
Simulation time 140428940 ps
CPU time 0.96 seconds
Started Aug 16 05:51:10 PM PDT 24
Finished Aug 16 05:51:11 PM PDT 24
Peak memory 207988 kb
Host smart-45dbb32a-6d49-440d-a672-7f8566714e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699563294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1699563294
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.202464321
Short name T990
Test name
Test status
Simulation time 63782898 ps
CPU time 0.8 seconds
Started Aug 16 05:52:15 PM PDT 24
Finished Aug 16 05:52:16 PM PDT 24
Peak memory 206844 kb
Host smart-7d7c05ba-eecf-48ac-a814-d661b7034d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202464321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.202464321
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1673685624
Short name T571
Test name
Test status
Simulation time 1999693624 ps
CPU time 10.26 seconds
Started Aug 16 05:51:10 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 250896 kb
Host smart-f7cd2cef-ab6a-4e5d-b358-d670b7f1e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673685624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1673685624
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3567390310
Short name T375
Test name
Test status
Simulation time 33527027 ps
CPU time 0.72 seconds
Started Aug 16 05:51:11 PM PDT 24
Finished Aug 16 05:51:12 PM PDT 24
Peak memory 205648 kb
Host smart-510c5a07-8cbd-4e79-8e70-a09104301620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567390310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3567390310
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3618303375
Short name T868
Test name
Test status
Simulation time 3342693731 ps
CPU time 7.74 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:59 PM PDT 24
Peak memory 225504 kb
Host smart-d774573c-0bd0-4d30-8679-9d2a2442d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618303375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3618303375
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.247328611
Short name T703
Test name
Test status
Simulation time 17512715 ps
CPU time 0.72 seconds
Started Aug 16 05:51:50 PM PDT 24
Finished Aug 16 05:51:51 PM PDT 24
Peak memory 207572 kb
Host smart-595e1629-494d-46c9-8877-4c4d59ccf28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247328611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.247328611
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1544906574
Short name T163
Test name
Test status
Simulation time 25948999861 ps
CPU time 138.87 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:53:45 PM PDT 24
Peak memory 250080 kb
Host smart-a3fb555e-2097-4db1-8735-029a9c6d4e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544906574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1544906574
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.516198763
Short name T459
Test name
Test status
Simulation time 15667160209 ps
CPU time 55.68 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:52:21 PM PDT 24
Peak memory 251380 kb
Host smart-11ebfd69-6dbf-4999-8933-c8ea4c81e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516198763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.516198763
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3694008558
Short name T290
Test name
Test status
Simulation time 52042296173 ps
CPU time 70.25 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 226556 kb
Host smart-1e3ecce1-a3e5-46bc-80b1-a359254aa921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694008558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3694008558
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2941369215
Short name T624
Test name
Test status
Simulation time 894097389 ps
CPU time 4.47 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 225276 kb
Host smart-a66d5a6b-4a12-477e-a8a6-4201157fcf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941369215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2941369215
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3386645271
Short name T160
Test name
Test status
Simulation time 212211848527 ps
CPU time 390.27 seconds
Started Aug 16 05:51:07 PM PDT 24
Finished Aug 16 05:57:38 PM PDT 24
Peak memory 269840 kb
Host smart-74ae2962-b4f7-4ad9-8c41-6e634b33c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386645271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3386645271
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4124363569
Short name T228
Test name
Test status
Simulation time 1542542044 ps
CPU time 7.26 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:43 PM PDT 24
Peak memory 225380 kb
Host smart-3907f1c2-48d9-4a2e-8031-0e5b706c3bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124363569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4124363569
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.818807769
Short name T811
Test name
Test status
Simulation time 5946148785 ps
CPU time 8.74 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:46 PM PDT 24
Peak memory 229668 kb
Host smart-61c35457-46a1-490b-b8d3-5b9f6e6b8fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818807769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.818807769
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1184588187
Short name T843
Test name
Test status
Simulation time 3898428360 ps
CPU time 13 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 225276 kb
Host smart-4eac62ee-d51a-44b7-916b-b38f69fcf0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184588187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1184588187
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1504249075
Short name T413
Test name
Test status
Simulation time 28829949596 ps
CPU time 22.59 seconds
Started Aug 16 05:51:41 PM PDT 24
Finished Aug 16 05:52:03 PM PDT 24
Peak memory 233748 kb
Host smart-507e39a5-f6bb-4ab4-b2c1-d1445e63b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504249075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1504249075
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2044731105
Short name T39
Test name
Test status
Simulation time 2473849102 ps
CPU time 15.81 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:52:07 PM PDT 24
Peak memory 221848 kb
Host smart-2cdc1fc0-a982-4be3-9730-c4adf6248621
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2044731105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2044731105
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2396947936
Short name T895
Test name
Test status
Simulation time 61014149 ps
CPU time 1.13 seconds
Started Aug 16 05:52:11 PM PDT 24
Finished Aug 16 05:52:13 PM PDT 24
Peak memory 207932 kb
Host smart-2d2a3562-09b9-4e1b-9ee2-64f3174a6cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396947936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2396947936
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.308010814
Short name T584
Test name
Test status
Simulation time 1668515244 ps
CPU time 10.36 seconds
Started Aug 16 05:51:43 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 217144 kb
Host smart-3097bbae-12a6-4eef-9c41-110174de350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308010814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.308010814
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3507778019
Short name T763
Test name
Test status
Simulation time 3898308407 ps
CPU time 1.93 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 208848 kb
Host smart-2432f1be-6b7f-4d43-92c3-abd0915b0c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507778019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3507778019
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1285565400
Short name T617
Test name
Test status
Simulation time 527560783 ps
CPU time 1.96 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:40 PM PDT 24
Peak memory 217192 kb
Host smart-cd71fab7-6033-4cd6-9bfd-4509a49a56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285565400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1285565400
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3097507038
Short name T829
Test name
Test status
Simulation time 45135625 ps
CPU time 0.85 seconds
Started Aug 16 05:52:00 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 206864 kb
Host smart-40012f7b-7783-4a9f-87c3-df8389c7f57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097507038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3097507038
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2064920379
Short name T483
Test name
Test status
Simulation time 19551952674 ps
CPU time 14.97 seconds
Started Aug 16 05:51:11 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 240880 kb
Host smart-05e00324-8320-4fbc-a0ca-2c30f99374d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064920379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2064920379
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1540810375
Short name T458
Test name
Test status
Simulation time 20885978 ps
CPU time 0.72 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 206280 kb
Host smart-a3076d28-f8e1-4bb0-ae1e-6b95ea9750e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540810375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1540810375
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4293345773
Short name T98
Test name
Test status
Simulation time 105173024 ps
CPU time 2.55 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:41 PM PDT 24
Peak memory 225328 kb
Host smart-ff6af98d-54bb-428b-8b75-8c3c5b2d1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293345773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4293345773
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.994189389
Short name T559
Test name
Test status
Simulation time 80316721 ps
CPU time 0.76 seconds
Started Aug 16 05:51:56 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 207740 kb
Host smart-fb532110-a47b-45a0-934b-ae40037aa4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994189389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.994189389
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.568411307
Short name T208
Test name
Test status
Simulation time 4061560239 ps
CPU time 41.1 seconds
Started Aug 16 05:51:12 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 250584 kb
Host smart-84faed16-2020-4320-b74d-64d52e410cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568411307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.568411307
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1802825876
Short name T881
Test name
Test status
Simulation time 5221188076 ps
CPU time 32.21 seconds
Started Aug 16 05:51:12 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 223364 kb
Host smart-c88345f5-0fd5-4473-b5f3-7fa76851bb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802825876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1802825876
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1213561390
Short name T336
Test name
Test status
Simulation time 44468751 ps
CPU time 0.82 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:09 PM PDT 24
Peak memory 217792 kb
Host smart-34081fd6-923a-4ea3-8e7f-e89c7f4fec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213561390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1213561390
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3078594260
Short name T185
Test name
Test status
Simulation time 28919209174 ps
CPU time 219.51 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:55:15 PM PDT 24
Peak memory 250072 kb
Host smart-84d05995-7500-4a96-9713-08dfcb8aad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078594260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3078594260
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2454213139
Short name T195
Test name
Test status
Simulation time 1806156388 ps
CPU time 17.78 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 233504 kb
Host smart-ed33fb1c-1167-48d3-ab1e-18bff65bd0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454213139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2454213139
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4155953258
Short name T606
Test name
Test status
Simulation time 1560482488 ps
CPU time 11.23 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 250156 kb
Host smart-b6960f22-cd03-428c-abea-174b941de86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155953258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4155953258
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1045906349
Short name T513
Test name
Test status
Simulation time 322005849 ps
CPU time 5.79 seconds
Started Aug 16 05:51:50 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 225104 kb
Host smart-a44cb7ee-b809-4552-ae1c-cd44b7b16039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045906349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1045906349
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1350024060
Short name T219
Test name
Test status
Simulation time 6121164677 ps
CPU time 10.26 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:43 PM PDT 24
Peak memory 236852 kb
Host smart-a0e5bf12-c57c-4e3c-9691-8a072c1ec2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350024060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1350024060
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.507552586
Short name T799
Test name
Test status
Simulation time 6134604140 ps
CPU time 18.88 seconds
Started Aug 16 05:51:12 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 220656 kb
Host smart-08319076-030d-4d1f-bb18-50364e022762
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=507552586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.507552586
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2017288036
Short name T151
Test name
Test status
Simulation time 446505901167 ps
CPU time 340 seconds
Started Aug 16 05:51:48 PM PDT 24
Finished Aug 16 05:57:28 PM PDT 24
Peak memory 272712 kb
Host smart-1802704f-a51b-4108-87ea-54acea9db621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017288036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2017288036
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2974514846
Short name T891
Test name
Test status
Simulation time 3713421762 ps
CPU time 16.11 seconds
Started Aug 16 05:51:16 PM PDT 24
Finished Aug 16 05:51:33 PM PDT 24
Peak memory 217324 kb
Host smart-23830598-bfd7-4849-9f7b-702c95bd1b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974514846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2974514846
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3618091574
Short name T9
Test name
Test status
Simulation time 1785650547 ps
CPU time 10.09 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 217172 kb
Host smart-5b7690bf-5973-4b05-9554-c6be6d694d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618091574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3618091574
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2789968024
Short name T752
Test name
Test status
Simulation time 26035334 ps
CPU time 0.99 seconds
Started Aug 16 05:51:16 PM PDT 24
Finished Aug 16 05:51:17 PM PDT 24
Peak memory 207912 kb
Host smart-5ada4d11-0de1-4c86-afa7-f4df93d46d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789968024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2789968024
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1032105898
Short name T536
Test name
Test status
Simulation time 86873568 ps
CPU time 0.78 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:15 PM PDT 24
Peak memory 206828 kb
Host smart-6888470e-167f-49a6-86bc-9719cc16d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032105898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1032105898
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.181496626
Short name T791
Test name
Test status
Simulation time 107568730 ps
CPU time 3.33 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:16 PM PDT 24
Peak memory 232792 kb
Host smart-8efe142b-0055-42da-914f-863feaa2d881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181496626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.181496626
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.521510259
Short name T878
Test name
Test status
Simulation time 15122791 ps
CPU time 0.74 seconds
Started Aug 16 05:53:00 PM PDT 24
Finished Aug 16 05:53:01 PM PDT 24
Peak memory 205508 kb
Host smart-bb82ac1f-f407-4643-a788-c454038b0df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521510259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.521510259
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3459747721
Short name T875
Test name
Test status
Simulation time 11423790648 ps
CPU time 32.72 seconds
Started Aug 16 05:52:04 PM PDT 24
Finished Aug 16 05:52:37 PM PDT 24
Peak memory 225460 kb
Host smart-2d2d32b1-b4f1-4102-80a9-73acdd2f674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459747721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3459747721
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3275261860
Short name T783
Test name
Test status
Simulation time 35209872 ps
CPU time 0.8 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:15 PM PDT 24
Peak memory 207756 kb
Host smart-774ab655-fab5-491f-bf2e-4806e57de47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275261860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3275261860
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3480949554
Short name T491
Test name
Test status
Simulation time 12287494569 ps
CPU time 97.62 seconds
Started Aug 16 05:51:40 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 248812 kb
Host smart-57adedc5-0952-4bb4-a2ca-340bcb268b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480949554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3480949554
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.664946849
Short name T241
Test name
Test status
Simulation time 293976911529 ps
CPU time 458.16 seconds
Started Aug 16 05:51:11 PM PDT 24
Finished Aug 16 05:58:49 PM PDT 24
Peak memory 258236 kb
Host smart-ae9f4db2-bf84-48ff-8939-8b9a7958560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664946849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.664946849
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3716612421
Short name T518
Test name
Test status
Simulation time 8024833484 ps
CPU time 64.91 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:52:19 PM PDT 24
Peak memory 241896 kb
Host smart-49ff38f8-e8ec-4438-b853-efc199cc5ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716612421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3716612421
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.22638529
Short name T682
Test name
Test status
Simulation time 612820327 ps
CPU time 7.8 seconds
Started Aug 16 05:52:20 PM PDT 24
Finished Aug 16 05:52:28 PM PDT 24
Peak memory 233388 kb
Host smart-a9042091-7a29-4ade-afaa-c903951ae08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22638529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.22638529
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1490929671
Short name T49
Test name
Test status
Simulation time 2820306581 ps
CPU time 30.77 seconds
Started Aug 16 05:51:53 PM PDT 24
Finished Aug 16 05:52:24 PM PDT 24
Peak memory 241884 kb
Host smart-55d3c2a4-487e-4946-bdb7-0049895b7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490929671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1490929671
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3463259609
Short name T722
Test name
Test status
Simulation time 625865701 ps
CPU time 3.47 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 05:51:43 PM PDT 24
Peak memory 233596 kb
Host smart-bfc85505-4d13-4768-89e1-120803ffa56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463259609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3463259609
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2681717853
Short name T609
Test name
Test status
Simulation time 1350953904 ps
CPU time 8.24 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:23 PM PDT 24
Peak memory 235120 kb
Host smart-85c9d2e3-0188-4bdb-94cc-af4e4bba562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681717853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2681717853
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1368030552
Short name T675
Test name
Test status
Simulation time 2347779714 ps
CPU time 6.56 seconds
Started Aug 16 05:52:10 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 225432 kb
Host smart-5fc91ed7-e0cb-4138-a76c-b83c310c844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368030552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1368030552
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.637853358
Short name T108
Test name
Test status
Simulation time 5011693189 ps
CPU time 6.99 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 225440 kb
Host smart-91ac344a-56a5-4305-b7dd-b3813942cb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637853358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.637853358
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3088799567
Short name T633
Test name
Test status
Simulation time 334145761 ps
CPU time 3.39 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:18 PM PDT 24
Peak memory 219704 kb
Host smart-a8c81f4a-4bd7-4750-9dcf-7aa5ecd73569
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3088799567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3088799567
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3446238977
Short name T502
Test name
Test status
Simulation time 622442019 ps
CPU time 4.75 seconds
Started Aug 16 05:51:14 PM PDT 24
Finished Aug 16 05:51:19 PM PDT 24
Peak memory 217272 kb
Host smart-bc5234b9-71d3-4ee6-b861-e92b7956dacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446238977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3446238977
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1079309555
Short name T376
Test name
Test status
Simulation time 19464586866 ps
CPU time 13.31 seconds
Started Aug 16 05:51:40 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 217316 kb
Host smart-0cef23d9-bed9-4e78-81c6-bf4190c720f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079309555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1079309555
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3117513985
Short name T568
Test name
Test status
Simulation time 26786153 ps
CPU time 1.59 seconds
Started Aug 16 05:51:32 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 217224 kb
Host smart-3ef14f06-02d3-449f-a6bd-c10cb98249e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117513985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3117513985
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1149331221
Short name T470
Test name
Test status
Simulation time 31506204 ps
CPU time 0.86 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:16 PM PDT 24
Peak memory 206852 kb
Host smart-8a5a3afb-004c-4559-a229-2e15a09d79a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149331221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1149331221
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.847095285
Short name T548
Test name
Test status
Simulation time 1256554626 ps
CPU time 4.23 seconds
Started Aug 16 05:51:50 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 225412 kb
Host smart-04026625-506e-4e83-b5ca-619cd1cd60e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847095285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.847095285
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1520405671
Short name T655
Test name
Test status
Simulation time 52148282 ps
CPU time 0.74 seconds
Started Aug 16 05:53:06 PM PDT 24
Finished Aug 16 05:53:07 PM PDT 24
Peak memory 205520 kb
Host smart-96d4e2a0-d95e-4c2c-aa29-95c4725821e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520405671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1520405671
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3591273593
Short name T253
Test name
Test status
Simulation time 87097625 ps
CPU time 2.95 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:27 PM PDT 24
Peak memory 233052 kb
Host smart-ff4f4777-6dcb-4935-a06e-cd9651804241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591273593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3591273593
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3856222582
Short name T551
Test name
Test status
Simulation time 33852281 ps
CPU time 0.76 seconds
Started Aug 16 05:51:19 PM PDT 24
Finished Aug 16 05:51:20 PM PDT 24
Peak memory 207584 kb
Host smart-751548c3-839a-41a4-9857-e7da40882639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856222582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3856222582
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3468875372
Short name T318
Test name
Test status
Simulation time 19828437 ps
CPU time 0.7 seconds
Started Aug 16 05:51:59 PM PDT 24
Finished Aug 16 05:51:59 PM PDT 24
Peak memory 216464 kb
Host smart-f19d2b60-1502-4bcb-9aad-c72a59584668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468875372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3468875372
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3738907580
Short name T567
Test name
Test status
Simulation time 5735146000 ps
CPU time 63.48 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 249192 kb
Host smart-517cfbc5-1ea0-4119-8069-376db05488a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738907580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3738907580
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1238467918
Short name T265
Test name
Test status
Simulation time 186884691303 ps
CPU time 234.61 seconds
Started Aug 16 05:51:17 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 250208 kb
Host smart-2683e016-8453-489b-8acc-e02d14949a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238467918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1238467918
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2190324367
Short name T424
Test name
Test status
Simulation time 989518384 ps
CPU time 12.08 seconds
Started Aug 16 05:52:06 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 250052 kb
Host smart-30883f35-4aa0-4a62-8234-c4d8884ec81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190324367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2190324367
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.333097989
Short name T187
Test name
Test status
Simulation time 189229195504 ps
CPU time 374.31 seconds
Started Aug 16 05:52:09 PM PDT 24
Finished Aug 16 05:58:23 PM PDT 24
Peak memory 266016 kb
Host smart-9c94cb04-1282-44e7-be3c-c49ab0bcf324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333097989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.333097989
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3329978997
Short name T730
Test name
Test status
Simulation time 572691705 ps
CPU time 6.1 seconds
Started Aug 16 05:53:12 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 233496 kb
Host smart-9928bc64-f70f-45ad-b2e6-d9410e7d4c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329978997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3329978997
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2253395213
Short name T671
Test name
Test status
Simulation time 150886844 ps
CPU time 4.02 seconds
Started Aug 16 05:51:20 PM PDT 24
Finished Aug 16 05:51:24 PM PDT 24
Peak memory 233524 kb
Host smart-6d678bce-e673-4656-abfb-ccdd42c2de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253395213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2253395213
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4071135486
Short name T240
Test name
Test status
Simulation time 4420522439 ps
CPU time 5.53 seconds
Started Aug 16 05:52:30 PM PDT 24
Finished Aug 16 05:52:36 PM PDT 24
Peak memory 224472 kb
Host smart-38fff444-eff5-4af5-a7cb-8bfa8ee2b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071135486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4071135486
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.561399452
Short name T860
Test name
Test status
Simulation time 1264586782 ps
CPU time 5.06 seconds
Started Aug 16 05:51:16 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 233508 kb
Host smart-0643b7ce-b760-46c0-88eb-381f7f1a0576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561399452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.561399452
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1080538269
Short name T758
Test name
Test status
Simulation time 627097803 ps
CPU time 3.43 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:28 PM PDT 24
Peak memory 223920 kb
Host smart-b74da217-caa5-4d84-bbe1-9c695747752b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1080538269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1080538269
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.295247018
Short name T853
Test name
Test status
Simulation time 36597711577 ps
CPU time 78.72 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 250212 kb
Host smart-114bbcc4-0b45-48ea-ba7d-effa66e1b616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295247018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.295247018
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2468029127
Short name T927
Test name
Test status
Simulation time 4486670893 ps
CPU time 30.99 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:46 PM PDT 24
Peak memory 217128 kb
Host smart-c3ece8d3-23a5-477a-a427-11face6592a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468029127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2468029127
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2836245456
Short name T62
Test name
Test status
Simulation time 458058753 ps
CPU time 2.12 seconds
Started Aug 16 05:51:11 PM PDT 24
Finished Aug 16 05:51:13 PM PDT 24
Peak memory 208752 kb
Host smart-af75289c-4226-44ef-b8ab-cbd0da9ef296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836245456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2836245456
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3199842558
Short name T932
Test name
Test status
Simulation time 102070403 ps
CPU time 1.21 seconds
Started Aug 16 05:51:20 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 208952 kb
Host smart-bf389f00-0a86-4938-bc5e-6e832945b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199842558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3199842558
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.673793330
Short name T530
Test name
Test status
Simulation time 19464133 ps
CPU time 0.73 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 206292 kb
Host smart-1fdc18a1-4258-4915-aef4-ff8f5e7cdd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673793330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.673793330
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.515197519
Short name T410
Test name
Test status
Simulation time 350187065 ps
CPU time 4.59 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 225084 kb
Host smart-8df7f929-80e0-4e0c-8beb-1a89fdd2f764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515197519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.515197519
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1565783685
Short name T684
Test name
Test status
Simulation time 51123163 ps
CPU time 0.75 seconds
Started Aug 16 05:52:32 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 204472 kb
Host smart-011434b1-9ccc-463e-8360-9a747847d3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565783685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1565783685
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2073109506
Short name T563
Test name
Test status
Simulation time 128011089 ps
CPU time 2.27 seconds
Started Aug 16 05:51:20 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 224840 kb
Host smart-11f26a0b-d8b3-4f5b-8e95-61d971791d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073109506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2073109506
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2571892789
Short name T866
Test name
Test status
Simulation time 18488984 ps
CPU time 0.75 seconds
Started Aug 16 05:51:20 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 206332 kb
Host smart-68387601-f157-4ca6-b454-4fb2e17c0e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571892789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2571892789
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2127765519
Short name T334
Test name
Test status
Simulation time 34502130904 ps
CPU time 97.86 seconds
Started Aug 16 05:53:04 PM PDT 24
Finished Aug 16 05:54:42 PM PDT 24
Peak memory 250144 kb
Host smart-4cf66cfe-3f8e-4679-adf9-9d646836fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127765519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2127765519
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2281908839
Short name T1007
Test name
Test status
Simulation time 9336781651 ps
CPU time 59 seconds
Started Aug 16 05:52:32 PM PDT 24
Finished Aug 16 05:53:32 PM PDT 24
Peak memory 237860 kb
Host smart-a0c265ae-2a8f-47e3-92bc-0165ad27bda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281908839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2281908839
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1452144607
Short name T680
Test name
Test status
Simulation time 64571420076 ps
CPU time 123.58 seconds
Started Aug 16 05:53:02 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 265672 kb
Host smart-f18686ed-504d-42c1-a704-8a2e2c197594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452144607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1452144607
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.401920298
Short name T283
Test name
Test status
Simulation time 7834251704 ps
CPU time 18.31 seconds
Started Aug 16 05:52:32 PM PDT 24
Finished Aug 16 05:52:56 PM PDT 24
Peak memory 232984 kb
Host smart-f4f32229-899c-4d7a-9fac-ef91fcb0adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401920298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.401920298
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4240071761
Short name T85
Test name
Test status
Simulation time 146358145289 ps
CPU time 199.92 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:54:45 PM PDT 24
Peak memory 249956 kb
Host smart-9df83d7d-3069-45a9-bb41-cd01c7b1b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240071761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4240071761
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3735588769
Short name T189
Test name
Test status
Simulation time 2672581588 ps
CPU time 9.66 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 225636 kb
Host smart-c33daa7d-7efd-48fb-804e-2520cb253a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735588769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3735588769
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1825384287
Short name T662
Test name
Test status
Simulation time 510594619 ps
CPU time 2.84 seconds
Started Aug 16 05:53:02 PM PDT 24
Finished Aug 16 05:53:05 PM PDT 24
Peak memory 233388 kb
Host smart-a30fb386-8e90-4923-8519-08e09fcef32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825384287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1825384287
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.23200581
Short name T460
Test name
Test status
Simulation time 438232188 ps
CPU time 4.49 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:06 PM PDT 24
Peak memory 233552 kb
Host smart-4b89bf3e-bfcd-4efd-bc48-e48f895f5ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23200581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.23200581
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4194641698
Short name T582
Test name
Test status
Simulation time 3069849828 ps
CPU time 6.09 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 233540 kb
Host smart-9b7cab58-6157-4e6e-9b58-38f051631b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194641698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4194641698
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4012575115
Short name T534
Test name
Test status
Simulation time 7854070908 ps
CPU time 13.25 seconds
Started Aug 16 05:53:03 PM PDT 24
Finished Aug 16 05:53:17 PM PDT 24
Peak memory 219676 kb
Host smart-8583e795-5bd9-434a-af77-10b15b8eb20d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4012575115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4012575115
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3761894181
Short name T857
Test name
Test status
Simulation time 7428165445 ps
CPU time 91.93 seconds
Started Aug 16 05:51:57 PM PDT 24
Finished Aug 16 05:53:29 PM PDT 24
Peak memory 253148 kb
Host smart-3243f5f8-c4e4-49e3-aa35-23e2968e128f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761894181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3761894181
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2120367993
Short name T620
Test name
Test status
Simulation time 3830740664 ps
CPU time 10.26 seconds
Started Aug 16 05:51:59 PM PDT 24
Finished Aug 16 05:52:09 PM PDT 24
Peak memory 217228 kb
Host smart-a4646cf1-d7a4-4119-83aa-c5b18927a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120367993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2120367993
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2234203938
Short name T440
Test name
Test status
Simulation time 4569607714 ps
CPU time 4.56 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:11 PM PDT 24
Peak memory 217036 kb
Host smart-bc13112c-59ed-41e7-bf6e-02da7cb64cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234203938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2234203938
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3294406413
Short name T585
Test name
Test status
Simulation time 99625313 ps
CPU time 1.06 seconds
Started Aug 16 05:52:32 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 206640 kb
Host smart-fdeda834-91f4-4b1a-b4fa-2bd4ce215100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294406413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3294406413
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1615790065
Short name T848
Test name
Test status
Simulation time 148034014 ps
CPU time 0.81 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:08 PM PDT 24
Peak memory 206676 kb
Host smart-a6f6b193-d924-4c7e-a118-67fcfdac2f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615790065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1615790065
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.994011274
Short name T206
Test name
Test status
Simulation time 529038320 ps
CPU time 6.35 seconds
Started Aug 16 05:52:56 PM PDT 24
Finished Aug 16 05:53:02 PM PDT 24
Peak memory 233392 kb
Host smart-77cb32f5-e7af-44cd-9467-eed101f55552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994011274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.994011274
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2641295424
Short name T368
Test name
Test status
Simulation time 12982216 ps
CPU time 0.7 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:25 PM PDT 24
Peak memory 206240 kb
Host smart-f8d2d6ce-a79e-443c-9682-1adf1c18e418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641295424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2641295424
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.204869156
Short name T980
Test name
Test status
Simulation time 2406059953 ps
CPU time 19.48 seconds
Started Aug 16 05:51:21 PM PDT 24
Finished Aug 16 05:51:41 PM PDT 24
Peak memory 233568 kb
Host smart-0277466a-bc4c-4aa0-aaeb-46b7590a8b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204869156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.204869156
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3877923994
Short name T741
Test name
Test status
Simulation time 14947753 ps
CPU time 0.73 seconds
Started Aug 16 05:52:59 PM PDT 24
Finished Aug 16 05:53:00 PM PDT 24
Peak memory 207532 kb
Host smart-3c9d0cb6-6715-4cff-a3c5-0604951778cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877923994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3877923994
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.680187167
Short name T181
Test name
Test status
Simulation time 50681303192 ps
CPU time 59.1 seconds
Started Aug 16 05:51:56 PM PDT 24
Finished Aug 16 05:52:55 PM PDT 24
Peak memory 250148 kb
Host smart-491b09e4-17f9-4b6e-a7e5-38f1b7371a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680187167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.680187167
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1224530875
Short name T677
Test name
Test status
Simulation time 115717820005 ps
CPU time 261.51 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 252200 kb
Host smart-de165c6b-16bd-4ef7-b811-756667228b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224530875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1224530875
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2982959322
Short name T179
Test name
Test status
Simulation time 351035543819 ps
CPU time 421.15 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:58:29 PM PDT 24
Peak memory 257520 kb
Host smart-49dd17ef-b8d9-4241-890c-7a3d1f0fbef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982959322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2982959322
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3405919172
Short name T771
Test name
Test status
Simulation time 448105560 ps
CPU time 3.78 seconds
Started Aug 16 05:51:15 PM PDT 24
Finished Aug 16 05:51:19 PM PDT 24
Peak memory 225376 kb
Host smart-984b08fd-dcea-4d2d-a1a8-20e750fec395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405919172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3405919172
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3347861692
Short name T53
Test name
Test status
Simulation time 3165747791 ps
CPU time 68.51 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:52:33 PM PDT 24
Peak memory 263472 kb
Host smart-245d942b-88b1-4be8-af17-e0577c214694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347861692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3347861692
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1936806045
Short name T786
Test name
Test status
Simulation time 201929020 ps
CPU time 2.11 seconds
Started Aug 16 05:52:33 PM PDT 24
Finished Aug 16 05:52:35 PM PDT 24
Peak memory 222436 kb
Host smart-7a1be256-48be-4c2a-bc4e-fd342f54e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936806045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1936806045
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.21618495
Short name T765
Test name
Test status
Simulation time 197355587 ps
CPU time 5.93 seconds
Started Aug 16 05:52:57 PM PDT 24
Finished Aug 16 05:53:03 PM PDT 24
Peak memory 240108 kb
Host smart-af528c2e-3a33-4ef5-89db-7caf746f17a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21618495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.21618495
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1101260233
Short name T887
Test name
Test status
Simulation time 10886704095 ps
CPU time 8.13 seconds
Started Aug 16 05:51:19 PM PDT 24
Finished Aug 16 05:51:27 PM PDT 24
Peak memory 225516 kb
Host smart-eaccd023-1e97-43f0-84ba-1d0268fafd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101260233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1101260233
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1639072892
Short name T356
Test name
Test status
Simulation time 638620801 ps
CPU time 4.61 seconds
Started Aug 16 05:52:58 PM PDT 24
Finished Aug 16 05:53:02 PM PDT 24
Peak memory 233404 kb
Host smart-46642a28-8d49-435b-9058-0075806c7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639072892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1639072892
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2873154439
Short name T851
Test name
Test status
Simulation time 1444177009 ps
CPU time 16.16 seconds
Started Aug 16 05:51:49 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 222960 kb
Host smart-1b4bcfa4-bf7e-4c07-a328-fc30f2725a6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2873154439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2873154439
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.96539069
Short name T690
Test name
Test status
Simulation time 19546071846 ps
CPU time 77.47 seconds
Started Aug 16 05:51:55 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 251196 kb
Host smart-48ed58bd-6049-4130-b73c-928a1baa51cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96539069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress
_all.96539069
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4006912289
Short name T511
Test name
Test status
Simulation time 9982014861 ps
CPU time 27.5 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 217120 kb
Host smart-0eccd65d-3c00-4a6b-86a2-3b8e2252b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006912289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4006912289
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.122206994
Short name T342
Test name
Test status
Simulation time 729795010 ps
CPU time 4.76 seconds
Started Aug 16 05:51:24 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 217068 kb
Host smart-7c318173-d8eb-4767-8321-b085d01ea52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122206994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.122206994
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1973491932
Short name T79
Test name
Test status
Simulation time 30048057 ps
CPU time 0.81 seconds
Started Aug 16 05:51:21 PM PDT 24
Finished Aug 16 05:51:22 PM PDT 24
Peak memory 207556 kb
Host smart-bdf4d53a-c6c9-40d7-804c-c8d45dfe7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973491932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1973491932
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.617180706
Short name T352
Test name
Test status
Simulation time 59071934 ps
CPU time 0.75 seconds
Started Aug 16 05:52:58 PM PDT 24
Finished Aug 16 05:52:59 PM PDT 24
Peak memory 206628 kb
Host smart-fab8ca92-f25b-466c-8681-c5ec68323318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617180706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.617180706
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.390840774
Short name T731
Test name
Test status
Simulation time 9566981224 ps
CPU time 29.63 seconds
Started Aug 16 05:51:18 PM PDT 24
Finished Aug 16 05:51:48 PM PDT 24
Peak memory 241768 kb
Host smart-d6d7f97c-8b2a-4e61-a582-e612dec78b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390840774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.390840774
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1947894672
Short name T419
Test name
Test status
Simulation time 20166550 ps
CPU time 0.69 seconds
Started Aug 16 05:49:44 PM PDT 24
Finished Aug 16 05:49:44 PM PDT 24
Peak memory 206168 kb
Host smart-32c6a3f2-e74b-4ae2-b549-d1a449e3deba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947894672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
947894672
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2449747910
Short name T231
Test name
Test status
Simulation time 9699014308 ps
CPU time 8.31 seconds
Started Aug 16 05:49:46 PM PDT 24
Finished Aug 16 05:49:54 PM PDT 24
Peak memory 225480 kb
Host smart-5990ef7d-661e-438b-9355-02a6f7f3ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449747910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2449747910
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.5025272
Short name T779
Test name
Test status
Simulation time 35683908 ps
CPU time 0.82 seconds
Started Aug 16 05:49:37 PM PDT 24
Finished Aug 16 05:49:38 PM PDT 24
Peak memory 207668 kb
Host smart-186878d4-e6cc-44e2-a4c3-0499d44d5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5025272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.5025272
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2152558539
Short name T202
Test name
Test status
Simulation time 133492272687 ps
CPU time 661.41 seconds
Started Aug 16 05:50:21 PM PDT 24
Finished Aug 16 06:01:22 PM PDT 24
Peak memory 271088 kb
Host smart-94628734-8a29-4eb8-ad3b-e4b6470a788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152558539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2152558539
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1718090409
Short name T725
Test name
Test status
Simulation time 3543166730 ps
CPU time 38.29 seconds
Started Aug 16 05:49:51 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 241808 kb
Host smart-e23ab8a8-4a82-4b6c-a221-612c2f119e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718090409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1718090409
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1793312061
Short name T711
Test name
Test status
Simulation time 530198124 ps
CPU time 5.46 seconds
Started Aug 16 05:49:48 PM PDT 24
Finished Aug 16 05:49:53 PM PDT 24
Peak memory 225364 kb
Host smart-3ba4155a-4062-4567-b357-241f89635fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793312061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1793312061
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2961236471
Short name T244
Test name
Test status
Simulation time 244900011709 ps
CPU time 415.64 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:58:05 PM PDT 24
Peak memory 256380 kb
Host smart-73a56a02-7d5e-48e7-9bd4-736b9780a699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961236471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2961236471
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1069518396
Short name T204
Test name
Test status
Simulation time 921225199 ps
CPU time 9.35 seconds
Started Aug 16 05:49:39 PM PDT 24
Finished Aug 16 05:49:49 PM PDT 24
Peak memory 225276 kb
Host smart-8df327f0-5d40-434b-b8a4-9bcd0d1307ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069518396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1069518396
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2900311546
Short name T197
Test name
Test status
Simulation time 10561635152 ps
CPU time 81.15 seconds
Started Aug 16 05:49:36 PM PDT 24
Finished Aug 16 05:50:58 PM PDT 24
Peak memory 241756 kb
Host smart-24ee3fd6-6362-4259-b2df-b4bdc471729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900311546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2900311546
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1654496480
Short name T271
Test name
Test status
Simulation time 18147920044 ps
CPU time 12.8 seconds
Started Aug 16 05:49:38 PM PDT 24
Finished Aug 16 05:49:51 PM PDT 24
Peak memory 225344 kb
Host smart-ba2c063a-93a1-44ec-949f-2659d7491598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654496480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1654496480
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.61010038
Short name T719
Test name
Test status
Simulation time 1370185148 ps
CPU time 6.56 seconds
Started Aug 16 05:50:32 PM PDT 24
Finished Aug 16 05:50:38 PM PDT 24
Peak memory 233540 kb
Host smart-42dbd9d3-1bea-41f5-a979-bf60bb13cc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61010038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.61010038
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2014879136
Short name T476
Test name
Test status
Simulation time 4002904082 ps
CPU time 6.26 seconds
Started Aug 16 05:50:18 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 223964 kb
Host smart-345f6fe3-f1e2-407d-b45f-3fc2d7e22751
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014879136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2014879136
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3183393006
Short name T75
Test name
Test status
Simulation time 120609081 ps
CPU time 1.04 seconds
Started Aug 16 05:50:14 PM PDT 24
Finished Aug 16 05:50:15 PM PDT 24
Peak memory 236556 kb
Host smart-0bdc818b-3170-4b60-a279-3a1b9fa7a95b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183393006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3183393006
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3227462477
Short name T34
Test name
Test status
Simulation time 98420038 ps
CPU time 0.89 seconds
Started Aug 16 05:50:26 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 207464 kb
Host smart-ce604c9c-56d7-47ed-be36-d1d0d21e7c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227462477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3227462477
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.906697422
Short name T28
Test name
Test status
Simulation time 3013991003 ps
CPU time 23.9 seconds
Started Aug 16 05:52:08 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 217080 kb
Host smart-840fee1f-490f-464a-9ca3-4184a03422de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906697422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.906697422
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2791246950
Short name T681
Test name
Test status
Simulation time 10964544418 ps
CPU time 7.11 seconds
Started Aug 16 05:49:35 PM PDT 24
Finished Aug 16 05:49:42 PM PDT 24
Peak memory 217340 kb
Host smart-1f4ba62d-a76f-4875-b040-1df968213c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791246950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2791246950
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.43224047
Short name T525
Test name
Test status
Simulation time 131302277 ps
CPU time 1.57 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:04 PM PDT 24
Peak memory 217040 kb
Host smart-15a62b82-f1f5-4a0a-8955-f2320cb02925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43224047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.43224047
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.213064839
Short name T2
Test name
Test status
Simulation time 109091918 ps
CPU time 0.86 seconds
Started Aug 16 05:49:35 PM PDT 24
Finished Aug 16 05:49:36 PM PDT 24
Peak memory 206808 kb
Host smart-c29999f9-c820-4993-b1a5-6aa5633c86e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213064839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.213064839
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4293401460
Short name T512
Test name
Test status
Simulation time 4819493341 ps
CPU time 12.92 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 233304 kb
Host smart-eff71dcd-160a-4813-beaf-9913b14009d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293401460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4293401460
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.773707848
Short name T650
Test name
Test status
Simulation time 40473201 ps
CPU time 0.71 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:51:27 PM PDT 24
Peak memory 205692 kb
Host smart-597ead51-e87a-4e14-8994-7cfec6c74e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773707848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.773707848
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4266401049
Short name T497
Test name
Test status
Simulation time 2520406897 ps
CPU time 10.1 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:38 PM PDT 24
Peak memory 233692 kb
Host smart-39e445ad-cc35-4025-bfd8-baaef22589fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266401049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4266401049
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2006675955
Short name T367
Test name
Test status
Simulation time 40209617 ps
CPU time 0.79 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:52:02 PM PDT 24
Peak memory 207412 kb
Host smart-86455bd5-ed72-48dd-9653-e968eaa61617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006675955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2006675955
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.737132959
Short name T191
Test name
Test status
Simulation time 32120282721 ps
CPU time 243.71 seconds
Started Aug 16 05:51:48 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 253472 kb
Host smart-fbadcaf9-7ebc-4653-8273-ed1acc8cdf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737132959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.737132959
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2102473499
Short name T210
Test name
Test status
Simulation time 13802887284 ps
CPU time 59.24 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:52:27 PM PDT 24
Peak memory 250084 kb
Host smart-e4014155-b2eb-483b-99ad-97012e2ed945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102473499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2102473499
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.427816170
Short name T430
Test name
Test status
Simulation time 112295980 ps
CPU time 0.97 seconds
Started Aug 16 05:51:30 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 218448 kb
Host smart-5198f841-196c-4778-9738-6c2b46b3e34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427816170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.427816170
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2851843671
Short name T327
Test name
Test status
Simulation time 184237767 ps
CPU time 5.32 seconds
Started Aug 16 05:51:31 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 235264 kb
Host smart-d43ee486-8b2c-41eb-bd5f-2dc2b4bce431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851843671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2851843671
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3747745809
Short name T921
Test name
Test status
Simulation time 764673004 ps
CPU time 9.14 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 225380 kb
Host smart-abb98ebb-eace-4ea2-a767-7014a0c44475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747745809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3747745809
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2011361457
Short name T537
Test name
Test status
Simulation time 9570034138 ps
CPU time 23.96 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:26 PM PDT 24
Peak memory 233764 kb
Host smart-14c3e41e-753b-47ae-9455-898f807e57be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011361457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2011361457
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2132554009
Short name T269
Test name
Test status
Simulation time 891495002 ps
CPU time 8.85 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:38 PM PDT 24
Peak memory 241508 kb
Host smart-377516ae-2508-4376-a1ef-8b843dd5fca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132554009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2132554009
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.341161950
Short name T463
Test name
Test status
Simulation time 2109344851 ps
CPU time 6.08 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:52:09 PM PDT 24
Peak memory 233504 kb
Host smart-c42e2ff0-d466-45a6-8adb-2219a2d80727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341161950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.341161950
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3227798758
Short name T605
Test name
Test status
Simulation time 1666333134 ps
CPU time 12.18 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:40 PM PDT 24
Peak memory 220872 kb
Host smart-b4c0109d-b4c0-4c06-9fbf-4ff8ca3a4574
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227798758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3227798758
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2663841130
Short name T19
Test name
Test status
Simulation time 198455874 ps
CPU time 0.98 seconds
Started Aug 16 05:51:57 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 207380 kb
Host smart-57b67b1f-db06-43a5-a14d-5ad54614c4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663841130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2663841130
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4211051490
Short name T299
Test name
Test status
Simulation time 8750837196 ps
CPU time 26.49 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 220820 kb
Host smart-68a6e272-9a3b-49ca-a0d8-94e0133df040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211051490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4211051490
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2893140901
Short name T956
Test name
Test status
Simulation time 1532699333 ps
CPU time 4.43 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 217176 kb
Host smart-77faa365-bec1-491e-9132-6e26e8a79d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893140901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2893140901
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2725629471
Short name T780
Test name
Test status
Simulation time 33755328 ps
CPU time 1.03 seconds
Started Aug 16 05:51:30 PM PDT 24
Finished Aug 16 05:51:31 PM PDT 24
Peak memory 208752 kb
Host smart-6b262abb-2ac7-4bca-88f8-0e7db80284ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725629471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2725629471
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4160613269
Short name T332
Test name
Test status
Simulation time 23696047 ps
CPU time 0.78 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:28 PM PDT 24
Peak memory 206712 kb
Host smart-a5ff00e4-8db7-43f3-a0e1-5e89c8cfde31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160613269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4160613269
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2171921004
Short name T678
Test name
Test status
Simulation time 167983062 ps
CPU time 2.54 seconds
Started Aug 16 05:52:02 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 235500 kb
Host smart-7040e7ee-f9c0-4842-bc44-4a36b2d1785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171921004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2171921004
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2491635936
Short name T830
Test name
Test status
Simulation time 51823662 ps
CPU time 0.74 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:51:28 PM PDT 24
Peak memory 206244 kb
Host smart-d20920b3-ad60-4d2b-a60b-4c0ff7831c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491635936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2491635936
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1642222626
Short name T635
Test name
Test status
Simulation time 617890562 ps
CPU time 3.52 seconds
Started Aug 16 05:51:30 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 225412 kb
Host smart-4f034255-eb44-4d21-99c1-d6a345102613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642222626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1642222626
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2382454242
Short name T360
Test name
Test status
Simulation time 16041497 ps
CPU time 0.76 seconds
Started Aug 16 05:51:31 PM PDT 24
Finished Aug 16 05:51:32 PM PDT 24
Peak memory 206320 kb
Host smart-535dea4d-71b8-4a5b-8b92-e20311d08d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382454242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2382454242
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3017472391
Short name T656
Test name
Test status
Simulation time 44098596723 ps
CPU time 93.43 seconds
Started Aug 16 05:51:39 PM PDT 24
Finished Aug 16 05:53:13 PM PDT 24
Peak memory 252796 kb
Host smart-0d841b47-98cb-4813-8b37-7afad5fcd0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017472391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3017472391
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1975029601
Short name T965
Test name
Test status
Simulation time 5931186310 ps
CPU time 45.63 seconds
Started Aug 16 05:51:27 PM PDT 24
Finished Aug 16 05:52:13 PM PDT 24
Peak memory 255504 kb
Host smart-b557ba9a-bd01-4c52-82b2-f64591318e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975029601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1975029601
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2924615171
Short name T915
Test name
Test status
Simulation time 2426759341 ps
CPU time 17.95 seconds
Started Aug 16 05:51:30 PM PDT 24
Finished Aug 16 05:51:49 PM PDT 24
Peak memory 241852 kb
Host smart-b8e5e7fc-f787-4352-bf29-0e9799c59291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924615171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2924615171
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.963890308
Short name T531
Test name
Test status
Simulation time 688700075 ps
CPU time 3.85 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 233632 kb
Host smart-949c484c-945f-4ffb-912b-d7cf71ae5151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963890308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.963890308
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2704907363
Short name T547
Test name
Test status
Simulation time 12395229 ps
CPU time 0.73 seconds
Started Aug 16 05:51:56 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 216568 kb
Host smart-c8047960-01a2-4095-bd0f-dfbd47e0b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704907363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2704907363
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3651350359
Short name T366
Test name
Test status
Simulation time 78950919 ps
CPU time 2.7 seconds
Started Aug 16 05:52:13 PM PDT 24
Finished Aug 16 05:52:16 PM PDT 24
Peak memory 233640 kb
Host smart-35bc3396-d695-4232-a783-7e18d693a51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651350359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3651350359
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3511521719
Short name T854
Test name
Test status
Simulation time 39732483217 ps
CPU time 75.74 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:52:42 PM PDT 24
Peak memory 241496 kb
Host smart-3cb6c246-825c-46a0-88ca-f7d9d45d63bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511521719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3511521719
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2407766831
Short name T867
Test name
Test status
Simulation time 1895535990 ps
CPU time 4.48 seconds
Started Aug 16 05:51:58 PM PDT 24
Finished Aug 16 05:52:02 PM PDT 24
Peak memory 233536 kb
Host smart-9a9d2c5d-cc4c-433b-b0f7-2bf9b0f1719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407766831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2407766831
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1153113847
Short name T194
Test name
Test status
Simulation time 5812233546 ps
CPU time 7.29 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 225420 kb
Host smart-9dda93f4-385b-43ab-b929-79985505797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153113847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1153113847
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1737921412
Short name T490
Test name
Test status
Simulation time 1346345458 ps
CPU time 10.69 seconds
Started Aug 16 05:51:25 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 220008 kb
Host smart-144ddccb-b2ab-4928-9643-da96da1e31b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1737921412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1737921412
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2315470004
Short name T683
Test name
Test status
Simulation time 171548811 ps
CPU time 1.03 seconds
Started Aug 16 05:52:09 PM PDT 24
Finished Aug 16 05:52:10 PM PDT 24
Peak memory 207784 kb
Host smart-4db4928b-18e4-41e1-9c2c-df2334a35a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315470004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2315470004
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.951519703
Short name T364
Test name
Test status
Simulation time 225690631 ps
CPU time 2.36 seconds
Started Aug 16 05:51:23 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 217140 kb
Host smart-17dcb89f-6960-40b5-a8d8-5fb929e571f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951519703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.951519703
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1589437900
Short name T949
Test name
Test status
Simulation time 903870734 ps
CPU time 6.71 seconds
Started Aug 16 05:51:48 PM PDT 24
Finished Aug 16 05:51:55 PM PDT 24
Peak memory 217212 kb
Host smart-b9ae5e17-d6e5-42d5-8d8a-09fd54ea2470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589437900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1589437900
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.483244990
Short name T402
Test name
Test status
Simulation time 31138337 ps
CPU time 0.71 seconds
Started Aug 16 05:52:15 PM PDT 24
Finished Aug 16 05:52:16 PM PDT 24
Peak memory 206416 kb
Host smart-260a463f-a105-461a-98cf-63c2719033ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483244990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.483244990
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1833259892
Short name T772
Test name
Test status
Simulation time 194599805 ps
CPU time 0.91 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:52:05 PM PDT 24
Peak memory 206864 kb
Host smart-359b29a7-a9c8-4b97-8e88-c55b5f85f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833259892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1833259892
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2381291706
Short name T213
Test name
Test status
Simulation time 7683821035 ps
CPU time 16.15 seconds
Started Aug 16 05:51:41 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 225520 kb
Host smart-4c6c3064-c478-4fe7-a101-d7094bc76c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381291706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2381291706
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3607692118
Short name T821
Test name
Test status
Simulation time 22738379 ps
CPU time 0.72 seconds
Started Aug 16 05:51:41 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 206124 kb
Host smart-dc2a7106-6acb-4377-97b7-b12e5e4a3130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607692118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3607692118
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1803789684
Short name T438
Test name
Test status
Simulation time 320924328 ps
CPU time 4.83 seconds
Started Aug 16 05:51:32 PM PDT 24
Finished Aug 16 05:51:37 PM PDT 24
Peak memory 233600 kb
Host smart-b91409a7-6e48-4f53-8c35-c3d1559db4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803789684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1803789684
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1995328688
Short name T574
Test name
Test status
Simulation time 21346246 ps
CPU time 0.78 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:52:04 PM PDT 24
Peak memory 207472 kb
Host smart-37265b36-39b9-47c3-b44d-f4bf02b56edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995328688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1995328688
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3964669638
Short name T995
Test name
Test status
Simulation time 28616891427 ps
CPU time 199.7 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 252468 kb
Host smart-857a92e8-938e-493a-ab4f-5ea802d19217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964669638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3964669638
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1873580253
Short name T243
Test name
Test status
Simulation time 18005303325 ps
CPU time 226.35 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:55:21 PM PDT 24
Peak memory 258300 kb
Host smart-c45c03e3-33f9-4fb6-8f75-c6cb1f303a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873580253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1873580253
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.514955015
Short name T994
Test name
Test status
Simulation time 1994258639 ps
CPU time 15.35 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 241784 kb
Host smart-9b1df98e-4c2b-46ce-8bea-df768254a9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514955015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.514955015
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1549746882
Short name T322
Test name
Test status
Simulation time 1311482707 ps
CPU time 7.1 seconds
Started Aug 16 05:52:15 PM PDT 24
Finished Aug 16 05:52:23 PM PDT 24
Peak memory 225448 kb
Host smart-fe4fa2f5-42e7-4867-9346-7a7db4b81682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549746882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1549746882
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1389028367
Short name T629
Test name
Test status
Simulation time 441269194 ps
CPU time 7.39 seconds
Started Aug 16 05:51:48 PM PDT 24
Finished Aug 16 05:51:55 PM PDT 24
Peak memory 225304 kb
Host smart-6b28d67e-bbf2-4bfe-930c-dd10ac184cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389028367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1389028367
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.650415297
Short name T503
Test name
Test status
Simulation time 551323265 ps
CPU time 9.19 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 241600 kb
Host smart-2ed82360-383d-4d05-b9ff-2cdbf129e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650415297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.650415297
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.837470890
Short name T734
Test name
Test status
Simulation time 11888397994 ps
CPU time 9.38 seconds
Started Aug 16 05:52:08 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 233640 kb
Host smart-f95a9b06-78dc-49ef-a083-d928009c9bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837470890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.837470890
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3463552421
Short name T704
Test name
Test status
Simulation time 255877551 ps
CPU time 3.33 seconds
Started Aug 16 05:51:32 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 225252 kb
Host smart-d1ade01d-7fab-4419-96d7-4555aadb40dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463552421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3463552421
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4121269334
Short name T40
Test name
Test status
Simulation time 507168940 ps
CPU time 5.91 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:51:40 PM PDT 24
Peak memory 223292 kb
Host smart-754c9cf0-af28-4b8a-8f0f-3ec37fdacb6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4121269334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4121269334
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4088411439
Short name T17
Test name
Test status
Simulation time 51047406 ps
CPU time 1.05 seconds
Started Aug 16 05:51:55 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 207784 kb
Host smart-5fa8fc52-33e3-48a6-9382-42d086973d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088411439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4088411439
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.755623267
Short name T643
Test name
Test status
Simulation time 2244812611 ps
CPU time 23.94 seconds
Started Aug 16 05:51:59 PM PDT 24
Finished Aug 16 05:52:23 PM PDT 24
Peak memory 217304 kb
Host smart-586ab227-078e-4e33-af7f-e7cd64875594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755623267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.755623267
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.398965375
Short name T369
Test name
Test status
Simulation time 1507160532 ps
CPU time 4.39 seconds
Started Aug 16 05:51:26 PM PDT 24
Finished Aug 16 05:51:30 PM PDT 24
Peak memory 217108 kb
Host smart-e8345c87-50ca-4cc0-8356-599fc6d23302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398965375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.398965375
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.303586769
Short name T834
Test name
Test status
Simulation time 180707346 ps
CPU time 3.22 seconds
Started Aug 16 05:52:14 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 217144 kb
Host smart-ca0f999d-873b-4cb2-939a-853ac625da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303586769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.303586769
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3364204208
Short name T653
Test name
Test status
Simulation time 59941676 ps
CPU time 0.88 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 05:52:09 PM PDT 24
Peak memory 207880 kb
Host smart-ff4d40dc-33f6-48d1-af77-cb87b4ad6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364204208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3364204208
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3736516788
Short name T826
Test name
Test status
Simulation time 28358411448 ps
CPU time 23.45 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:52:00 PM PDT 24
Peak memory 240908 kb
Host smart-7a54a849-6e42-45c9-b89e-1f970393cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736516788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3736516788
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1125012822
Short name T709
Test name
Test status
Simulation time 15772164 ps
CPU time 0.77 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 206224 kb
Host smart-31b8e069-f9da-48e4-bd0e-1894c3808119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125012822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1125012822
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2743297740
Short name T945
Test name
Test status
Simulation time 1576492179 ps
CPU time 5.38 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:43 PM PDT 24
Peak memory 225320 kb
Host smart-4e481bce-8344-4516-9541-07228ea6c7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743297740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2743297740
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2735363425
Short name T391
Test name
Test status
Simulation time 59034091 ps
CPU time 0.78 seconds
Started Aug 16 05:52:00 PM PDT 24
Finished Aug 16 05:52:01 PM PDT 24
Peak memory 207392 kb
Host smart-0cde64de-0466-4121-9c32-34e575180717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735363425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2735363425
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1764638885
Short name T1005
Test name
Test status
Simulation time 5993081751 ps
CPU time 103.34 seconds
Started Aug 16 05:51:31 PM PDT 24
Finished Aug 16 05:53:14 PM PDT 24
Peak memory 255048 kb
Host smart-31103d64-05df-450e-8d35-2808537f4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764638885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1764638885
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2348108656
Short name T298
Test name
Test status
Simulation time 25481319841 ps
CPU time 54.54 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:52:58 PM PDT 24
Peak memory 250196 kb
Host smart-f375d60b-8b15-4a56-b599-e607d74a3f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348108656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2348108656
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4139552981
Short name T474
Test name
Test status
Simulation time 1807108177 ps
CPU time 24.26 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:52:27 PM PDT 24
Peak memory 220308 kb
Host smart-f3cd4cd1-9a2d-49bc-a323-f53e71faadee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139552981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4139552981
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.779443657
Short name T288
Test name
Test status
Simulation time 1388509683 ps
CPU time 11.33 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:48 PM PDT 24
Peak memory 241720 kb
Host smart-53e7b5d9-7c72-472f-8ec0-ddb98ca47508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779443657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.779443657
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.323295879
Short name T162
Test name
Test status
Simulation time 18927820896 ps
CPU time 120.85 seconds
Started Aug 16 05:52:13 PM PDT 24
Finished Aug 16 05:54:14 PM PDT 24
Peak memory 249968 kb
Host smart-6591419d-ca36-41c2-9ad4-73bfdcf5a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323295879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.323295879
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2423931848
Short name T248
Test name
Test status
Simulation time 2474634153 ps
CPU time 9.35 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:46 PM PDT 24
Peak memory 225424 kb
Host smart-8d6b631b-d2ff-470a-8d31-986bf4ce1f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423931848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2423931848
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2875737059
Short name T580
Test name
Test status
Simulation time 14636483942 ps
CPU time 66.02 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:52:40 PM PDT 24
Peak memory 233708 kb
Host smart-400d845f-0df2-4af9-9228-ca199cb18ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875737059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2875737059
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3331027231
Short name T807
Test name
Test status
Simulation time 16488550333 ps
CPU time 7.19 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:52:23 PM PDT 24
Peak memory 233600 kb
Host smart-1ae0e15a-b990-45e1-9945-86d9b8363536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331027231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3331027231
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1592427297
Short name T221
Test name
Test status
Simulation time 24931533498 ps
CPU time 16.35 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:51:50 PM PDT 24
Peak memory 241836 kb
Host smart-02eeacd7-f9c9-4d2a-9169-bb8c14321bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592427297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1592427297
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.722710096
Short name T564
Test name
Test status
Simulation time 370333955 ps
CPU time 4.33 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 219640 kb
Host smart-242779aa-8757-40ea-8d9b-8438a5c72bc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=722710096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.722710096
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1727415350
Short name T767
Test name
Test status
Simulation time 45343091905 ps
CPU time 341.01 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:57:16 PM PDT 24
Peak memory 250760 kb
Host smart-662765e9-afa6-4e8d-bf3e-13288f4617f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727415350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1727415350
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3370351027
Short name T477
Test name
Test status
Simulation time 960132055 ps
CPU time 15.28 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 05:52:23 PM PDT 24
Peak memory 217248 kb
Host smart-b0053e6e-5ac5-488e-8ae7-473adf3ee8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370351027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3370351027
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3542770582
Short name T697
Test name
Test status
Simulation time 21834419063 ps
CPU time 7.65 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:52:09 PM PDT 24
Peak memory 217376 kb
Host smart-004bb87c-71cf-47a9-bfdc-6f0d218daf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542770582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3542770582
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3742451247
Short name T803
Test name
Test status
Simulation time 253394416 ps
CPU time 7.47 seconds
Started Aug 16 05:52:06 PM PDT 24
Finished Aug 16 05:52:14 PM PDT 24
Peak memory 217076 kb
Host smart-9cf3d85f-e655-42ce-b057-fd9eea964e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742451247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3742451247
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4175728365
Short name T447
Test name
Test status
Simulation time 55691635 ps
CPU time 0.81 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 05:52:08 PM PDT 24
Peak memory 206824 kb
Host smart-a588f5e7-3bee-4b36-8d88-c4e435c07d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175728365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4175728365
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3382643469
Short name T7
Test name
Test status
Simulation time 107047880 ps
CPU time 3.68 seconds
Started Aug 16 05:51:54 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 233620 kb
Host smart-2d776f7d-5370-4481-875c-bbe533f0cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382643469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3382643469
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3525617163
Short name T68
Test name
Test status
Simulation time 12040512 ps
CPU time 0.73 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 205688 kb
Host smart-dcf52281-b08f-4936-9e97-93f908080d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525617163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3525617163
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1815182729
Short name T801
Test name
Test status
Simulation time 627837903 ps
CPU time 10.04 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:48 PM PDT 24
Peak memory 225272 kb
Host smart-a309b00d-d9b3-4cd5-8599-bdd07bbf1ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815182729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1815182729
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3214676583
Short name T404
Test name
Test status
Simulation time 20075367 ps
CPU time 0.79 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:38 PM PDT 24
Peak memory 207664 kb
Host smart-337bd213-12cb-446f-ad09-2706d7edfaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214676583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3214676583
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2379629584
Short name T817
Test name
Test status
Simulation time 627331549 ps
CPU time 10.4 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 239116 kb
Host smart-e4e7814c-145c-4fa4-ade2-363b639b06d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379629584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2379629584
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.500420205
Short name T707
Test name
Test status
Simulation time 20297361413 ps
CPU time 79.53 seconds
Started Aug 16 05:52:08 PM PDT 24
Finished Aug 16 05:53:28 PM PDT 24
Peak memory 250400 kb
Host smart-4f0b6140-1f19-4d45-9505-205c1b2a3db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500420205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.500420205
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1384580075
Short name T26
Test name
Test status
Simulation time 71621656944 ps
CPU time 204.3 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:55:00 PM PDT 24
Peak memory 250220 kb
Host smart-4553b710-0b6b-4b93-92fd-bb9d3c65bb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384580075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1384580075
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2280144924
Short name T340
Test name
Test status
Simulation time 2103943850 ps
CPU time 6.22 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:42 PM PDT 24
Peak memory 241764 kb
Host smart-7a0c4687-16c5-4d46-9590-eaa477c6a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280144924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2280144924
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2239449610
Short name T425
Test name
Test status
Simulation time 32183850411 ps
CPU time 61.79 seconds
Started Aug 16 05:51:48 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 250844 kb
Host smart-f72b9b67-c84f-4822-ad0a-618b856385c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239449610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2239449610
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3835931808
Short name T448
Test name
Test status
Simulation time 237692629 ps
CPU time 3.32 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:39 PM PDT 24
Peak memory 233612 kb
Host smart-a530e78d-94a0-4b4f-8f46-2f2ddcb3bd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835931808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3835931808
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1022483984
Short name T64
Test name
Test status
Simulation time 55760834 ps
CPU time 2.69 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 05:52:10 PM PDT 24
Peak memory 233580 kb
Host smart-13d67717-2fd3-43ae-a3e8-faf1daf6b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022483984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1022483984
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1945858883
Short name T971
Test name
Test status
Simulation time 723135668 ps
CPU time 3.39 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:51:37 PM PDT 24
Peak memory 225292 kb
Host smart-3e42c797-0ac5-498d-b23d-53bf18e9c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945858883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1945858883
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.697948865
Short name T925
Test name
Test status
Simulation time 929297711 ps
CPU time 3.91 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 225324 kb
Host smart-2eee14e3-1f35-449b-a5f1-9a9cb8e8899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697948865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.697948865
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3474523252
Short name T47
Test name
Test status
Simulation time 212694289 ps
CPU time 4.27 seconds
Started Aug 16 05:51:48 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 223896 kb
Host smart-3e2207f7-0c11-4210-9be6-917805100f9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3474523252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3474523252
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2830445178
Short name T275
Test name
Test status
Simulation time 118037545955 ps
CPU time 336.93 seconds
Started Aug 16 05:51:59 PM PDT 24
Finished Aug 16 05:57:36 PM PDT 24
Peak memory 270596 kb
Host smart-2b9d820b-bad4-44d6-b1f6-438958a81f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830445178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2830445178
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1862671752
Short name T487
Test name
Test status
Simulation time 16638954109 ps
CPU time 26.07 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:52:02 PM PDT 24
Peak memory 217196 kb
Host smart-ec40eb13-20b1-4e9f-81f3-056a00b41b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862671752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1862671752
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2655288959
Short name T572
Test name
Test status
Simulation time 9184250059 ps
CPU time 6.13 seconds
Started Aug 16 05:52:13 PM PDT 24
Finished Aug 16 05:52:19 PM PDT 24
Peak memory 217260 kb
Host smart-b078252d-b161-4cc8-b9df-fe3ac5ff482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655288959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2655288959
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4046942818
Short name T10
Test name
Test status
Simulation time 23898924 ps
CPU time 0.96 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:51:35 PM PDT 24
Peak memory 207916 kb
Host smart-10da7691-de10-4db3-a66b-322f733583b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046942818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4046942818
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3442130136
Short name T326
Test name
Test status
Simulation time 65480078 ps
CPU time 0.74 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:51:34 PM PDT 24
Peak memory 206832 kb
Host smart-f7c45393-cab7-48d2-b82c-a7da7942b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442130136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3442130136
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2199238405
Short name T223
Test name
Test status
Simulation time 12331785867 ps
CPU time 5.72 seconds
Started Aug 16 05:51:35 PM PDT 24
Finished Aug 16 05:51:41 PM PDT 24
Peak memory 233676 kb
Host smart-78005a9d-403f-4b40-b027-eeeb83b84c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199238405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2199238405
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1991531129
Short name T57
Test name
Test status
Simulation time 12149889 ps
CPU time 0.73 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 206200 kb
Host smart-839bf38e-be4a-4e16-b47b-1e3a80552ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991531129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1991531129
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.764669991
Short name T256
Test name
Test status
Simulation time 1757157169 ps
CPU time 15.69 seconds
Started Aug 16 05:52:12 PM PDT 24
Finished Aug 16 05:52:28 PM PDT 24
Peak memory 233580 kb
Host smart-e1e0ad99-2275-4bd6-b18b-a2819b5e22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764669991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.764669991
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1488377400
Short name T996
Test name
Test status
Simulation time 66180745 ps
CPU time 0.78 seconds
Started Aug 16 05:51:57 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 207348 kb
Host smart-0fa18075-540e-4ea0-9854-c91764662528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488377400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1488377400
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1522346273
Short name T401
Test name
Test status
Simulation time 32658829548 ps
CPU time 51.79 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:52:36 PM PDT 24
Peak memory 225380 kb
Host smart-32ca5e43-b9b0-45d4-9b94-f6877812d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522346273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1522346273
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1673374066
Short name T769
Test name
Test status
Simulation time 27642039880 ps
CPU time 129.28 seconds
Started Aug 16 05:52:11 PM PDT 24
Finished Aug 16 05:54:20 PM PDT 24
Peak memory 250152 kb
Host smart-953d4068-99de-4973-ab28-f381d62b8d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673374066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1673374066
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2108190535
Short name T451
Test name
Test status
Simulation time 92161115664 ps
CPU time 186.15 seconds
Started Aug 16 05:52:03 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 268144 kb
Host smart-57716e6f-17f3-4130-bfdc-91491c37a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108190535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2108190535
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2820477543
Short name T766
Test name
Test status
Simulation time 376772293 ps
CPU time 12.46 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:49 PM PDT 24
Peak memory 233508 kb
Host smart-1ab9828a-f27e-4678-af1d-818e6996566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820477543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2820477543
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3622465173
Short name T24
Test name
Test status
Simulation time 41334535992 ps
CPU time 185.13 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 256732 kb
Host smart-15f311f7-1901-4535-a75b-b8c7d63c573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622465173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3622465173
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.998910635
Short name T227
Test name
Test status
Simulation time 146318439 ps
CPU time 2.7 seconds
Started Aug 16 05:52:13 PM PDT 24
Finished Aug 16 05:52:16 PM PDT 24
Peak memory 225400 kb
Host smart-3f621ecb-4044-40c8-b6cb-f0f172fb5d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998910635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.998910635
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1586823117
Short name T935
Test name
Test status
Simulation time 452377031 ps
CPU time 10.9 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:48 PM PDT 24
Peak memory 241532 kb
Host smart-fc1bb4ca-17eb-4766-9851-1f85cb7ffec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586823117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1586823117
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.674389055
Short name T239
Test name
Test status
Simulation time 4309132810 ps
CPU time 13.49 seconds
Started Aug 16 05:52:00 PM PDT 24
Finished Aug 16 05:52:14 PM PDT 24
Peak memory 225460 kb
Host smart-23ddd3af-dadf-4934-b9b3-5d97ca00aacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674389055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.674389055
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2355579665
Short name T577
Test name
Test status
Simulation time 189738599 ps
CPU time 2.72 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:41 PM PDT 24
Peak memory 233532 kb
Host smart-324271cd-7e32-4b60-8c62-658c2ebfa234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355579665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2355579665
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1701496390
Short name T785
Test name
Test status
Simulation time 1508411046 ps
CPU time 7.87 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 223944 kb
Host smart-d5dc14da-96bd-4c4b-902e-449396b50a53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701496390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1701496390
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.406067247
Short name T597
Test name
Test status
Simulation time 51002984838 ps
CPU time 149.29 seconds
Started Aug 16 05:51:42 PM PDT 24
Finished Aug 16 05:54:12 PM PDT 24
Peak memory 274356 kb
Host smart-16527d87-e003-4586-b79d-cbb2d15b140e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406067247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.406067247
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3878274487
Short name T989
Test name
Test status
Simulation time 25777894 ps
CPU time 0.7 seconds
Started Aug 16 05:51:58 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 206544 kb
Host smart-264a6998-5464-4f77-ace2-17eb8dfcd9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878274487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3878274487
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1303380246
Short name T93
Test name
Test status
Simulation time 39935097597 ps
CPU time 9.33 seconds
Started Aug 16 05:52:10 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 217484 kb
Host smart-5275eaac-ce07-40c2-81d6-43fc67bd6b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303380246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1303380246
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2333241573
Short name T901
Test name
Test status
Simulation time 87360940 ps
CPU time 1.62 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:39 PM PDT 24
Peak memory 217368 kb
Host smart-169a6f21-7d58-4a0d-9e73-b095707698e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333241573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2333241573
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2439000915
Short name T4
Test name
Test status
Simulation time 1538349077 ps
CPU time 0.95 seconds
Started Aug 16 05:51:38 PM PDT 24
Finished Aug 16 05:51:39 PM PDT 24
Peak memory 206804 kb
Host smart-44906857-846d-4ff8-8fa5-55f3508c0266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439000915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2439000915
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1022636384
Short name T858
Test name
Test status
Simulation time 82004099940 ps
CPU time 17.01 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 233800 kb
Host smart-1571551f-591a-41b9-b3bf-798602921b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022636384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1022636384
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3675816364
Short name T359
Test name
Test status
Simulation time 16170882 ps
CPU time 0.76 seconds
Started Aug 16 05:52:01 PM PDT 24
Finished Aug 16 05:52:02 PM PDT 24
Peak memory 205552 kb
Host smart-cb3e107d-cfd7-4e07-9a60-1d6ce7b0ba04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675816364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3675816364
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1925860077
Short name T516
Test name
Test status
Simulation time 664371818 ps
CPU time 4.8 seconds
Started Aug 16 05:51:41 PM PDT 24
Finished Aug 16 05:51:46 PM PDT 24
Peak memory 233552 kb
Host smart-f5ef8e69-5b32-44af-abab-89b6dc0abed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925860077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1925860077
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.745932915
Short name T999
Test name
Test status
Simulation time 50058731 ps
CPU time 0.81 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:51:46 PM PDT 24
Peak memory 206360 kb
Host smart-e29d120d-bca4-43f3-943a-f9146033e30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745932915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.745932915
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2789442834
Short name T862
Test name
Test status
Simulation time 54103216 ps
CPU time 0.78 seconds
Started Aug 16 05:51:43 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 216744 kb
Host smart-f97111b8-9d72-4781-9d76-65079019ae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789442834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2789442834
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.809535760
Short name T1004
Test name
Test status
Simulation time 3030292474 ps
CPU time 40.07 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:52:25 PM PDT 24
Peak memory 236536 kb
Host smart-c24271ad-abf1-4c15-aa16-7893d40dc6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809535760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.809535760
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2017767809
Short name T287
Test name
Test status
Simulation time 3198049249 ps
CPU time 13.69 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:51:58 PM PDT 24
Peak memory 241872 kb
Host smart-c600b5c0-618a-435e-94fa-26a04da847c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017767809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2017767809
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3486577718
Short name T234
Test name
Test status
Simulation time 35748681767 ps
CPU time 92.08 seconds
Started Aug 16 05:51:46 PM PDT 24
Finished Aug 16 05:53:19 PM PDT 24
Peak memory 254348 kb
Host smart-37d6d7ff-01ba-4be3-9975-e5c6328fe4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486577718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3486577718
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.418072812
Short name T255
Test name
Test status
Simulation time 1280276162 ps
CPU time 6.26 seconds
Started Aug 16 05:51:46 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 233604 kb
Host smart-53b3f3e2-651c-4ef2-ac94-67dd5cec260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418072812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.418072812
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1986927301
Short name T177
Test name
Test status
Simulation time 8785347943 ps
CPU time 11.6 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 233692 kb
Host smart-c7f75f09-2210-48c3-b3b1-9113e843e240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986927301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1986927301
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.651777767
Short name T363
Test name
Test status
Simulation time 808743509 ps
CPU time 6.14 seconds
Started Aug 16 05:51:47 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 233540 kb
Host smart-7fd2aa78-9c9f-4e0f-824d-a7ed53214e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651777767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.651777767
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1991517991
Short name T886
Test name
Test status
Simulation time 64842893419 ps
CPU time 19.81 seconds
Started Aug 16 05:51:58 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 233560 kb
Host smart-a77ec8fe-201e-4a63-ac9c-d1f093aa937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991517991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1991517991
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3173120041
Short name T328
Test name
Test status
Simulation time 466602797 ps
CPU time 5.22 seconds
Started Aug 16 05:52:15 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 221304 kb
Host smart-d9c07ef1-af5a-4ed9-a598-b75e61fa77f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3173120041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3173120041
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4165602048
Short name T702
Test name
Test status
Simulation time 70134480540 ps
CPU time 32.26 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 220916 kb
Host smart-d75c248f-b50b-4677-b1ca-23697fc33495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165602048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4165602048
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1114638702
Short name T977
Test name
Test status
Simulation time 11111358 ps
CPU time 0.71 seconds
Started Aug 16 05:51:43 PM PDT 24
Finished Aug 16 05:51:44 PM PDT 24
Peak memory 206492 kb
Host smart-df4d0d98-9a46-43cf-8164-dd747535fa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114638702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1114638702
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2142826161
Short name T439
Test name
Test status
Simulation time 38203775 ps
CPU time 1.41 seconds
Started Aug 16 05:51:45 PM PDT 24
Finished Aug 16 05:51:47 PM PDT 24
Peak memory 217216 kb
Host smart-4d14d6b5-1abf-4b57-bb12-567439f466e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142826161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2142826161
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3248243613
Short name T32
Test name
Test status
Simulation time 16799702 ps
CPU time 0.74 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 206832 kb
Host smart-07e49d0e-aafc-4b79-87e5-d404ca8313ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248243613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3248243613
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2820614463
Short name T943
Test name
Test status
Simulation time 5882192757 ps
CPU time 18.79 seconds
Started Aug 16 05:51:58 PM PDT 24
Finished Aug 16 05:52:17 PM PDT 24
Peak memory 233672 kb
Host smart-67723389-c6d0-45f5-8016-db85b6c023b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820614463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2820614463
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1042772180
Short name T437
Test name
Test status
Simulation time 41393683 ps
CPU time 0.68 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:51 PM PDT 24
Peak memory 205676 kb
Host smart-ff8bdc54-9ec9-4051-88ce-2d0c5146a49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042772180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1042772180
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3526780130
Short name T942
Test name
Test status
Simulation time 56461952 ps
CPU time 2.13 seconds
Started Aug 16 05:51:53 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 225284 kb
Host smart-5872d7fe-c544-4fb9-abd2-285e2c2bdc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526780130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3526780130
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.907603127
Short name T575
Test name
Test status
Simulation time 45225080 ps
CPU time 0.74 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 207380 kb
Host smart-f026210c-01b1-4705-94b2-1107f620543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907603127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.907603127
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2389220635
Short name T955
Test name
Test status
Simulation time 7796370895 ps
CPU time 28.13 seconds
Started Aug 16 05:52:21 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 250032 kb
Host smart-63f69d77-aaf6-4ce7-b21c-aca099f17af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389220635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2389220635
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3449381174
Short name T44
Test name
Test status
Simulation time 106986028023 ps
CPU time 411.4 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:59:14 PM PDT 24
Peak memory 256500 kb
Host smart-f788dd71-9220-4018-9d6f-5fce343f5858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449381174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3449381174
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2826557012
Short name T173
Test name
Test status
Simulation time 26200314007 ps
CPU time 116.07 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:54:18 PM PDT 24
Peak memory 252000 kb
Host smart-bdbaf9f9-fe74-4a1f-819e-5491b6c48308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826557012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2826557012
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.635436244
Short name T532
Test name
Test status
Simulation time 215338137 ps
CPU time 7.56 seconds
Started Aug 16 05:52:15 PM PDT 24
Finished Aug 16 05:52:23 PM PDT 24
Peak memory 238516 kb
Host smart-7fdc24ec-64bb-4318-8b6c-5199a7d57720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635436244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.635436244
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1240453505
Short name T831
Test name
Test status
Simulation time 4377668016 ps
CPU time 60.67 seconds
Started Aug 16 05:52:20 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 269920 kb
Host smart-53d10149-5416-48f0-8dc5-d0f42fa52cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240453505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1240453505
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2334060330
Short name T94
Test name
Test status
Simulation time 1175966948 ps
CPU time 7.41 seconds
Started Aug 16 05:51:43 PM PDT 24
Finished Aug 16 05:51:50 PM PDT 24
Peak memory 233532 kb
Host smart-e03b948f-bc6c-4beb-bed2-f269f2abcbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334060330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2334060330
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2389680086
Short name T226
Test name
Test status
Simulation time 3091506854 ps
CPU time 34.16 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:52:50 PM PDT 24
Peak memory 233656 kb
Host smart-275908cf-be31-4ce2-a883-aaf7906da7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389680086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2389680086
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3067933810
Short name T270
Test name
Test status
Simulation time 24429581786 ps
CPU time 16.69 seconds
Started Aug 16 05:51:58 PM PDT 24
Finished Aug 16 05:52:15 PM PDT 24
Peak memory 233604 kb
Host smart-83e8d935-2a44-43b8-a892-01c7737769d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067933810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3067933810
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2647843210
Short name T961
Test name
Test status
Simulation time 761890150 ps
CPU time 3.44 seconds
Started Aug 16 05:52:12 PM PDT 24
Finished Aug 16 05:52:15 PM PDT 24
Peak memory 233620 kb
Host smart-2dd7ef22-f0f3-4376-8a4f-69418b075b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647843210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2647843210
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3993531641
Short name T357
Test name
Test status
Simulation time 627124464 ps
CPU time 7.81 seconds
Started Aug 16 05:51:52 PM PDT 24
Finished Aug 16 05:52:00 PM PDT 24
Peak memory 220440 kb
Host smart-d778b23a-e834-4ff4-8046-30a5a4913d37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3993531641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3993531641
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2664826848
Short name T33
Test name
Test status
Simulation time 286476536876 ps
CPU time 602.64 seconds
Started Aug 16 05:52:07 PM PDT 24
Finished Aug 16 06:02:10 PM PDT 24
Peak memory 274552 kb
Host smart-5d191ecb-d84d-4a62-9e86-76fb17dbb916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664826848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2664826848
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3420980306
Short name T596
Test name
Test status
Simulation time 14030242739 ps
CPU time 31.42 seconds
Started Aug 16 05:51:46 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 217304 kb
Host smart-c7519cfd-844d-422e-8692-2098ba506773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420980306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3420980306
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1787375699
Short name T658
Test name
Test status
Simulation time 4933054382 ps
CPU time 13.31 seconds
Started Aug 16 05:51:43 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 217284 kb
Host smart-e707fe4a-396b-4338-9538-6cc9f06ee59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787375699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1787375699
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3534360062
Short name T844
Test name
Test status
Simulation time 649376034 ps
CPU time 3.31 seconds
Started Aug 16 05:51:47 PM PDT 24
Finished Aug 16 05:51:50 PM PDT 24
Peak memory 217096 kb
Host smart-a4cb20ef-0d62-406c-aaa5-80b78fdb9abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534360062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3534360062
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4292094638
Short name T156
Test name
Test status
Simulation time 32592162 ps
CPU time 0.69 seconds
Started Aug 16 05:51:44 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 206820 kb
Host smart-397f2781-575e-4da3-b833-a1be8a5522ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292094638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4292094638
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.923134355
Short name T592
Test name
Test status
Simulation time 236699824 ps
CPU time 2.29 seconds
Started Aug 16 05:52:47 PM PDT 24
Finished Aug 16 05:52:49 PM PDT 24
Peak memory 225008 kb
Host smart-9b45f316-9a0a-4c8b-b28e-0af6ab559776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923134355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.923134355
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3046138211
Short name T933
Test name
Test status
Simulation time 66780332 ps
CPU time 0.71 seconds
Started Aug 16 05:51:55 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 206160 kb
Host smart-07659f39-0960-4cbc-82a8-8cdf880260a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046138211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3046138211
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1496415703
Short name T856
Test name
Test status
Simulation time 60664389 ps
CPU time 2.48 seconds
Started Aug 16 05:51:52 PM PDT 24
Finished Aug 16 05:51:55 PM PDT 24
Peak memory 233536 kb
Host smart-9028c919-c4eb-41d9-ae02-d3b1b57ac4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496415703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1496415703
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1751433003
Short name T67
Test name
Test status
Simulation time 22249210 ps
CPU time 0.77 seconds
Started Aug 16 05:53:07 PM PDT 24
Finished Aug 16 05:53:07 PM PDT 24
Peak memory 207588 kb
Host smart-366c2654-8a5a-4cdb-8a4d-ab369c339b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751433003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1751433003
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1092557664
Short name T648
Test name
Test status
Simulation time 29624674269 ps
CPU time 131.72 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:54:34 PM PDT 24
Peak memory 233872 kb
Host smart-d86cee21-e917-4c68-b8b3-a3de2b640a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092557664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1092557664
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3224054104
Short name T263
Test name
Test status
Simulation time 37492449988 ps
CPU time 91.38 seconds
Started Aug 16 05:51:49 PM PDT 24
Finished Aug 16 05:53:21 PM PDT 24
Peak memory 252004 kb
Host smart-bc5dad76-81c2-48eb-af98-db28bf071aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224054104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3224054104
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1686893128
Short name T863
Test name
Test status
Simulation time 1580316289 ps
CPU time 23.33 seconds
Started Aug 16 05:52:19 PM PDT 24
Finished Aug 16 05:52:43 PM PDT 24
Peak memory 239180 kb
Host smart-16569846-3445-49d4-b866-204b178f7923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686893128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1686893128
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3190990190
Short name T861
Test name
Test status
Simulation time 11748610809 ps
CPU time 40.28 seconds
Started Aug 16 05:52:20 PM PDT 24
Finished Aug 16 05:53:01 PM PDT 24
Peak memory 241908 kb
Host smart-6b2a3e87-7bc8-4633-95a3-96d4023dfc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190990190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3190990190
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1501132492
Short name T409
Test name
Test status
Simulation time 1882907891 ps
CPU time 17.34 seconds
Started Aug 16 05:51:52 PM PDT 24
Finished Aug 16 05:52:10 PM PDT 24
Peak memory 233516 kb
Host smart-5952932a-593c-414b-9710-56155ba30b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501132492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1501132492
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3904864788
Short name T589
Test name
Test status
Simulation time 2898875972 ps
CPU time 27.89 seconds
Started Aug 16 05:52:19 PM PDT 24
Finished Aug 16 05:52:47 PM PDT 24
Peak memory 233644 kb
Host smart-cf1411af-2de6-410c-98d3-f54b0ca29e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904864788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3904864788
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.77341543
Short name T452
Test name
Test status
Simulation time 75958923 ps
CPU time 2.29 seconds
Started Aug 16 05:52:18 PM PDT 24
Finished Aug 16 05:52:20 PM PDT 24
Peak memory 223848 kb
Host smart-1ff9b901-8460-4145-a2cf-2d80d81fab02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77341543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.77341543
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1267231681
Short name T639
Test name
Test status
Simulation time 1724797633 ps
CPU time 5.47 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 233440 kb
Host smart-9e4d8aef-691c-4547-9d2b-44819b93557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267231681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1267231681
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.361969295
Short name T840
Test name
Test status
Simulation time 1340570200 ps
CPU time 4.27 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 220128 kb
Host smart-700d920e-1f7d-4133-b940-fdb8d8bba6b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=361969295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.361969295
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.67550777
Short name T544
Test name
Test status
Simulation time 74785792136 ps
CPU time 153.25 seconds
Started Aug 16 05:52:18 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 253268 kb
Host smart-5de31241-2e20-4388-b403-90045b3053a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67550777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress
_all.67550777
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3296262095
Short name T728
Test name
Test status
Simulation time 789627560 ps
CPU time 2.71 seconds
Started Aug 16 05:51:53 PM PDT 24
Finished Aug 16 05:51:56 PM PDT 24
Peak memory 217132 kb
Host smart-81e20f06-bffe-4e6d-beb7-0813f2bce4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296262095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3296262095
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2390805368
Short name T462
Test name
Test status
Simulation time 20587983 ps
CPU time 0.92 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 207596 kb
Host smart-d893112e-0b71-449e-a44e-ebb46c5b3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390805368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2390805368
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3731930455
Short name T456
Test name
Test status
Simulation time 144993343 ps
CPU time 0.93 seconds
Started Aug 16 05:52:31 PM PDT 24
Finished Aug 16 05:52:32 PM PDT 24
Peak memory 206852 kb
Host smart-6cc96bd2-73a3-4d55-bad6-ab84f9a86db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731930455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3731930455
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2507248314
Short name T494
Test name
Test status
Simulation time 5874645519 ps
CPU time 20.5 seconds
Started Aug 16 05:51:55 PM PDT 24
Finished Aug 16 05:52:15 PM PDT 24
Peak memory 225516 kb
Host smart-f9e089fc-5273-4721-bbc1-c1ec1a250b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507248314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2507248314
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2529317413
Short name T405
Test name
Test status
Simulation time 32407697 ps
CPU time 0.74 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 206244 kb
Host smart-6c6bfd12-2191-4066-b8bf-93de7286ae16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529317413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2529317413
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3610644228
Short name T443
Test name
Test status
Simulation time 31302569 ps
CPU time 2.62 seconds
Started Aug 16 05:51:50 PM PDT 24
Finished Aug 16 05:51:53 PM PDT 24
Peak memory 233224 kb
Host smart-ea0e67ec-e68e-4eb8-a4a3-8d0fe7418ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610644228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3610644228
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3312043161
Short name T386
Test name
Test status
Simulation time 35967101 ps
CPU time 0.75 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:52:18 PM PDT 24
Peak memory 206388 kb
Host smart-f17f13e3-8d7e-4caa-b64b-621052b0c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312043161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3312043161
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3956476396
Short name T549
Test name
Test status
Simulation time 1402952029 ps
CPU time 5.15 seconds
Started Aug 16 05:53:05 PM PDT 24
Finished Aug 16 05:53:10 PM PDT 24
Peak memory 225348 kb
Host smart-3ddb0d87-a19c-4ac0-844d-3e9c34c65ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956476396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3956476396
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2631062133
Short name T601
Test name
Test status
Simulation time 534783340222 ps
CPU time 230.33 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 252220 kb
Host smart-203c85a3-5d2e-4d15-b02a-d384215bee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631062133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2631062133
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3009783007
Short name T141
Test name
Test status
Simulation time 877392506 ps
CPU time 11.55 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:52:28 PM PDT 24
Peak memory 225336 kb
Host smart-dbcfcc64-ef3b-4fc8-b39c-360af968d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009783007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3009783007
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1252496845
Short name T926
Test name
Test status
Simulation time 65043649388 ps
CPU time 231.22 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 253032 kb
Host smart-db1ffbdb-ea13-4c52-a8e7-40d8c326b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252496845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1252496845
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4364794
Short name T691
Test name
Test status
Simulation time 195918137 ps
CPU time 3.53 seconds
Started Aug 16 05:52:17 PM PDT 24
Finished Aug 16 05:52:21 PM PDT 24
Peak memory 233580 kb
Host smart-caf4cd36-d86e-4d40-8e45-8bfdda9168aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4364794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4364794
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1295031811
Short name T837
Test name
Test status
Simulation time 933746587 ps
CPU time 15.62 seconds
Started Aug 16 05:52:18 PM PDT 24
Finished Aug 16 05:52:34 PM PDT 24
Peak memory 225156 kb
Host smart-468b3c45-d239-46c5-84b5-46ad59b4f893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295031811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1295031811
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.592794549
Short name T242
Test name
Test status
Simulation time 467127658 ps
CPU time 4.35 seconds
Started Aug 16 05:51:52 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 225280 kb
Host smart-c61303a2-86da-4fa4-9482-2fa4765277e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592794549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.592794549
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2934897193
Short name T478
Test name
Test status
Simulation time 9508551186 ps
CPU time 9.43 seconds
Started Aug 16 05:52:19 PM PDT 24
Finished Aug 16 05:52:29 PM PDT 24
Peak memory 225544 kb
Host smart-9a75eab0-7460-43ca-82e5-6632d343ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934897193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2934897193
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3948343152
Short name T903
Test name
Test status
Simulation time 1849230094 ps
CPU time 5.12 seconds
Started Aug 16 05:52:48 PM PDT 24
Finished Aug 16 05:52:54 PM PDT 24
Peak memory 222660 kb
Host smart-8fe8c9ff-572f-48f4-817d-f2ba1f7a66fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3948343152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3948343152
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3848341841
Short name T43
Test name
Test status
Simulation time 368719327228 ps
CPU time 846.39 seconds
Started Aug 16 05:52:16 PM PDT 24
Finished Aug 16 06:06:23 PM PDT 24
Peak memory 266576 kb
Host smart-b4b284fc-d9f3-4da8-823c-048758b9b9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848341841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3848341841
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.875362369
Short name T755
Test name
Test status
Simulation time 6156831217 ps
CPU time 38.38 seconds
Started Aug 16 05:51:54 PM PDT 24
Finished Aug 16 05:52:33 PM PDT 24
Peak memory 217332 kb
Host smart-93a67142-1f4f-4831-ab34-c582e8be3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875362369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.875362369
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4283515687
Short name T739
Test name
Test status
Simulation time 2979593736 ps
CPU time 7.12 seconds
Started Aug 16 05:52:14 PM PDT 24
Finished Aug 16 05:52:21 PM PDT 24
Peak memory 217192 kb
Host smart-be4bf924-850f-4b47-b899-c25afc48790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283515687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4283515687
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4094696220
Short name T750
Test name
Test status
Simulation time 1576958646 ps
CPU time 1.68 seconds
Started Aug 16 05:52:22 PM PDT 24
Finished Aug 16 05:52:24 PM PDT 24
Peak memory 217132 kb
Host smart-9b28a261-7469-4098-af0c-8d6f40a5c7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094696220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4094696220
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.915359531
Short name T484
Test name
Test status
Simulation time 30270019 ps
CPU time 0.75 seconds
Started Aug 16 05:51:51 PM PDT 24
Finished Aug 16 05:51:52 PM PDT 24
Peak memory 206860 kb
Host smart-b9df4216-9ce7-4fed-8dab-ce8836ba8321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915359531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.915359531
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3172804555
Short name T742
Test name
Test status
Simulation time 22655611181 ps
CPU time 11.72 seconds
Started Aug 16 05:51:50 PM PDT 24
Finished Aug 16 05:52:02 PM PDT 24
Peak memory 233700 kb
Host smart-21f2d28b-3e71-427a-8f76-ba2db6118b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172804555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3172804555
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1186158105
Short name T341
Test name
Test status
Simulation time 79365630 ps
CPU time 0.7 seconds
Started Aug 16 05:50:07 PM PDT 24
Finished Aug 16 05:50:08 PM PDT 24
Peak memory 205716 kb
Host smart-f75cf221-6ff5-4f53-8edd-1b8b0f21ba6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186158105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
186158105
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1795263270
Short name T732
Test name
Test status
Simulation time 63538570 ps
CPU time 3.04 seconds
Started Aug 16 05:49:50 PM PDT 24
Finished Aug 16 05:49:53 PM PDT 24
Peak memory 233560 kb
Host smart-1616de22-1873-4626-a69d-453672ea8429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795263270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1795263270
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1077773525
Short name T418
Test name
Test status
Simulation time 55512158 ps
CPU time 0.78 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:49:53 PM PDT 24
Peak memory 207664 kb
Host smart-cd18cc20-378c-432e-8d03-9071b5671228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077773525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1077773525
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.201606593
Short name T159
Test name
Test status
Simulation time 18625918155 ps
CPU time 33.03 seconds
Started Aug 16 05:49:44 PM PDT 24
Finished Aug 16 05:50:17 PM PDT 24
Peak memory 241868 kb
Host smart-ce257d3d-5072-466e-98d5-1aa7f4110004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201606593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.201606593
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1468342147
Short name T232
Test name
Test status
Simulation time 7526959100 ps
CPU time 105.71 seconds
Started Aug 16 05:50:21 PM PDT 24
Finished Aug 16 05:52:07 PM PDT 24
Peak memory 251328 kb
Host smart-0b406c04-94c3-47b0-a1fc-720d8f35933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468342147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1468342147
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1257760140
Short name T218
Test name
Test status
Simulation time 243160632121 ps
CPU time 350.06 seconds
Started Aug 16 05:50:31 PM PDT 24
Finished Aug 16 05:56:22 PM PDT 24
Peak memory 256028 kb
Host smart-192d5120-a160-42f8-b122-5d1725c56af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257760140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1257760140
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1484519397
Short name T938
Test name
Test status
Simulation time 1634359564 ps
CPU time 28.12 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 233516 kb
Host smart-9c1ddd2e-c79c-48be-b5ca-869ef7edb8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484519397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1484519397
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1396339079
Short name T864
Test name
Test status
Simulation time 13692427320 ps
CPU time 76.88 seconds
Started Aug 16 05:50:37 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 265972 kb
Host smart-20fa261b-4bca-4357-adec-8a17c9c8382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396339079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1396339079
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3927305565
Short name T778
Test name
Test status
Simulation time 80606763 ps
CPU time 2.1 seconds
Started Aug 16 05:49:51 PM PDT 24
Finished Aug 16 05:49:54 PM PDT 24
Peak memory 224632 kb
Host smart-b4846fc2-1e94-4eb8-9160-eac8b790bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927305565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3927305565
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1409449762
Short name T224
Test name
Test status
Simulation time 353669893 ps
CPU time 8.87 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:17 PM PDT 24
Peak memory 240032 kb
Host smart-da6593c9-bde4-4a74-9f4f-208a1c8d84eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409449762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1409449762
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2612092092
Short name T216
Test name
Test status
Simulation time 11878782802 ps
CPU time 43.09 seconds
Started Aug 16 05:50:08 PM PDT 24
Finished Aug 16 05:50:51 PM PDT 24
Peak memory 258296 kb
Host smart-6a190b8d-f11c-4d74-b835-01d23140aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612092092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2612092092
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1767783711
Short name T400
Test name
Test status
Simulation time 206233338 ps
CPU time 2.56 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:12 PM PDT 24
Peak memory 224960 kb
Host smart-5a9d0341-38a8-4224-babb-3345b32557e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767783711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1767783711
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3158138510
Short name T993
Test name
Test status
Simulation time 158488123 ps
CPU time 3.42 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 220800 kb
Host smart-cf35053a-99c5-4bae-ba6e-87eed4ed1d65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3158138510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3158138510
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3782153337
Short name T510
Test name
Test status
Simulation time 35787355 ps
CPU time 0.99 seconds
Started Aug 16 05:49:43 PM PDT 24
Finished Aug 16 05:49:44 PM PDT 24
Peak memory 207724 kb
Host smart-8f2961bf-452a-483d-a02b-4c44ae7b01d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782153337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3782153337
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2700353834
Short name T714
Test name
Test status
Simulation time 71441920 ps
CPU time 0.74 seconds
Started Aug 16 05:49:44 PM PDT 24
Finished Aug 16 05:49:45 PM PDT 24
Peak memory 206508 kb
Host smart-36d7aa34-7463-4dea-9883-188470f10c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700353834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2700353834
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3008993837
Short name T941
Test name
Test status
Simulation time 7263125242 ps
CPU time 4.77 seconds
Started Aug 16 05:49:43 PM PDT 24
Finished Aug 16 05:49:48 PM PDT 24
Peak memory 218256 kb
Host smart-1e9acddf-50bf-4f27-967b-223bb763593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008993837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3008993837
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3116716516
Short name T814
Test name
Test status
Simulation time 184182858 ps
CPU time 2.06 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:32 PM PDT 24
Peak memory 217044 kb
Host smart-5aa5f3a5-55ee-4836-875c-fc730c1ea110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116716516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3116716516
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3223873813
Short name T384
Test name
Test status
Simulation time 57435472 ps
CPU time 0.71 seconds
Started Aug 16 05:50:30 PM PDT 24
Finished Aug 16 05:50:31 PM PDT 24
Peak memory 206808 kb
Host smart-37778a44-4e92-4cdf-8609-343defe5fe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223873813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3223873813
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1681567904
Short name T607
Test name
Test status
Simulation time 5677737682 ps
CPU time 22.03 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:50:08 PM PDT 24
Peak memory 236644 kb
Host smart-e1c957c3-9129-4fa0-97b4-ff1dabdea2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681567904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1681567904
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1227203378
Short name T339
Test name
Test status
Simulation time 35856106 ps
CPU time 0.71 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:49:53 PM PDT 24
Peak memory 205676 kb
Host smart-63c01d4f-bae0-4031-982c-820cf0b7ccb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227203378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
227203378
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1768856317
Short name T399
Test name
Test status
Simulation time 78271529 ps
CPU time 2.17 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:01 PM PDT 24
Peak memory 224584 kb
Host smart-24f0fe34-976e-4bc9-aaa0-838d52a611cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768856317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1768856317
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3869569432
Short name T788
Test name
Test status
Simulation time 21379999 ps
CPU time 0.76 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:49:46 PM PDT 24
Peak memory 207384 kb
Host smart-02dff8cf-26cc-49d1-9da6-76107b42e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869569432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3869569432
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.571296705
Short name T211
Test name
Test status
Simulation time 54735191028 ps
CPU time 87.16 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:52:41 PM PDT 24
Peak memory 238344 kb
Host smart-9824247b-ef42-4fc4-85d2-0f74a2671a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571296705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.571296705
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3709377535
Short name T182
Test name
Test status
Simulation time 86261850484 ps
CPU time 407.5 seconds
Started Aug 16 05:49:54 PM PDT 24
Finished Aug 16 05:56:41 PM PDT 24
Peak memory 272940 kb
Host smart-c05034c2-1eb3-48b1-9790-7b4a432bd9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709377535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3709377535
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.592549830
Short name T207
Test name
Test status
Simulation time 10465864227 ps
CPU time 33.99 seconds
Started Aug 16 05:49:55 PM PDT 24
Finished Aug 16 05:50:29 PM PDT 24
Peak memory 233796 kb
Host smart-d7bde8bb-07de-4bec-96d4-5743dab9b836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592549830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
592549830
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2728088577
Short name T737
Test name
Test status
Simulation time 876731550 ps
CPU time 16.9 seconds
Started Aug 16 05:49:54 PM PDT 24
Finished Aug 16 05:50:11 PM PDT 24
Peak memory 225512 kb
Host smart-9fd957f4-ee45-4760-86a5-8265177b0154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728088577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2728088577
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1284515963
Short name T972
Test name
Test status
Simulation time 25000047228 ps
CPU time 170.05 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:52:36 PM PDT 24
Peak memory 240580 kb
Host smart-6ccbf90b-d9ec-476b-9162-dcddb8c3ddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284515963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1284515963
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1714005856
Short name T890
Test name
Test status
Simulation time 6945679651 ps
CPU time 15.77 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:50:01 PM PDT 24
Peak memory 225552 kb
Host smart-6dd3a4c2-3765-4a58-bea2-33c8c0811eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714005856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1714005856
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2052993138
Short name T453
Test name
Test status
Simulation time 539591071 ps
CPU time 2.99 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:49:48 PM PDT 24
Peak memory 225532 kb
Host smart-9b1b36f9-b704-4489-8b57-6ca9493c0173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052993138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2052993138
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2935502400
Short name T390
Test name
Test status
Simulation time 3482174232 ps
CPU time 7.57 seconds
Started Aug 16 05:50:04 PM PDT 24
Finished Aug 16 05:50:11 PM PDT 24
Peak memory 233672 kb
Host smart-fba453b9-84d7-4481-b96e-9e6649523552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935502400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2935502400
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1370106846
Short name T378
Test name
Test status
Simulation time 1110646735 ps
CPU time 2.99 seconds
Started Aug 16 05:49:43 PM PDT 24
Finished Aug 16 05:49:46 PM PDT 24
Peak memory 233584 kb
Host smart-9da6f6b1-23e4-4436-bb57-efac920798fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370106846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1370106846
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2797923641
Short name T566
Test name
Test status
Simulation time 935513836 ps
CPU time 13.8 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 219920 kb
Host smart-90f9fbf0-0fd8-4037-ab08-3fe6b06e7338
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2797923641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2797923641
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.338329449
Short name T307
Test name
Test status
Simulation time 40227982823 ps
CPU time 355.7 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:57:25 PM PDT 24
Peak memory 268228 kb
Host smart-2080fb08-74a7-4c5a-89ab-6d7f2f94ef63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338329449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.338329449
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1572564328
Short name T898
Test name
Test status
Simulation time 75261728 ps
CPU time 0.73 seconds
Started Aug 16 05:49:44 PM PDT 24
Finished Aug 16 05:49:45 PM PDT 24
Peak memory 206524 kb
Host smart-67b61529-52fd-4b6e-bb29-14690e80cfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572564328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1572564328
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.600062588
Short name T782
Test name
Test status
Simulation time 19656298290 ps
CPU time 14.61 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:23 PM PDT 24
Peak memory 215528 kb
Host smart-7e13fa5a-b314-4e6c-b2fe-50d3d8c4675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600062588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.600062588
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.150811304
Short name T598
Test name
Test status
Simulation time 70465823 ps
CPU time 1.29 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 217220 kb
Host smart-a852c80e-1fd7-42e5-bb4c-2cb1e4bed4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150811304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.150811304
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1949394992
Short name T616
Test name
Test status
Simulation time 70725477 ps
CPU time 0.93 seconds
Started Aug 16 05:50:03 PM PDT 24
Finished Aug 16 05:50:04 PM PDT 24
Peak memory 206832 kb
Host smart-fe26f95c-e0c5-4c3e-8971-28f0047e9662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949394992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1949394992
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2819937794
Short name T15
Test name
Test status
Simulation time 1269563342 ps
CPU time 6.36 seconds
Started Aug 16 05:49:57 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 233600 kb
Host smart-4b14034f-d48c-43fd-8d7b-653bdbe5a47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819937794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2819937794
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4188151270
Short name T397
Test name
Test status
Simulation time 13774213 ps
CPU time 0.75 seconds
Started Aug 16 05:49:48 PM PDT 24
Finished Aug 16 05:49:49 PM PDT 24
Peak memory 206596 kb
Host smart-3661390c-43a7-4a6c-9edb-a201ce839155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188151270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
188151270
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1804534283
Short name T527
Test name
Test status
Simulation time 80368110 ps
CPU time 3.09 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:05 PM PDT 24
Peak memory 233576 kb
Host smart-048207c1-7b50-4c38-b8d1-81ea9182dcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804534283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1804534283
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1012799873
Short name T429
Test name
Test status
Simulation time 40140569 ps
CPU time 0.79 seconds
Started Aug 16 05:49:45 PM PDT 24
Finished Aug 16 05:49:45 PM PDT 24
Peak memory 207560 kb
Host smart-a60c7680-c47f-4de4-a98b-558147f669f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012799873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1012799873
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3585317200
Short name T908
Test name
Test status
Simulation time 16649957680 ps
CPU time 97.87 seconds
Started Aug 16 05:50:03 PM PDT 24
Finished Aug 16 05:51:41 PM PDT 24
Peak memory 272992 kb
Host smart-f8cf4209-cd7e-436e-a10d-2b819244a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585317200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3585317200
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3946539794
Short name T501
Test name
Test status
Simulation time 160796949203 ps
CPU time 301.67 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:56:15 PM PDT 24
Peak memory 270584 kb
Host smart-2f09b956-badc-4cd3-8d10-e62344a785e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946539794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3946539794
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2673683802
Short name T381
Test name
Test status
Simulation time 276701248 ps
CPU time 4.56 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:07 PM PDT 24
Peak memory 233612 kb
Host smart-92235aad-b9ba-4032-889b-3c579fbde980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673683802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2673683802
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2007651296
Short name T576
Test name
Test status
Simulation time 3389177393 ps
CPU time 34.23 seconds
Started Aug 16 05:50:13 PM PDT 24
Finished Aug 16 05:50:47 PM PDT 24
Peak memory 249960 kb
Host smart-4e3691ba-a151-4e53-ba18-ff7f91ea98f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007651296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2007651296
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4028503901
Short name T879
Test name
Test status
Simulation time 460296817 ps
CPU time 2.59 seconds
Started Aug 16 05:49:49 PM PDT 24
Finished Aug 16 05:49:52 PM PDT 24
Peak memory 225404 kb
Host smart-be2c2926-7d01-4681-8649-42e62d2abaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028503901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4028503901
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.340936010
Short name T481
Test name
Test status
Simulation time 2036804608 ps
CPU time 19.1 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:21 PM PDT 24
Peak memory 240624 kb
Host smart-4aebc963-ed86-494b-a512-05d096e3ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340936010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.340936010
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.265358186
Short name T238
Test name
Test status
Simulation time 49324789637 ps
CPU time 33.5 seconds
Started Aug 16 05:50:31 PM PDT 24
Finished Aug 16 05:51:05 PM PDT 24
Peak memory 249968 kb
Host smart-a89d1172-11f0-4f67-a909-dbc215b682e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265358186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
265358186
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3990257331
Short name T154
Test name
Test status
Simulation time 53764866502 ps
CPU time 30.5 seconds
Started Aug 16 05:49:51 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 250096 kb
Host smart-8832942f-e362-43b7-a6f1-4afe079bbcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990257331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3990257331
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1810476842
Short name T500
Test name
Test status
Simulation time 1569373291 ps
CPU time 13.94 seconds
Started Aug 16 05:50:28 PM PDT 24
Finished Aug 16 05:50:42 PM PDT 24
Peak memory 223888 kb
Host smart-c80e35e1-fde2-4230-8972-4dbb5a724061
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1810476842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1810476842
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2289780301
Short name T233
Test name
Test status
Simulation time 42320834452 ps
CPU time 438.85 seconds
Started Aug 16 05:49:52 PM PDT 24
Finished Aug 16 05:57:11 PM PDT 24
Peak memory 274452 kb
Host smart-72f50ff2-aaf1-4408-89a4-ac6a9f64920a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289780301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2289780301
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2443129437
Short name T983
Test name
Test status
Simulation time 1719052043 ps
CPU time 18.01 seconds
Started Aug 16 05:50:03 PM PDT 24
Finished Aug 16 05:50:21 PM PDT 24
Peak memory 219688 kb
Host smart-cdeb8d51-8317-4db0-9d31-75862f021a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443129437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2443129437
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.844624781
Short name T388
Test name
Test status
Simulation time 21417263211 ps
CPU time 10.8 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:10 PM PDT 24
Peak memory 217336 kb
Host smart-e729cb2d-d762-4050-be8d-e70ca74bd7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844624781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.844624781
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2434498632
Short name T666
Test name
Test status
Simulation time 171458966 ps
CPU time 1.78 seconds
Started Aug 16 05:49:48 PM PDT 24
Finished Aug 16 05:49:50 PM PDT 24
Peak memory 217124 kb
Host smart-97d1e4cf-88dc-4ddc-8e06-c33d32327b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434498632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2434498632
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1645809503
Short name T353
Test name
Test status
Simulation time 87299941 ps
CPU time 0.71 seconds
Started Aug 16 05:51:56 PM PDT 24
Finished Aug 16 05:51:57 PM PDT 24
Peak memory 206696 kb
Host smart-ecce0803-0078-4ef2-a6cc-0face5c6868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645809503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1645809503
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1725395160
Short name T329
Test name
Test status
Simulation time 13093561 ps
CPU time 0.75 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:49:59 PM PDT 24
Peak memory 205680 kb
Host smart-54106a0f-6148-4751-bbbc-8e77e13bc435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725395160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
725395160
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3589728250
Short name T96
Test name
Test status
Simulation time 66862131 ps
CPU time 3.27 seconds
Started Aug 16 05:49:46 PM PDT 24
Finished Aug 16 05:49:50 PM PDT 24
Peak memory 233520 kb
Host smart-97b35666-1724-4157-a4b4-41a48394473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589728250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3589728250
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3126306716
Short name T480
Test name
Test status
Simulation time 55688930 ps
CPU time 0.94 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:14 PM PDT 24
Peak memory 205584 kb
Host smart-fa0fb5a6-6385-4947-8c86-5bcd943cae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126306716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3126306716
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1056852829
Short name T793
Test name
Test status
Simulation time 2280746954 ps
CPU time 53.99 seconds
Started Aug 16 05:50:27 PM PDT 24
Finished Aug 16 05:51:21 PM PDT 24
Peak memory 253856 kb
Host smart-8b78f510-c055-4afb-b2e5-25817449ba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056852829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1056852829
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.595516847
Short name T849
Test name
Test status
Simulation time 6466018678 ps
CPU time 45.72 seconds
Started Aug 16 05:51:08 PM PDT 24
Finished Aug 16 05:51:54 PM PDT 24
Peak memory 240560 kb
Host smart-50b5ee0d-68ad-49f8-91f7-95dfb3f42f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595516847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.595516847
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3351212235
Short name T274
Test name
Test status
Simulation time 64539724698 ps
CPU time 140.64 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:52:19 PM PDT 24
Peak memory 265424 kb
Host smart-a53c370b-4ca0-43e9-abc0-049a879ea5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351212235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3351212235
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2992642810
Short name T827
Test name
Test status
Simulation time 16232495813 ps
CPU time 59.7 seconds
Started Aug 16 05:50:37 PM PDT 24
Finished Aug 16 05:51:36 PM PDT 24
Peak memory 233664 kb
Host smart-a0c0e37d-0adb-431d-b320-e12e80a9871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992642810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2992642810
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.967031009
Short name T753
Test name
Test status
Simulation time 1037293347 ps
CPU time 9.28 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:50:08 PM PDT 24
Peak memory 225376 kb
Host smart-206b6693-2116-4823-a808-a711b5a8ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967031009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.967031009
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.477315799
Short name T373
Test name
Test status
Simulation time 639535976 ps
CPU time 7.95 seconds
Started Aug 16 05:51:37 PM PDT 24
Finished Aug 16 05:51:45 PM PDT 24
Peak memory 233320 kb
Host smart-27411758-f729-431c-b013-bd74bb1e210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477315799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.477315799
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4201303809
Short name T245
Test name
Test status
Simulation time 333352988 ps
CPU time 3.77 seconds
Started Aug 16 05:51:34 PM PDT 24
Finished Aug 16 05:51:38 PM PDT 24
Peak memory 225184 kb
Host smart-dd54e5cd-c6dd-48d7-93b4-61371df16f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201303809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4201303809
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2494132829
Short name T432
Test name
Test status
Simulation time 10288705521 ps
CPU time 12.8 seconds
Started Aug 16 05:51:13 PM PDT 24
Finished Aug 16 05:51:26 PM PDT 24
Peak memory 239756 kb
Host smart-5582ce8f-73a1-47da-a6ad-92a37bdaa489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494132829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2494132829
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.738610788
Short name T320
Test name
Test status
Simulation time 428987594 ps
CPU time 4.32 seconds
Started Aug 16 05:49:55 PM PDT 24
Finished Aug 16 05:49:59 PM PDT 24
Peak memory 223432 kb
Host smart-1d092892-953c-47a4-a112-16dbdaf960e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738610788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.738610788
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3289366305
Short name T724
Test name
Test status
Simulation time 9479014798 ps
CPU time 32.44 seconds
Started Aug 16 05:49:59 PM PDT 24
Finished Aug 16 05:50:31 PM PDT 24
Peak memory 250240 kb
Host smart-6c01219c-181d-4d8a-8186-939b25c46f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289366305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3289366305
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.280252958
Short name T296
Test name
Test status
Simulation time 2456506351 ps
CPU time 15.74 seconds
Started Aug 16 05:50:28 PM PDT 24
Finished Aug 16 05:50:44 PM PDT 24
Peak memory 217344 kb
Host smart-a42a07c3-e4ea-4b46-82ff-970e1518cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280252958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.280252958
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.489545856
Short name T565
Test name
Test status
Simulation time 5101851621 ps
CPU time 7.62 seconds
Started Aug 16 05:49:54 PM PDT 24
Finished Aug 16 05:50:01 PM PDT 24
Peak memory 217336 kb
Host smart-eb70f539-6b90-4e95-98fc-861d5647d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489545856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.489545856
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1077376376
Short name T838
Test name
Test status
Simulation time 27223996 ps
CPU time 1.03 seconds
Started Aug 16 05:49:46 PM PDT 24
Finished Aug 16 05:49:47 PM PDT 24
Peak memory 208508 kb
Host smart-9b30c353-01c1-4098-a521-a15ba2f55c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077376376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1077376376
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.926467902
Short name T604
Test name
Test status
Simulation time 55260389 ps
CPU time 0.72 seconds
Started Aug 16 05:50:23 PM PDT 24
Finished Aug 16 05:50:24 PM PDT 24
Peak memory 206788 kb
Host smart-d3798e31-7c0d-4535-98bc-f781844abbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926467902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.926467902
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3469514668
Short name T847
Test name
Test status
Simulation time 50674922893 ps
CPU time 21.01 seconds
Started Aug 16 05:49:46 PM PDT 24
Finished Aug 16 05:50:07 PM PDT 24
Peak memory 233712 kb
Host smart-9d94a672-336d-48a7-828c-f892a9cec112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469514668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3469514668
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1184692253
Short name T371
Test name
Test status
Simulation time 21174592 ps
CPU time 0.74 seconds
Started Aug 16 05:51:09 PM PDT 24
Finished Aug 16 05:51:10 PM PDT 24
Peak memory 205328 kb
Host smart-b8e04423-c080-4caa-b84e-57748cb1e4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184692253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
184692253
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3977851920
Short name T252
Test name
Test status
Simulation time 190433516 ps
CPU time 3.74 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:05 PM PDT 24
Peak memory 225324 kb
Host smart-298c54fe-9b78-4ff0-b2f3-b646137a0eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977851920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3977851920
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.192066413
Short name T436
Test name
Test status
Simulation time 98720039 ps
CPU time 0.81 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:03 PM PDT 24
Peak memory 207308 kb
Host smart-3c2d372d-c69d-4a22-9482-3e123351f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192066413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.192066413
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.933683203
Short name T940
Test name
Test status
Simulation time 22433129119 ps
CPU time 114.02 seconds
Started Aug 16 05:50:28 PM PDT 24
Finished Aug 16 05:52:22 PM PDT 24
Peak memory 251196 kb
Host smart-1543921a-a0f4-4306-81dc-8dccdf653dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933683203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.933683203
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.18563236
Short name T787
Test name
Test status
Simulation time 17803750308 ps
CPU time 115.5 seconds
Started Aug 16 05:50:05 PM PDT 24
Finished Aug 16 05:52:00 PM PDT 24
Peak memory 241232 kb
Host smart-2f476cd3-f800-4afc-ae37-5b8aaea71d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18563236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.18563236
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2360071149
Short name T135
Test name
Test status
Simulation time 15897477700 ps
CPU time 123.24 seconds
Started Aug 16 05:51:33 PM PDT 24
Finished Aug 16 05:53:36 PM PDT 24
Peak memory 271828 kb
Host smart-c4d8fc51-91d2-4500-bfa2-5d32f3835b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360071149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2360071149
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.312145695
Short name T286
Test name
Test status
Simulation time 7229199054 ps
CPU time 28.37 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 250120 kb
Host smart-448f21b3-9184-418a-9fb1-595bcddb5fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312145695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.312145695
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3325132332
Short name T65
Test name
Test status
Simulation time 13072659993 ps
CPU time 42.71 seconds
Started Aug 16 05:49:57 PM PDT 24
Finished Aug 16 05:50:40 PM PDT 24
Peak memory 233632 kb
Host smart-a90c804f-9f69-459e-be1f-f9441921da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325132332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3325132332
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.520210054
Short name T930
Test name
Test status
Simulation time 1108078137 ps
CPU time 8.04 seconds
Started Aug 16 05:49:58 PM PDT 24
Finished Aug 16 05:50:06 PM PDT 24
Peak memory 233596 kb
Host smart-282a8eb3-0c53-4e79-b55f-89bd6fa120b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520210054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.520210054
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1861576034
Short name T498
Test name
Test status
Simulation time 191185911 ps
CPU time 3.51 seconds
Started Aug 16 05:51:29 PM PDT 24
Finished Aug 16 05:51:35 PM PDT 24
Peak memory 225244 kb
Host smart-01de5fc5-b007-459f-b017-c2a856f0f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861576034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1861576034
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3144829830
Short name T865
Test name
Test status
Simulation time 16943226342 ps
CPU time 25.17 seconds
Started Aug 16 05:50:02 PM PDT 24
Finished Aug 16 05:50:27 PM PDT 24
Peak memory 233700 kb
Host smart-61abe33f-01de-4167-9b77-0f540cfaf364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144829830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3144829830
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4212152514
Short name T493
Test name
Test status
Simulation time 319380551 ps
CPU time 2.94 seconds
Started Aug 16 05:51:36 PM PDT 24
Finished Aug 16 05:51:39 PM PDT 24
Peak memory 233428 kb
Host smart-043e8cec-5f3a-401b-ab90-ae61debc903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212152514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4212152514
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1187347925
Short name T902
Test name
Test status
Simulation time 772468025 ps
CPU time 5.45 seconds
Started Aug 16 05:50:28 PM PDT 24
Finished Aug 16 05:50:34 PM PDT 24
Peak memory 220208 kb
Host smart-ce328fa2-689f-41d0-8be5-7722f53f6219
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1187347925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1187347925
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1163132480
Short name T136
Test name
Test status
Simulation time 119235830814 ps
CPU time 253.73 seconds
Started Aug 16 05:50:22 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 258596 kb
Host smart-59920519-f6f7-4757-8013-da7d0b28e9e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163132480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1163132480
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1706746638
Short name T27
Test name
Test status
Simulation time 36959394594 ps
CPU time 31.68 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:33 PM PDT 24
Peak memory 217244 kb
Host smart-f4f05cd5-198c-4c59-929d-42cf4b71f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706746638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1706746638
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3200113600
Short name T872
Test name
Test status
Simulation time 21920097491 ps
CPU time 16.43 seconds
Started Aug 16 05:49:57 PM PDT 24
Finished Aug 16 05:50:13 PM PDT 24
Peak memory 217264 kb
Host smart-154316bf-03a2-47ed-88ba-b5420f5c92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200113600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3200113600
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2509390335
Short name T825
Test name
Test status
Simulation time 1010090781 ps
CPU time 1.33 seconds
Started Aug 16 05:50:29 PM PDT 24
Finished Aug 16 05:50:30 PM PDT 24
Peak memory 215924 kb
Host smart-4dc22b0e-0363-4290-8fe5-4a239e4bb0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509390335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2509390335
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4283189928
Short name T721
Test name
Test status
Simulation time 37329675 ps
CPU time 0.79 seconds
Started Aug 16 05:51:28 PM PDT 24
Finished Aug 16 05:51:29 PM PDT 24
Peak memory 206676 kb
Host smart-aa8854cf-40c9-43bd-bc74-94fe92e3a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283189928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4283189928
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3415653829
Short name T647
Test name
Test status
Simulation time 672048057 ps
CPU time 5.76 seconds
Started Aug 16 05:50:01 PM PDT 24
Finished Aug 16 05:50:07 PM PDT 24
Peak memory 233512 kb
Host smart-ee49c0f2-8608-405a-930f-6d21fc5afc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415653829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3415653829
Directory /workspace/9.spi_device_upload/latest
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