Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2149704	1			T1	374		T3	2489		T5	7880
all_values[1]	2149704	1			T1	374		T3	2489		T5	7880
all_values[2]	2149704	1			T1	374		T3	2489		T5	7880
all_values[3]	2149704	1			T1	374		T3	2489		T5	7880
all_values[4]	2149704	1			T1	374		T3	2489		T5	7880
all_values[5]	2149704	1			T1	374		T3	2489		T5	7880
all_values[6]	2149704	1			T1	374		T3	2489		T5	7880
all_values[7]	2149704	1			T1	374		T3	2489		T5	7880

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16529277

1

T1

2992

T3

19912

T5

63040

auto[1]

668355

1

T18

67

T19

51032

T68

4807

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17175358

1

T1

2992

T3

19912

T5

63040

auto[1]

22274

1

T16

3

T29

33

T18

55

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2078963	1			T1	374		T3	2489		T5	7880
all_values[0]	auto[0]	auto[1]	10307	1			T16	3		T29	28		T18	4
all_values[0]	auto[1]	auto[0]	60100	1			T18	6		T68	2389		T21	5
all_values[0]	auto[1]	auto[1]	334	1			T18	2		T19	3		T68	2
all_values[1]	auto[0]	auto[0]	2006411	1			T1	374		T3	2489		T5	7880
all_values[1]	auto[0]	auto[1]	6253	1			T29	5		T18	3		T31	64
all_values[1]	auto[1]	auto[0]	136346	1			T18	1		T19	12620		T68	3
all_values[1]	auto[1]	auto[1]	694	1			T18	4		T19	134		T68	3
all_values[2]	auto[0]	auto[0]	2047514	1			T1	374		T3	2489		T5	7880
all_values[2]	auto[0]	auto[1]	2379	1			T18	1		T32	5		T47	52
all_values[2]	auto[1]	auto[0]	99459	1			T18	4		T19	12702		T68	5
all_values[2]	auto[1]	auto[1]	352	1			T18	5		T19	51		T21	2
all_values[3]	auto[0]	auto[0]	2066923	1			T1	374		T3	2489		T5	7880
all_values[3]	auto[0]	auto[1]	230	1			T18	7		T19	2		T68	4
all_values[3]	auto[1]	auto[0]	82350	1			T18	4		T19	3		T68	1
all_values[3]	auto[1]	auto[1]	201	1			T18	3		T19	1		T68	1
all_values[4]	auto[0]	auto[0]	2074856	1			T1	374		T3	2489		T5	7880
all_values[4]	auto[0]	auto[1]	196	1			T18	2		T19	1		T21	2
all_values[4]	auto[1]	auto[0]	74447	1			T18	8		T19	12749		T68	6
all_values[4]	auto[1]	auto[1]	205	1			T18	4		T19	4		T21	1
all_values[5]	auto[0]	auto[0]	2023536	1			T1	374		T3	2489		T5	7880
all_values[5]	auto[0]	auto[1]	178	1			T18	6		T19	2		T68	2
all_values[5]	auto[1]	auto[0]	125813	1			T18	5		T19	12752		T68	2389
all_values[5]	auto[1]	auto[1]	177	1			T18	1		T19	3		T68	2
all_values[6]	auto[0]	auto[0]	2095549	1			T1	374		T3	2489		T5	7880
all_values[6]	auto[0]	auto[1]	209	1			T18	2		T19	2		T68	4
all_values[6]	auto[1]	auto[0]	53776	1			T18	6		T19	3		T21	1
all_values[6]	auto[1]	auto[1]	170	1			T18	4		T19	2		T68	3
all_values[7]	auto[0]	auto[0]	2115567	1			T1	374		T3	2489		T5	7880
all_values[7]	auto[0]	auto[1]	206	1			T18	4		T19	4		T68	7
all_values[7]	auto[1]	auto[0]	33748	1			T18	7		T68	2		T21	2
all_values[7]	auto[1]	auto[1]	183	1			T18	3		T19	5		T68	1