Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33157	1			T1	58		T8	8		T16	42
auto[SpiFlashAddrCfg]	7174	1			T1	28		T8	2		T11	6
auto[SpiFlashAddr3b]	8760	1			T1	35		T8	6		T13	2
auto[SpiFlashAddr4b]	7369	1			T1	39		T8	4		T10	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31456

1

T1

106

T8

20

T10

6

auto[1]

25004

1

T1

54

T13

16

T16

31

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29252

1

T1

78

T8

6

T11

4

auto[1]

27208

1

T1

82

T8

14

T10

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37570	1			T1	81		T8	8		T10	6
values[1]	1069	1			T1	6		T16	2		T29	3
values[2]	1411	1			T1	5		T14	4		T16	5
values[3]	1401	1			T1	8		T11	4		T14	2
values[4]	1362	1			T1	8		T13	2		T16	3
values[5]	1454	1			T1	4		T8	2		T16	3
values[6]	1463	1			T1	3		T8	4		T16	5
values[7]	1412	1			T1	4		T8	4		T13	8
values[8]	9318	1			T1	41		T8	2		T11	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28491

1

T1

160

T8

20

T10

6

auto[1]

27969

1

T16

104

T29

137

T31

143

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53459

1

T1

151

T8

16

T10

6

write

3001

1

T1

9

T8

4

T13

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18447

1

T1

83

T8

4

T11

2

valids[0x1]

38013

1

T1

77

T8

16

T10

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1440	1			T1	5		T16	2		T29	7
internal_process_ops[0x5a]	1466	1			T1	6		T8	2		T16	4
internal_process_ops[0x05]	20040	1			T1	6		T8	2		T16	9
internal_process_ops[0x35]	1503	1			T1	5		T13	2		T16	3
internal_process_ops[0x15]	1486	1			T1	6		T16	2		T29	8
internal_process_ops[0x03]	1024	1			T1	7		T14	6		T16	1
internal_process_ops[0x0b]	1011	1			T1	5		T16	3		T25	4
internal_process_ops[0x3b]	1025	1			T1	5		T13	4		T16	2
internal_process_ops[0x6b]	1028	1			T1	5		T14	4		T16	2
internal_process_ops[0xbb]	966	1			T1	5		T8	2		T13	2
internal_process_ops[0xeb]	1059	1			T1	2		T14	4		T29	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54955

1

T1

153

T8

20

T10

6

auto[1]

1505

1

T1

7

T13

2

T46

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54219

1

T1

151

T8

20

T10

6

auto[1]

2241

1

T1

9

T16

2

T29

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9404

1

T1

41

T8

6

T17

18

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5831

1

T1

17

T46

2

T47

60

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1865

1

T1

12

T8

2

T11

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1726

1

T1

13

T13

2

T47

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2411

1

T1

21

T8

6

T14

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1984

1

T1

12

T13

2

T46

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1956

1

T1

26

T8

2

T10

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1827

1

T1

9

T13

10

T46

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

114

1

T8

2

T42

2

T50

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

74

1

T171

3

T172

2

T173

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T50

2

T20

2

T172

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

123

1

T47

1

T51

2

T53

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

78

1

T47

1

T48

1

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T1

1

T47

3

T48

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

87

1

T1

2

T50

2

T171

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T13

2

T46

2

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

97

1

T174

8

T175

2

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

66

1

T1

2

T44

1

T170

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

76

1

T47

1

T50

1

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

86

1

T50

1

T51

1

T44

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

127

1

T8

2

T50

6

T44

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T1

3

T47

3

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T47

2

T50

1

T51

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T1

1

T48

2

T50

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9526

1

T16

26

T29

60

T31

79

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7651

1

T16

16

T29

21

T31

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1505

1

T16

23

T29

13

T31

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1374

1

T16

4

T29

2

T31

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1812

1

T16

8

T29

9

T31

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1828

1

T16

8

T29

10

T31

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1409

1

T16

15

T29

10

T31

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1350

1

T16

2

T29

8

T31

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

79

1

T176

2

T19

1

T177

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T31

1

T43

2

T84

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T29

2

T32

2

T85

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T84

1

T85

2

T178

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

98

1

T29

1

T54

2

T176

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T32

2

T84

2

T178

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

88

1

T29

1

T31

1

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T43

1

T176

1

T19

8

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T31

3

T84

1

T85

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

130

1

T31

1

T85

3

T176

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

67

1

T16

1

T31

1

T43

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T32

1

T43

2

T84

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T16

1

T32

2

T43

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

103

1

T32

1

T43

2

T84

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T32

3

T43

3

T85

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T43

1

T84

2

T85

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3684	1			T1	34		T17	18		T36	4
auto[0]	values[0]	valids[0x1]	14285	1			T1	47		T8	8		T10	6
auto[0]	values[1]	valids[0x1]	501	1			T1	6		T47	6		T48	1
auto[0]	values[2]	valids[0x0]	533	1			T1	4		T14	4		T47	6
auto[0]	values[2]	valids[0x1]	251	1			T1	1		T47	9		T48	1
auto[0]	values[3]	valids[0x0]	517	1			T1	4		T14	2		T25	6
auto[0]	values[3]	valids[0x1]	288	1			T1	4		T11	4		T47	4
auto[0]	values[4]	valids[0x0]	467	1			T1	6		T13	2		T47	4
auto[0]	values[4]	valids[0x1]	267	1			T1	2		T47	3		T50	8
auto[0]	values[5]	valids[0x0]	525	1			T8	2		T47	5		T48	1
auto[0]	values[5]	valids[0x1]	305	1			T1	4		T47	6		T48	3
auto[0]	values[6]	valids[0x0]	541	1			T1	2		T46	2		T47	4
auto[0]	values[6]	valids[0x1]	312	1			T1	1		T8	4		T46	6
auto[0]	values[7]	valids[0x0]	516	1			T1	3		T13	6		T47	7
auto[0]	values[7]	valids[0x1]	287	1			T1	1		T8	4		T13	2
auto[0]	values[8]	valids[0x0]	3281	1			T1	30		T8	2		T11	2
auto[0]	values[8]	valids[0x1]	1931	1			T1	11		T179	6		T47	27
auto[1]	values[0]	valids[0x0]	3756	1			T16	19		T29	24		T31	26
auto[1]	values[0]	valids[0x1]	15845	1			T16	32		T29	73		T31	77
auto[1]	values[1]	valids[0x1]	568	1			T16	2		T29	3		T43	9
auto[1]	values[2]	valids[0x0]	365	1			T29	2		T32	1		T43	2
auto[1]	values[2]	valids[0x1]	262	1			T16	5		T54	3		T85	4
auto[1]	values[3]	valids[0x0]	359	1			T16	4		T32	3		T43	3
auto[1]	values[3]	valids[0x1]	237	1			T16	1		T29	1		T31	1
auto[1]	values[4]	valids[0x0]	364	1			T16	2		T29	1		T32	1
auto[1]	values[4]	valids[0x1]	264	1			T16	1		T29	3		T32	1
auto[1]	values[5]	valids[0x0]	366	1			T16	1		T32	4		T43	3
auto[1]	values[5]	valids[0x1]	258	1			T16	2		T29	2		T32	1
auto[1]	values[6]	valids[0x0]	344	1			T16	2		T29	2		T31	2
auto[1]	values[6]	valids[0x1]	266	1			T16	3		T29	2		T43	4
auto[1]	values[7]	valids[0x0]	344	1			T29	2		T32	1		T43	5
auto[1]	values[7]	valids[0x1]	265	1			T16	1		T31	2		T43	2
auto[1]	values[8]	valids[0x0]	2485	1			T16	26		T29	19		T31	26
auto[1]	values[8]	valids[0x1]	1621	1			T16	3		T29	3		T31	9