Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3187642

1

T1

16555

T8

1

T10

870

auto[1]

28358

1

T1

1121

T16

4

T29

37

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

903930

1

T1

376

T8

1

T10

870

auto[1]

2312070

1

T1

17300

T16

4187

T29

5878

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	606383	1			T1	41		T8	1		T10	58
auto[524288:1048575]	424201	1			T1	1046		T10	237		T14	125
auto[1048576:1572863]	369516	1			T1	6007		T10	10		T14	149
auto[1572864:2097151]	364504	1			T1	1906		T10	66		T14	357
auto[2097152:2621439]	344126	1			T1	5218		T10	205		T14	300
auto[2621440:3145727]	394117	1			T1	326		T10	65		T14	349
auto[3145728:3670015]	365245	1			T1	1066		T10	65		T14	298
auto[3670016:4194303]	347908	1			T1	2066		T10	164		T14	271

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2347276

1

T1

17667

T8

1

T10

229

auto[1]

868724

1

T1

9

T10

641

T14

1774

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2734478

1

T1

17384

T8

1

T10

870

auto[1]

481522

1

T1

292

T16

483

T17

371

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	204679	1			T1	31		T8	1		T10	58
auto[0]	auto[0]	auto[0:524287]	auto[1]	343957	1			T16	517		T29	256		T31	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	125719	1			T1	20		T10	237		T14	125
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	232708	1			T1	1017		T16	2504		T29	2886
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	91027	1			T1	28		T10	10		T14	149
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	213809	1			T1	5149		T16	128		T29	512
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	90780	1			T1	26		T10	66		T14	357
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	223417	1			T1	1618		T16	256		T31	769
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	93339	1			T1	59		T10	205		T14	300
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	174760	1			T1	5149		T16	256		T29	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	100128	1			T1	48		T10	65		T14	349
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	220973	1			T1	4		T47	541		T48	118
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	91354	1			T1	34		T10	65		T14	298
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	209411	1			T1	1027		T47	6		T43	1589
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	92850	1			T1	48		T10	164		T14	271
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	202482	1			T1	2008		T16	52		T29	1926
auto[0]	auto[1]	auto[0:524287]	auto[0]	831	1			T16	3		T17	19		T36	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	52692	1			T16	216		T84	2965		T50	391
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	595	1			T1	9		T29	7		T31	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	61221	1			T29	257		T43	3		T50	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1468	1			T1	8		T17	3		T29	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	59869	1			T29	1		T84	1119		T85	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1564	1			T17	343		T47	3		T54	48
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	44920	1			T47	88		T54	1038		T50	3091
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3181	1			T1	5		T31	1		T47	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	70184	1			T31	256		T47	2977		T48	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	576	1			T1	11		T16	5		T29	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	68525	1			T1	256		T16	256		T29	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	994	1			T17	6		T47	7		T43	26
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	60353	1			T47	258		T43	3539		T50	2950
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	996	1			T16	1		T32	8		T47	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48280	1			T32	513		T47	256		T19	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	492	1			T1	10		T16	1		T42	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2612	1			T16	1		T42	9		T85	108
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	395	1			T31	5		T47	1		T43	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2764	1			T31	20		T47	9		T43	42
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	341	1			T1	3		T54	9		T84	31
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2380	1			T1	816		T84	21		T176	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	414	1			T1	6		T31	1		T32	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2841	1			T1	256		T31	11		T32	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	378	1			T1	5		T29	1		T31	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1902	1			T29	29		T31	5		T84	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	383	1			T1	7		T47	1		T48	6
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2912	1			T47	6		T85	27		T19	17
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	332	1			T1	5		T47	1		T43	10
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2082	1			T47	4		T50	14		T85	38
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	411	1			T1	10		T32	5		T43	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2446	1			T32	22		T48	60		T50	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	103	1			T16	1		T84	4		T50	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1017	1			T16	1		T50	8		T24	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	95	1			T29	1		T43	3		T50	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	704	1			T29	3		T50	10		T85	76
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	108	1			T1	3		T29	1		T84	22
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	514	1			T29	1		T84	33		T85	16
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	66	1			T50	1		T19	3		T204	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	502	1			T50	4		T19	16		T204	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	91	1			T44	3		T171	5		T172	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	291	1			T172	10		T22	1		T33	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	88	1			T29	1		T176	2		T204	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	532	1			T176	2		T204	1		T24	31
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	101	1			T47	2		T43	3		T84	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	618	1			T47	14		T50	8		T20	42
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	51	1			T32	1		T54	6		T84	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	392	1			T32	11		T19	8		T20	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1848362	1			T1	16266		T8	1		T10	229
auto[0]	auto[0]	auto[1]	863031	1			T10	641		T14	1774		T17	8
auto[0]	auto[1]	auto[0]	471215	1			T1	289		T16	481		T17	27
auto[0]	auto[1]	auto[1]	5034	1			T17	344		T193	54		T85	1
auto[1]	auto[0]	auto[0]	22550	1			T1	1110		T16	2		T29	29
auto[1]	auto[0]	auto[1]	535	1			T1	8		T29	1		T32	1
auto[1]	auto[1]	auto[0]	5149	1			T1	2		T16	2		T29	7
auto[1]	auto[1]	auto[1]	124	1			T1	1		T43	2		T54	1