Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[1]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[2]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[3]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[4]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[5]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[6]	2149704	1			T1	374		T3	2489		T5	7880
all_pins[7]	2149704	1			T1	374		T3	2489		T5	7880

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17139745	1			T1	2992		T3	19912		T5	63040
values[0x1]	57887	1			T18	26		T19	409		T68	12
transitions[0x0=>0x1]	56350	1			T18	18		T19	351		T68	10
transitions[0x1=>0x0]	56365	1			T18	19		T19	351		T68	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2149335	1			T1	374		T3	2489		T5	7880
all_pins[0]	values[0x1]	369	1			T18	2		T19	3		T68	2
all_pins[0]	transitions[0x0=>0x1]	197	1			T18	2		T19	2		T68	2
all_pins[0]	transitions[0x1=>0x0]	589	1			T18	4		T19	146		T68	3
all_pins[1]	values[0x0]	2148943	1			T1	374		T3	2489		T5	7880
all_pins[1]	values[0x1]	761	1			T18	4		T19	147		T68	3
all_pins[1]	transitions[0x0=>0x1]	532	1			T18	1		T19	94		T68	3
all_pins[1]	transitions[0x1=>0x0]	140	1			T18	2		T19	2		T21	2
all_pins[2]	values[0x0]	2149335	1			T1	374		T3	2489		T5	7880
all_pins[2]	values[0x1]	369	1			T18	5		T19	55		T21	2
all_pins[2]	transitions[0x0=>0x1]	332	1			T18	3		T19	55		T21	2
all_pins[2]	transitions[0x1=>0x0]	164	1			T18	1		T19	1		T68	1
all_pins[3]	values[0x0]	2149503	1			T1	374		T3	2489		T5	7880
all_pins[3]	values[0x1]	201	1			T18	3		T19	1		T68	1
all_pins[3]	transitions[0x0=>0x1]	143	1			T18	3		T68	1		T21	2
all_pins[3]	transitions[0x1=>0x0]	147	1			T18	4		T19	3		T21	1
all_pins[4]	values[0x0]	2149499	1			T1	374		T3	2489		T5	7880
all_pins[4]	values[0x1]	205	1			T18	4		T19	4		T21	1
all_pins[4]	transitions[0x0=>0x1]	164	1			T18	4		T19	2		T22	1
all_pins[4]	transitions[0x1=>0x0]	2334	1			T18	1		T19	190		T68	2
all_pins[5]	values[0x0]	2147329	1			T1	374		T3	2489		T5	7880
all_pins[5]	values[0x1]	2375	1			T18	1		T19	192		T68	2
all_pins[5]	transitions[0x0=>0x1]	1468	1			T19	191		T68	2		T21	2
all_pins[5]	transitions[0x1=>0x0]	52517	1			T18	3		T19	1		T68	3
all_pins[6]	values[0x0]	2096280	1			T1	374		T3	2489		T5	7880
all_pins[6]	values[0x1]	53424	1			T18	4		T19	2		T68	3
all_pins[6]	transitions[0x0=>0x1]	53387	1			T18	3		T19	2		T68	2
all_pins[6]	transitions[0x1=>0x0]	146	1			T18	2		T19	5		T21	1
all_pins[7]	values[0x0]	2149521	1			T1	374		T3	2489		T5	7880
all_pins[7]	values[0x1]	183	1			T18	3		T19	5		T68	1
all_pins[7]	transitions[0x0=>0x1]	127	1			T18	2		T19	5		T21	2
all_pins[7]	transitions[0x1=>0x0]	328	1			T18	2		T19	3		T68	1