Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16371

1

T1

106

T8

20

T10

6

auto[1]

12120

1

T1

54

T13

16

T46

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3931	1			T1	40		T47	27		T48	20
values[1]	4499	1			T1	20		T25	10		T179	6
values[2]	3902	1			T14	16		T36	4		T60	2
values[3]	2888	1			T1	40		T10	6		T11	8
values[4]	3580	1			T8	20		T13	16		T42	33
values[5]	3653	1			T1	40		T47	35		T63	4
values[6]	3015	1			T1	20		T47	20		T50	37
values[7]	3023	1			T17	18		T40	8		T46	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4028	1			T11	8		T17	18		T60	2
values[1]	3326	1			T1	20		T10	6		T13	16
values[2]	3045	1			T42	33		T47	40		T63	4
values[3]	3681	1			T1	60		T46	20		T47	20
values[4]	3865	1			T1	60		T8	20		T14	16
values[5]	4079	1			T47	35		T50	87		T193	12
values[6]	3583	1			T47	43		T48	20		T50	34
values[7]	2884	1			T1	20		T36	4		T40	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	345	1			T47	10		T50	13		T249	10
auto[0]	values[0]	values[1]	180	1			T175	2		T51	14		T96	16
auto[0]	values[0]	values[2]	215	1			T214	12		T199	22		T197	6
auto[0]	values[0]	values[3]	285	1			T1	22		T48	6		T50	9
auto[0]	values[0]	values[4]	128	1			T168	14		T216	18		T250	2
auto[0]	values[0]	values[5]	339	1			T50	22		T237	11		T202	13
auto[0]	values[0]	values[6]	222	1			T50	10		T20	59		T240	22
auto[0]	values[0]	values[7]	433	1			T50	16		T51	11		T203	16
auto[0]	values[1]	values[0]	418	1			T47	16		T51	13		T44	10
auto[0]	values[1]	values[1]	467	1			T1	13		T25	10		T202	11
auto[0]	values[1]	values[2]	281	1			T105	8		T51	14		T44	11
auto[0]	values[1]	values[3]	227	1			T198	15		T251	8		T78	52
auto[0]	values[1]	values[4]	487	1			T50	13		T226	16		T171	15
auto[0]	values[1]	values[5]	105	1			T51	11		T23	10		T196	8
auto[0]	values[1]	values[6]	267	1			T44	8		T252	24		T237	9
auto[0]	values[1]	values[7]	276	1			T179	6		T172	22		T253	2
auto[0]	values[2]	values[0]	362	1			T60	2		T50	11		T22	6
auto[0]	values[2]	values[1]	185	1			T171	16		T24	7		T254	15
auto[0]	values[2]	values[2]	389	1			T255	22		T24	13		T256	4
auto[0]	values[2]	values[3]	185	1			T20	15		T205	8		T232	12
auto[0]	values[2]	values[4]	297	1			T14	16		T44	9		T24	17
auto[0]	values[2]	values[5]	394	1			T20	14		T164	12		T237	12
auto[0]	values[2]	values[6]	298	1			T44	6		T171	8		T237	11
auto[0]	values[2]	values[7]	181	1			T36	4		T50	12		T202	11
auto[0]	values[3]	values[0]	196	1			T11	8		T257	2		T258	18
auto[0]	values[3]	values[1]	234	1			T10	6		T51	10		T237	9
auto[0]	values[3]	values[2]	144	1			T50	18		T20	11		T259	4
auto[0]	values[3]	values[3]	238	1			T1	14		T171	17		T68	9
auto[0]	values[3]	values[4]	242	1			T1	15		T47	21		T51	13
auto[0]	values[3]	values[5]	303	1			T172	123		T24	12		T33	25
auto[0]	values[3]	values[6]	249	1			T47	8		T24	20		T260	14
auto[0]	values[3]	values[7]	183	1			T47	32		T24	7		T223	6
auto[0]	values[4]	values[0]	176	1			T261	8		T237	13		T33	20
auto[0]	values[4]	values[1]	154	1			T20	15		T222	8		T202	8
auto[0]	values[4]	values[2]	237	1			T42	33		T47	9		T262	4
auto[0]	values[4]	values[3]	329	1			T51	10		T171	12		T263	6
auto[0]	values[4]	values[4]	461	1			T8	20		T22	13		T164	14
auto[0]	values[4]	values[5]	339	1			T51	7		T171	7		T20	6
auto[0]	values[4]	values[6]	147	1			T236	4		T199	17		T264	4
auto[0]	values[4]	values[7]	149	1			T48	12		T24	11		T210	21
auto[0]	values[5]	values[0]	238	1			T48	12		T171	12		T22	7
auto[0]	values[5]	values[1]	264	1			T49	14		T44	9		T20	14
auto[0]	values[5]	values[2]	237	1			T63	4		T171	14		T24	15
auto[0]	values[5]	values[3]	293	1			T48	10		T50	18		T44	14
auto[0]	values[5]	values[4]	219	1			T1	16		T48	9		T221	7
auto[0]	values[5]	values[5]	327	1			T47	25		T24	11		T265	16
auto[0]	values[5]	values[6]	259	1			T98	10		T197	11		T200	14
auto[0]	values[5]	values[7]	197	1			T1	10		T168	7		T35	10
auto[0]	values[6]	values[0]	448	1			T199	8		T201	12		T266	12
auto[0]	values[6]	values[1]	292	1			T170	11		T68	14		T173	17
auto[0]	values[6]	values[2]	175	1			T213	6		T164	16		T203	27
auto[0]	values[6]	values[3]	251	1			T51	13		T20	101		T172	12
auto[0]	values[6]	values[4]	260	1			T1	16		T47	6		T267	18
auto[0]	values[6]	values[5]	309	1			T50	26		T193	12		T211	22
auto[0]	values[6]	values[6]	207	1			T24	13		T237	16		T209	12
auto[0]	values[6]	values[7]	98	1			T171	15		T202	14		T205	9
auto[0]	values[7]	values[0]	204	1			T17	18		T237	13		T268	6
auto[0]	values[7]	values[1]	179	1			T173	12		T164	17		T269	20
auto[0]	values[7]	values[2]	245	1			T47	15		T174	20		T270	6
auto[0]	values[7]	values[3]	248	1			T47	8		T50	10		T33	12
auto[0]	values[7]	values[4]	198	1			T51	6		T44	14		T171	16
auto[0]	values[7]	values[5]	190	1			T197	22		T271	10		T272	8
auto[0]	values[7]	values[6]	168	1			T48	7		T164	6		T254	12
auto[0]	values[7]	values[7]	118	1			T40	8		T171	17		T164	13
auto[1]	values[0]	values[0]	365	1			T47	17		T50	7		T44	9
auto[1]	values[0]	values[1]	129	1			T51	6		T202	13		T203	7
auto[1]	values[0]	values[2]	153	1			T199	12		T197	14		T81	24
auto[1]	values[0]	values[3]	177	1			T1	18		T48	14		T50	11
auto[1]	values[0]	values[4]	235	1			T168	8		T273	41		T233	80
auto[1]	values[0]	values[5]	306	1			T50	28		T237	9		T202	11
auto[1]	values[0]	values[6]	220	1			T50	24		T20	6		T200	6
auto[1]	values[0]	values[7]	199	1			T50	6		T51	9		T203	9
auto[1]	values[1]	values[0]	249	1			T47	8		T51	7		T44	10
auto[1]	values[1]	values[1]	274	1			T1	7		T202	9		T33	8
auto[1]	values[1]	values[2]	194	1			T51	6		T44	9		T52	20
auto[1]	values[1]	values[3]	126	1			T274	10		T198	5		T275	18
auto[1]	values[1]	values[4]	233	1			T50	15		T171	5		T164	19
auto[1]	values[1]	values[5]	302	1			T51	9		T23	12		T198	15
auto[1]	values[1]	values[6]	339	1			T44	12		T237	11		T218	2
auto[1]	values[1]	values[7]	254	1			T172	3		T203	8		T200	6
auto[1]	values[2]	values[0]	238	1			T50	9		T22	18		T221	7
auto[1]	values[2]	values[1]	120	1			T171	4		T24	13		T254	5
auto[1]	values[2]	values[2]	155	1			T24	7		T201	10		T198	7
auto[1]	values[2]	values[3]	174	1			T20	45		T205	19		T271	8
auto[1]	values[2]	values[4]	132	1			T44	11		T248	16		T24	12
auto[1]	values[2]	values[5]	290	1			T20	6		T164	8		T237	8
auto[1]	values[2]	values[6]	296	1			T44	14		T171	12		T237	9
auto[1]	values[2]	values[7]	206	1			T50	8		T202	9		T201	6
auto[1]	values[3]	values[0]	73	1			T202	17		T205	14		T201	3
auto[1]	values[3]	values[1]	114	1			T51	10		T237	11		T33	3
auto[1]	values[3]	values[2]	61	1			T50	2		T20	9		T276	13
auto[1]	values[3]	values[3]	184	1			T1	6		T171	3		T68	11
auto[1]	values[3]	values[4]	85	1			T1	5		T47	21		T51	7
auto[1]	values[3]	values[5]	208	1			T172	9		T24	8		T33	24
auto[1]	values[3]	values[6]	261	1			T47	35		T24	4		T199	2
auto[1]	values[3]	values[7]	113	1			T47	10		T24	14		T206	9
auto[1]	values[4]	values[0]	81	1			T237	7		T33	7		T203	13
auto[1]	values[4]	values[1]	212	1			T13	16		T20	80		T202	12
auto[1]	values[4]	values[2]	198	1			T47	11		T199	40		T198	11
auto[1]	values[4]	values[3]	396	1			T51	10		T171	8		T20	36
auto[1]	values[4]	values[4]	208	1			T22	11		T164	8		T24	21
auto[1]	values[4]	values[5]	231	1			T51	13		T171	13		T20	41
auto[1]	values[4]	values[6]	124	1			T199	3		T203	34		T277	6
auto[1]	values[4]	values[7]	138	1			T48	8		T246	16		T24	12
auto[1]	values[5]	values[0]	281	1			T48	8		T171	8		T22	14
auto[1]	values[5]	values[1]	305	1			T278	4		T44	11		T20	62
auto[1]	values[5]	values[2]	121	1			T171	6		T24	8		T199	27
auto[1]	values[5]	values[3]	195	1			T48	10		T50	8		T44	6
auto[1]	values[5]	values[4]	308	1			T1	4		T48	11		T221	24
auto[1]	values[5]	values[5]	128	1			T47	10		T24	9		T205	5
auto[1]	values[5]	values[6]	99	1			T197	10		T200	6		T78	8
auto[1]	values[5]	values[7]	182	1			T1	10		T168	30		T35	10
auto[1]	values[6]	values[0]	136	1			T199	19		T201	8		T266	8
auto[1]	values[6]	values[1]	106	1			T170	9		T68	6		T173	20
auto[1]	values[6]	values[2]	95	1			T164	7		T203	7		T198	18
auto[1]	values[6]	values[3]	102	1			T51	7		T20	6		T172	8
auto[1]	values[6]	values[4]	138	1			T1	4		T47	14		T33	7
auto[1]	values[6]	values[5]	228	1			T50	11		T237	9		T209	21
auto[1]	values[6]	values[6]	110	1			T24	7		T237	4		T209	8
auto[1]	values[6]	values[7]	60	1			T171	5		T202	6		T205	11
auto[1]	values[7]	values[0]	218	1			T237	7		T279	2		T254	69
auto[1]	values[7]	values[1]	111	1			T173	8		T164	5		T203	10
auto[1]	values[7]	values[2]	145	1			T47	5		T172	39		T22	7
auto[1]	values[7]	values[3]	271	1			T46	20		T47	12		T50	24
auto[1]	values[7]	values[4]	234	1			T51	14		T44	6		T171	4
auto[1]	values[7]	values[5]	80	1			T197	8		T271	10		T272	12
auto[1]	values[7]	values[6]	317	1			T48	13		T164	14		T280	14
auto[1]	values[7]	values[7]	97	1			T171	3		T164	7		T218	12