Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	357	1			T47	2		T48	4		T50	3
auto[ReadAddrCrossIntoMailbox]	269	1			T1	3		T14	2		T48	1
auto[ReadAddrCrossOutOfMailbox]	295	1			T14	2		T25	6		T47	3
auto[ReadAddrCrossAllMailbox]	219	1			T1	1		T14	6		T48	2
auto[ReadAddrOutsideMailbox]	3445	1			T1	25		T8	2		T13	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2266

1

T1

13

T8

1

T13

3

auto[1]

2319

1

T1

16

T8

1

T13

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	786	1			T1	7		T14	6		T46	4
read_ops[0x0b]	746	1			T1	5		T25	4		T60	2
read_ops[0x3b]	792	1			T1	5		T13	4		T46	4
read_ops[0x6b]	771	1			T1	5		T14	4		T25	6
read_ops[0xbb]	706	1			T1	5		T8	2		T13	2
read_ops[0xeb]	784	1			T1	2		T14	4		T46	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T47	1		T172	1		T202	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T50	1		T44	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T50	1		T171	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T20	1		T237	1		T281	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T237	1		T276	1		T218	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T50	1		T20	1		T237	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T14	1		T20	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T14	1		T20	1		T206	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T1	3		T14	2		T46	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T1	4		T14	2		T46	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T24	1		T237	1		T33	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T48	2		T171	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T171	2		T22	2		T173	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T1	1		T238	1		T197	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T25	1		T20	1		T24	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T25	1		T50	1		T171	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T173	1		T24	1		T237	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T1	1		T50	1		T171	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T1	2		T25	1		T60	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T1	1		T25	1		T60	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T48	1		T50	1		T24	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T50	1		T51	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T1	2		T48	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T50	1		T24	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T171	2		T20	2		T265	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T44	1		T202	2		T199	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T237	1		T202	1		T265	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T48	1		T20	1		T237	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T1	2		T13	2		T46	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T1	1		T13	2		T46	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T47	1		T44	1		T20	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T51	1		T22	1		T164	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T50	1		T44	1		T20	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T50	2		T51	2		T44	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T25	2		T47	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T25	2		T47	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T14	2		T44	1		T23	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T14	2		T48	1		T171	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T25	1		T47	3		T48	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T1	5		T25	1		T47	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T51	1		T44	1		T68	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T237	1		T33	1		T276	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T199	1		T276	2		T209	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T237	1		T33	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T51	2		T68	1		T20	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T47	1		T173	1		T164	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T50	1		T171	1		T237	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T265	1		T203	1		T200	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T1	2		T8	1		T13	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	260	1			T1	3		T8	1		T13	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T51	1		T24	1		T237	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T48	1		T171	1		T68	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T14	1		T24	1		T237	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T14	1		T50	1		T51	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T14	1		T172	1		T237	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T14	1		T48	4		T171	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T237	2		T199	1		T209	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T44	1		T171	1		T173	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T1	2		T46	1		T50	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T46	1		T47	6		T48	1