Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3505	1			T17	18		T40	8		T46	20
values[1]	3473	1			T1	20		T8	20		T10	6
values[2]	2957	1			T25	10		T36	4		T60	2
values[3]	3345	1			T1	20		T11	8		T179	6
values[4]	3982	1			T1	20		T13	16		T48	20
values[5]	3592	1			T1	20		T47	40		T105	8
values[6]	3449	1			T1	20		T14	16		T47	121
values[7]	4188	1			T1	60		T47	20		T48	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3269	1			T1	20		T10	6		T47	27
values[1]	3234	1			T1	20		T13	16		T47	60
values[2]	2732	1			T8	20		T63	4		T214	12
values[3]	3772	1			T17	18		T25	10		T40	8
values[4]	4577	1			T1	60		T11	8		T14	16
values[5]	3711	1			T1	20		T48	20		T174	20
values[6]	3401	1			T36	4		T47	65		T105	8
values[7]	3795	1			T1	40		T46	20		T47	59

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27764

1

T1

153

T8

20

T10

6

auto[1]

727

1

T1

7

T13

2

T46

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	626	1			T50	35		T238	28		T78	20
auto[0]	values[0]	values[1]	354	1			T171	20		T24	21		T237	19
auto[0]	values[0]	values[2]	321	1			T22	24		T267	18		T237	19
auto[0]	values[0]	values[3]	306	1			T17	18		T40	8		T238	23
auto[0]	values[0]	values[4]	438	1			T50	39		T49	14		T171	18
auto[0]	values[0]	values[5]	506	1			T174	20		T24	23		T205	20
auto[0]	values[0]	values[6]	345	1			T47	21		T20	40		T173	19
auto[0]	values[0]	values[7]	507	1			T46	18		T44	13		T68	20
auto[0]	values[1]	values[0]	255	1			T10	6		T282	6		T200	20
auto[0]	values[1]	values[1]	286	1			T1	16		T20	60		T283	12
auto[0]	values[1]	values[2]	493	1			T8	20		T52	12		T20	64
auto[0]	values[1]	values[3]	298	1			T51	20		T284	2		T202	21
auto[0]	values[1]	values[4]	548	1			T50	48		T44	17		T202	91
auto[0]	values[1]	values[5]	436	1			T51	20		T24	20		T210	20
auto[0]	values[1]	values[6]	335	1			T255	22		T199	24		T209	24
auto[0]	values[1]	values[7]	714	1			T171	20		T168	34		T285	18
auto[0]	values[2]	values[0]	426	1			T50	33		T286	4		T206	20
auto[0]	values[2]	values[1]	404	1			T22	22		T163	16		T24	23
auto[0]	values[2]	values[2]	251	1			T63	4		T44	20		T287	4
auto[0]	values[2]	values[3]	292	1			T25	10		T60	2		T48	19
auto[0]	values[2]	values[4]	454	1			T42	33		T261	8		T200	18
auto[0]	values[2]	values[5]	325	1			T48	20		T51	38		T237	20
auto[0]	values[2]	values[6]	460	1			T36	4		T171	20		T203	34
auto[0]	values[2]	values[7]	259	1			T48	20		T164	27		T288	10
auto[0]	values[3]	values[0]	260	1			T47	26		T246	16		T20	45
auto[0]	values[3]	values[1]	211	1			T44	19		T257	2		T172	18
auto[0]	values[3]	values[2]	426	1			T20	94		T164	20		T33	40
auto[0]	values[3]	values[3]	547	1			T179	6		T20	125		T252	24
auto[0]	values[3]	values[4]	480	1			T1	20		T11	8		T47	20
auto[0]	values[3]	values[5]	499	1			T222	8		T289	2		T205	23
auto[0]	values[3]	values[6]	374	1			T47	42		T50	26		T164	20
auto[0]	values[3]	values[7]	458	1			T50	28		T98	10		T290	8
auto[0]	values[4]	values[0]	665	1			T278	4		T168	22		T291	41
auto[0]	values[4]	values[1]	572	1			T13	14		T48	18		T205	23
auto[0]	values[4]	values[2]	153	1			T164	22		T209	20		T206	20
auto[0]	values[4]	values[3]	532	1			T51	19		T24	20		T237	20
auto[0]	values[4]	values[4]	595	1			T171	20		T221	20		T202	18
auto[0]	values[4]	values[5]	472	1			T44	20		T24	20		T202	19
auto[0]	values[4]	values[6]	402	1			T44	20		T170	27		T171	20
auto[0]	values[4]	values[7]	505	1			T1	20		T171	20		T237	20
auto[0]	values[5]	values[0]	327	1			T262	4		T254	76		T209	19
auto[0]	values[5]	values[1]	392	1			T47	20		T50	22		T292	4
auto[0]	values[5]	values[2]	353	1			T249	10		T20	20		T172	22
auto[0]	values[5]	values[3]	610	1			T171	20		T293	14		T217	24
auto[0]	values[5]	values[4]	553	1			T47	20		T53	43		T258	18
auto[0]	values[5]	values[5]	279	1			T294	20		T195	12		T295	19
auto[0]	values[5]	values[6]	604	1			T105	8		T50	20		T51	20
auto[0]	values[5]	values[7]	395	1			T1	19		T193	12		T51	19
auto[0]	values[6]	values[0]	320	1			T213	6		T171	19		T237	19
auto[0]	values[6]	values[1]	461	1			T47	20		T50	34		T270	6
auto[0]	values[6]	values[2]	284	1			T51	19		T237	20		T199	26
auto[0]	values[6]	values[3]	422	1			T47	38		T48	18		T44	20
auto[0]	values[6]	values[4]	457	1			T14	16		T236	4		T24	23
auto[0]	values[6]	values[5]	622	1			T1	19		T51	20		T44	20
auto[0]	values[6]	values[6]	360	1			T202	27		T35	20		T199	59
auto[0]	values[6]	values[7]	446	1			T47	59		T248	10		T202	20
auto[0]	values[7]	values[0]	306	1			T1	20		T48	19		T50	19
auto[0]	values[7]	values[1]	475	1			T47	20		T170	18		T68	19
auto[0]	values[7]	values[2]	376	1			T214	12		T24	29		T202	19
auto[0]	values[7]	values[3]	683	1			T50	20		T51	20		T44	20
auto[0]	values[7]	values[4]	925	1			T1	39		T175	2		T20	20
auto[0]	values[7]	values[5]	489	1			T172	132		T240	22		T212	20
auto[0]	values[7]	values[6]	442	1			T237	35		T199	20		T212	18
auto[0]	values[7]	values[7]	393	1			T22	21		T247	8		T157	20
auto[1]	values[0]	values[0]	19	1			T50	2		T238	3		T295	2
auto[1]	values[0]	values[1]	7	1			T237	1		T296	2		T203	2
auto[1]	values[0]	values[2]	13	1			T237	1		T199	1		T82	2
auto[1]	values[0]	values[3]	4	1			T238	1		T297	3		-	-
auto[1]	values[0]	values[4]	19	1			T50	1		T171	2		T172	5
auto[1]	values[0]	values[5]	11	1			T203	2		T273	1		T233	3
auto[1]	values[0]	values[6]	6	1			T47	1		T173	1		T206	1
auto[1]	values[0]	values[7]	23	1			T46	2		T44	7		T22	1
auto[1]	values[1]	values[0]	5	1			T271	2		T298	3		-	-
auto[1]	values[1]	values[1]	11	1			T1	4		T299	1		T300	1
auto[1]	values[1]	values[2]	17	1			T52	8		T20	1		T172	2
auto[1]	values[1]	values[3]	11	1			T202	3		T205	3		T200	1
auto[1]	values[1]	values[4]	19	1			T44	3		T202	3		T200	1
auto[1]	values[1]	values[5]	9	1			T210	2		T301	2		T298	2
auto[1]	values[1]	values[6]	6	1			T209	1		T302	2		T303	1
auto[1]	values[1]	values[7]	30	1			T168	3		T33	1		T212	2
auto[1]	values[2]	values[0]	19	1			T50	1		T272	3		T162	1
auto[1]	values[2]	values[1]	9	1			T22	2		T24	1		T304	1
auto[1]	values[2]	values[2]	4	1			T299	1		T305	1		T306	2
auto[1]	values[2]	values[3]	5	1			T48	1		T272	4		-	-
auto[1]	values[2]	values[4]	19	1			T200	2		T198	1		T273	2
auto[1]	values[2]	values[5]	12	1			T51	2		T210	1		T206	1
auto[1]	values[2]	values[6]	17	1			T200	1		T201	1		T78	1
auto[1]	values[2]	values[7]	1	1			T307	1		-	-		-	-
auto[1]	values[3]	values[0]	5	1			T47	1		T20	2		T197	1
auto[1]	values[3]	values[1]	8	1			T44	1		T172	2		T202	1
auto[1]	values[3]	values[2]	16	1			T20	1		T33	1		T206	1
auto[1]	values[3]	values[3]	13	1			T20	2		T173	4		T202	2
auto[1]	values[3]	values[4]	11	1			T212	1		T203	1		T129	1
auto[1]	values[3]	values[5]	11	1			T228	1		T273	1		T233	4
auto[1]	values[3]	values[6]	8	1			T47	1		T242	1		T56	1
auto[1]	values[3]	values[7]	18	1			T50	2		T290	2		T276	1
auto[1]	values[4]	values[0]	15	1			T237	2		T266	4		T78	2
auto[1]	values[4]	values[1]	14	1			T13	2		T48	2		T205	1
auto[1]	values[4]	values[2]	2	1			T271	1		T41	1		-	-
auto[1]	values[4]	values[3]	7	1			T51	1		T24	1		T271	3
auto[1]	values[4]	values[4]	15	1			T202	2		T33	2		T197	3
auto[1]	values[4]	values[5]	12	1			T202	1		T33	1		T254	1
auto[1]	values[4]	values[6]	10	1			T200	2		T231	1		T308	6
auto[1]	values[4]	values[7]	11	1			T33	1		T209	2		T198	2
auto[1]	values[5]	values[0]	7	1			T254	2		T209	1		T271	1
auto[1]	values[5]	values[1]	12	1			T203	1		T197	1		T200	2
auto[1]	values[5]	values[2]	13	1			T172	3		T24	2		T199	1
auto[1]	values[5]	values[3]	12	1			T203	4		T198	3		T228	2
auto[1]	values[5]	values[4]	8	1			T53	1		T210	2		T229	1
auto[1]	values[5]	values[5]	8	1			T294	1		T295	1		T242	1
auto[1]	values[5]	values[6]	8	1			T221	3		T237	1		T198	1
auto[1]	values[5]	values[7]	11	1			T1	1		T51	1		T20	1
auto[1]	values[6]	values[0]	7	1			T171	1		T237	1		T254	1
auto[1]	values[6]	values[1]	5	1			T209	2		T231	3		-	-
auto[1]	values[6]	values[2]	5	1			T51	1		T199	1		T273	1
auto[1]	values[6]	values[3]	11	1			T47	4		T48	2		T266	1
auto[1]	values[6]	values[4]	13	1			T24	1		T237	1		T199	1
auto[1]	values[6]	values[5]	10	1			T1	1		T309	1		T206	2
auto[1]	values[6]	values[6]	7	1			T201	3		T215	1		T310	1
auto[1]	values[6]	values[7]	19	1			T248	6		T311	3		T231	1
auto[1]	values[7]	values[0]	7	1			T48	1		T50	1		T205	3
auto[1]	values[7]	values[1]	13	1			T170	2		T68	1		T33	2
auto[1]	values[7]	values[2]	5	1			T202	1		T238	1		T129	1
auto[1]	values[7]	values[3]	19	1			T171	2		T164	1		T24	1
auto[1]	values[7]	values[4]	23	1			T1	1		T203	1		T201	3
auto[1]	values[7]	values[5]	10	1			T157	1		T312	4		T78	1
auto[1]	values[7]	values[6]	17	1			T237	5		T212	2		T229	2
auto[1]	values[7]	values[7]	5	1			T272	2		T313	2		T314	1