Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	812	1			T18	14		T19	10		T68	11
all_values[1]	812	1			T18	14		T19	10		T68	11
all_values[2]	812	1			T18	14		T19	10		T68	11
all_values[3]	812	1			T18	14		T19	10		T68	11
all_values[4]	812	1			T18	14		T19	10		T68	11
all_values[5]	812	1			T18	14		T19	10		T68	11
all_values[6]	812	1			T18	14		T19	10		T68	11
all_values[7]	812	1			T18	14		T19	10		T68	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3481

1

T18

59

T19

42

T68

59

auto[1]

3015

1

T18

53

T19

38

T68

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2587

1

T18

43

T19

23

T68

47

auto[1]

3909

1

T18

69

T19

57

T68

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3701

1

T18

59

T19

35

T68

57

auto[1]

2795

1

T18

53

T19

45

T68

31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	156	1			T18	3		T19	3		T68	4
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T18	1		T19	1		T22	1
all_values[0]	auto[0]	auto[1]	auto[0]	126	1			T18	4		T68	3		T21	2
all_values[0]	auto[0]	auto[1]	auto[1]	95	1			T18	2		T19	1		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	202	1			T18	3		T19	3		T68	1
all_values[0]	auto[1]	auto[1]	auto[1]	159	1			T18	1		T19	2		T68	3
all_values[1]	auto[0]	auto[0]	auto[0]	162	1			T18	3		T19	2		T68	6
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T18	1		T19	1		T21	2
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T18	1		T19	3		T21	2
all_values[1]	auto[0]	auto[1]	auto[1]	90	1			T18	2		T68	1		T21	1
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T18	5		T68	2		T21	4
all_values[1]	auto[1]	auto[1]	auto[1]	155	1			T18	2		T19	4		T68	2
all_values[2]	auto[0]	auto[0]	auto[0]	182	1			T18	4		T19	1		T68	5
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T19	1		T68	1		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T18	2		T68	2		T22	1
all_values[2]	auto[0]	auto[1]	auto[1]	60	1			T18	1		T19	1		T21	2
all_values[2]	auto[1]	auto[0]	auto[1]	180	1			T18	3		T19	4		T68	2
all_values[2]	auto[1]	auto[1]	auto[1]	164	1			T18	4		T19	3		T68	1
all_values[3]	auto[0]	auto[0]	auto[0]	152	1			T19	2		T68	4		T21	2
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T18	3		T68	2		T22	1
all_values[3]	auto[0]	auto[1]	auto[0]	122	1			T18	2		T19	1		T68	1
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T18	1		T23	4		T24	2
all_values[3]	auto[1]	auto[0]	auto[1]	208	1			T18	6		T19	4		T68	3
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T18	2		T19	3		T68	1
all_values[4]	auto[0]	auto[0]	auto[0]	153	1			T18	2		T19	1		T68	5
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T18	2		T19	1		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T18	3		T19	1		T68	4
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T18	1		T19	1		T23	1
all_values[4]	auto[1]	auto[0]	auto[1]	189	1			T18	2		T19	3		T68	1
all_values[4]	auto[1]	auto[1]	auto[1]	164	1			T18	4		T19	3		T68	1
all_values[5]	auto[0]	auto[0]	auto[0]	235	1			T18	4		T19	3		T68	4
all_values[5]	auto[0]	auto[1]	auto[0]	222	1			T18	3		T19	2		T68	3
all_values[5]	auto[1]	auto[0]	auto[1]	181	1			T18	4		T19	2		T68	2
all_values[5]	auto[1]	auto[1]	auto[1]	174	1			T18	3		T19	3		T68	2
all_values[6]	auto[0]	auto[0]	auto[0]	171	1			T18	3		T19	1		T68	4
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T19	1		T68	1		T21	3
all_values[6]	auto[0]	auto[1]	auto[0]	146	1			T18	3		T19	3		T22	1
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T19	1		T21	1		T22	1
all_values[6]	auto[1]	auto[0]	auto[1]	202	1			T18	4		T19	2		T68	3
all_values[6]	auto[1]	auto[1]	auto[1]	142	1			T18	4		T19	2		T68	3
all_values[7]	auto[0]	auto[0]	auto[0]	182	1			T68	2		T21	2		T22	3
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T18	1		T19	3		T68	5
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T18	6		T21	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T18	1		T21	2		T22	1
all_values[7]	auto[1]	auto[0]	auto[1]	183	1			T18	5		T19	3		T68	2
all_values[7]	auto[1]	auto[1]	auto[1]	148	1			T18	1		T19	4		T68	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal