Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T3

1

T5

1

T12

4

auto[1]

1793

1

T3

1

T5

7

T12

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1766

1

T3

2

T5

8

T16

8

auto[1]

1872

1

T12

7

T32

1

T62

34

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2968

1

T5

6

T12

7

T16

7

auto[1]

670

1

T3

2

T5

2

T16

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	726	1			T5	3		T12	1		T16	5
valid[1]	735	1			T3	1		T5	3		T12	1
valid[2]	733	1			T12	2		T16	1		T29	2
valid[3]	683	1			T3	1		T12	2		T29	1
valid[4]	761	1			T5	2		T12	1		T16	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	108	1			T16	4		T27	1		T31	1
auto[0]	auto[0]	valid[0]	auto[1]	179	1			T32	1		T62	1		T94	2
auto[0]	auto[0]	valid[1]	auto[0]	119	1			T5	1		T27	1		T92	1
auto[0]	auto[0]	valid[1]	auto[1]	190	1			T62	2		T91	1		T95	1
auto[0]	auto[0]	valid[2]	auto[0]	104	1			T16	1		T29	1		T27	1
auto[0]	auto[0]	valid[2]	auto[1]	186	1			T12	1		T62	1		T95	3
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T29	1		T27	1		T19	1
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T12	2		T62	2		T94	1
auto[0]	auto[0]	valid[4]	auto[0]	130	1			T27	1		T31	2		T32	2
auto[0]	auto[0]	valid[4]	auto[1]	203	1			T12	1		T62	5		T94	2
auto[0]	auto[1]	valid[0]	auto[0]	116	1			T5	2		T16	1		T31	3
auto[0]	auto[1]	valid[0]	auto[1]	187	1			T12	1		T62	4		T93	1
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T5	2		T29	1		T47	2
auto[0]	auto[1]	valid[1]	auto[1]	188	1			T12	1		T62	2		T95	4
auto[0]	auto[1]	valid[2]	auto[0]	101	1			T91	1		T92	1		T50	1
auto[0]	auto[1]	valid[2]	auto[1]	193	1			T12	1		T62	8		T91	2
auto[0]	auto[1]	valid[3]	auto[0]	102	1			T27	2		T31	1		T32	1
auto[0]	auto[1]	valid[3]	auto[1]	182	1			T62	6		T92	1		T343	4
auto[0]	auto[1]	valid[4]	auto[0]	97	1			T5	1		T16	1		T27	1
auto[0]	auto[1]	valid[4]	auto[1]	193	1			T62	3		T93	1		T95	6
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T47	1		T19	1		T328	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T47	1		T50	1		T337	2
auto[1]	auto[0]	valid[2]	auto[0]	82	1			T27	1		T31	1		T32	1
auto[1]	auto[0]	valid[3]	auto[0]	60	1			T3	1		T32	2		T91	2
auto[1]	auto[0]	valid[4]	auto[0]	61	1			T16	1		T27	1		T92	2
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T5	1		T50	1		T170	1
auto[1]	auto[1]	valid[1]	auto[0]	60	1			T3	1		T27	1		T31	1
auto[1]	auto[1]	valid[2]	auto[0]	67	1			T29	1		T27	1		T92	1
auto[1]	auto[1]	valid[3]	auto[0]	57	1			T31	1		T32	1		T91	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T5	1		T47	1		T19	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal