Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46361

1

T3

95

T5

376

T7

10

auto[1]

19663

1

T3

22

T12

7

T32

37

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48968

1

T3

80

T5

256

T7

4

auto[1]

17056

1

T3

37

T5

120

T7

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33809	1			T3	59		T5	183		T7	4
others[1]	5645	1			T3	4		T5	38		T16	24
others[2]	5587	1			T3	10		T5	32		T16	11
others[3]	6290	1			T3	13		T5	37		T7	2
interest[1]	3645	1			T3	11		T5	19		T7	2
interest[4]	22119	1			T3	37		T5	111		T7	4
interest[64]	11048	1			T3	20		T5	67		T7	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14969	1			T3	30		T5	131		T7	1
auto[0]	auto[0]	others[1]	2567	1			T3	2		T5	22		T16	21
auto[0]	auto[0]	others[2]	2437	1			T3	5		T5	20		T16	5
auto[0]	auto[0]	others[3]	2780	1			T3	8		T5	25		T7	1
auto[0]	auto[0]	interest[1]	1611	1			T3	5		T5	12		T7	2
auto[0]	auto[0]	interest[4]	9729	1			T3	16		T5	77		T7	1
auto[0]	auto[0]	interest[64]	4941	1			T3	8		T5	46		T16	20
auto[0]	auto[1]	others[0]	10143	1			T3	11		T12	7		T32	19
auto[0]	auto[1]	others[1]	1603	1			T32	2		T62	26		T94	2
auto[0]	auto[1]	others[2]	1706	1			T3	4		T32	4		T62	34
auto[0]	auto[1]	others[3]	1841	1			T3	2		T32	6		T62	38
auto[0]	auto[1]	interest[1]	1073	1			T3	1		T32	2		T62	19
auto[0]	auto[1]	interest[4]	6704	1			T3	7		T12	7		T32	14
auto[0]	auto[1]	interest[64]	3297	1			T3	4		T32	4		T62	70
auto[1]	auto[0]	others[0]	8697	1			T3	18		T5	52		T7	3
auto[1]	auto[0]	others[1]	1475	1			T3	2		T5	16		T16	3
auto[1]	auto[0]	others[2]	1444	1			T3	1		T5	12		T16	6
auto[1]	auto[0]	others[3]	1669	1			T3	3		T5	12		T7	1
auto[1]	auto[0]	interest[1]	961	1			T3	5		T5	7		T16	3
auto[1]	auto[0]	interest[4]	5686	1			T3	14		T5	34		T7	3
auto[1]	auto[0]	interest[64]	2810	1			T3	8		T5	21		T7	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal