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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

T152 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1840841636 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:14 PM PDT 24 229916920 ps
T1032 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1499279282 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:08 PM PDT 24 17762827 ps
T153 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1622688085 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:06 PM PDT 24 138049004 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3763806587 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:45 PM PDT 24 7516757603 ps
T154 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3455564859 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:17 PM PDT 24 353109260 ps
T1033 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1236863932 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 133694120 ps
T183 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3362061008 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:22 PM PDT 24 418874852 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4067540531 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:17 PM PDT 24 1319169922 ps
T1034 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2396286545 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:16 PM PDT 24 29509221 ps
T107 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2289263116 Aug 17 06:33:59 PM PDT 24 Aug 17 06:34:05 PM PDT 24 283879142 ps
T1035 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.424504254 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 17719215 ps
T110 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2182454965 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:12 PM PDT 24 177504192 ps
T155 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4155042433 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:26 PM PDT 24 7065188071 ps
T125 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.816964840 Aug 17 06:34:00 PM PDT 24 Aug 17 06:34:02 PM PDT 24 148914678 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2173915822 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 75994618 ps
T1036 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3228499676 Aug 17 06:33:58 PM PDT 24 Aug 17 06:33:59 PM PDT 24 14299069 ps
T1037 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2278631038 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:12 PM PDT 24 36394959 ps
T1038 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2289223508 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:08 PM PDT 24 29791158 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2207737447 Aug 17 06:34:00 PM PDT 24 Aug 17 06:34:13 PM PDT 24 649143561 ps
T184 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4081865113 Aug 17 06:34:18 PM PDT 24 Aug 17 06:34:30 PM PDT 24 209237381 ps
T156 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.338445140 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:13 PM PDT 24 1392864110 ps
T1040 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.943548005 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:11 PM PDT 24 25250501 ps
T1041 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.639838390 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:12 PM PDT 24 197465491 ps
T1042 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2573457956 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:10 PM PDT 24 16070773 ps
T1043 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.172513800 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:16 PM PDT 24 479885534 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3353248460 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:12 PM PDT 24 63178785 ps
T109 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1228143712 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 22027312 ps
T1045 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2032502374 Aug 17 06:34:21 PM PDT 24 Aug 17 06:34:36 PM PDT 24 889626111 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1369137826 Aug 17 06:33:55 PM PDT 24 Aug 17 06:33:56 PM PDT 24 42820140 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2939284688 Aug 17 06:33:59 PM PDT 24 Aug 17 06:34:01 PM PDT 24 48065311 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1209293466 Aug 17 06:33:57 PM PDT 24 Aug 17 06:33:58 PM PDT 24 47314880 ps
T1048 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.151125792 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:06 PM PDT 24 46974534 ps
T1049 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1547900637 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 74816576 ps
T128 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.196843483 Aug 17 06:34:01 PM PDT 24 Aug 17 06:34:03 PM PDT 24 77086095 ps
T1050 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1643028991 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:09 PM PDT 24 32782979 ps
T1051 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4028788492 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:14 PM PDT 24 79471239 ps
T185 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2968547013 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:26 PM PDT 24 537928677 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4054237422 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:12 PM PDT 24 605807475 ps
T1053 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1931809187 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:09 PM PDT 24 107366143 ps
T1054 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1866090991 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 226032032 ps
T1055 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1896193038 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:12 PM PDT 24 43042600 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1269156367 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:13 PM PDT 24 451628537 ps
T114 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2581797231 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:10 PM PDT 24 227277520 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.627745542 Aug 17 06:34:01 PM PDT 24 Aug 17 06:34:04 PM PDT 24 108668422 ps
T1058 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.875901044 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:06 PM PDT 24 81855888 ps
T1059 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3143743434 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:11 PM PDT 24 137000869 ps
T1060 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3668223686 Aug 17 06:34:03 PM PDT 24 Aug 17 06:34:05 PM PDT 24 56620837 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1606068183 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 44471232 ps
T1062 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.961318779 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:13 PM PDT 24 135443995 ps
T1063 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.618097015 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:06 PM PDT 24 51214281 ps
T1064 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3486305062 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:11 PM PDT 24 15689124 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3201997321 Aug 17 06:33:59 PM PDT 24 Aug 17 06:34:01 PM PDT 24 61636749 ps
T111 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1530100037 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:14 PM PDT 24 387407036 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.14238548 Aug 17 06:34:03 PM PDT 24 Aug 17 06:34:07 PM PDT 24 656931575 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2327450850 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:14 PM PDT 24 47816158 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1258052762 Aug 17 06:33:51 PM PDT 24 Aug 17 06:33:54 PM PDT 24 375900994 ps
T180 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2536645854 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:14 PM PDT 24 84788009 ps
T115 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.810784851 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:11 PM PDT 24 304556617 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.379587414 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:42 PM PDT 24 1885696024 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2546716861 Aug 17 06:34:02 PM PDT 24 Aug 17 06:34:03 PM PDT 24 44051470 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2493387427 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:07 PM PDT 24 86846734 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1136413191 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:13 PM PDT 24 240127295 ps
T87 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2729124899 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 77186708 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.935094711 Aug 17 06:33:57 PM PDT 24 Aug 17 06:34:17 PM PDT 24 307117389 ps
T1073 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3456841903 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:10 PM PDT 24 23744615 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1834302442 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:14 PM PDT 24 57307095 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2249316409 Aug 17 06:33:56 PM PDT 24 Aug 17 06:34:17 PM PDT 24 5883714060 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1361007071 Aug 17 06:34:01 PM PDT 24 Aug 17 06:34:03 PM PDT 24 30515815 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2988588364 Aug 17 06:33:57 PM PDT 24 Aug 17 06:34:21 PM PDT 24 1241367197 ps
T1078 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.821167941 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:13 PM PDT 24 12040254 ps
T1079 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1374757669 Aug 17 06:34:25 PM PDT 24 Aug 17 06:34:26 PM PDT 24 77842648 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4243834587 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:10 PM PDT 24 222374459 ps
T186 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1036393320 Aug 17 06:34:03 PM PDT 24 Aug 17 06:34:10 PM PDT 24 200843766 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3479669759 Aug 17 06:34:00 PM PDT 24 Aug 17 06:34:09 PM PDT 24 1329088250 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2396837549 Aug 17 06:34:03 PM PDT 24 Aug 17 06:34:04 PM PDT 24 35967778 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2349680949 Aug 17 06:34:12 PM PDT 24 Aug 17 06:34:15 PM PDT 24 141164501 ps
T1084 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1094158093 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:11 PM PDT 24 151524820 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2538473120 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:07 PM PDT 24 136670392 ps
T1086 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.24007464 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:08 PM PDT 24 18206077 ps
T1087 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1940723362 Aug 17 06:34:01 PM PDT 24 Aug 17 06:34:07 PM PDT 24 44475365 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3770859707 Aug 17 06:34:03 PM PDT 24 Aug 17 06:34:03 PM PDT 24 18099713 ps
T1089 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.976500356 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:06 PM PDT 24 15422556 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4058420493 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:14 PM PDT 24 32768104 ps
T1091 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.208601296 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 135335125 ps
T1092 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3578543641 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:11 PM PDT 24 74716455 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2197670542 Aug 17 06:33:58 PM PDT 24 Aug 17 06:34:00 PM PDT 24 30543038 ps
T1094 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.336953977 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:13 PM PDT 24 14090550 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2153794466 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:24 PM PDT 24 610014890 ps
T1096 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2066643135 Aug 17 06:34:14 PM PDT 24 Aug 17 06:34:15 PM PDT 24 164361292 ps
T1097 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.641503653 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:10 PM PDT 24 242928526 ps
T1098 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.709467271 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:11 PM PDT 24 26290930 ps
T1099 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.742517644 Aug 17 06:33:58 PM PDT 24 Aug 17 06:34:00 PM PDT 24 78987926 ps
T1100 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1240389106 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:18 PM PDT 24 864859895 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1023847729 Aug 17 06:33:54 PM PDT 24 Aug 17 06:33:55 PM PDT 24 39658806 ps
T1102 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1509411122 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:13 PM PDT 24 37828794 ps
T181 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3700157857 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:35 PM PDT 24 1059688082 ps
T1103 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2223688242 Aug 17 06:33:55 PM PDT 24 Aug 17 06:33:56 PM PDT 24 94805292 ps
T1104 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2304766510 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:13 PM PDT 24 192345159 ps
T1105 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3596165534 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:11 PM PDT 24 18459156 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.822367799 Aug 17 06:34:02 PM PDT 24 Aug 17 06:34:04 PM PDT 24 59232081 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.917984116 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:07 PM PDT 24 41218480 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.319502029 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:11 PM PDT 24 46268491 ps
T182 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.135237316 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:27 PM PDT 24 1665915224 ps
T1109 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2032501495 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:12 PM PDT 24 43516526 ps
T1110 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3735412975 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:14 PM PDT 24 402220567 ps
T88 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.422914721 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:09 PM PDT 24 40353834 ps
T1111 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4214924551 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:06 PM PDT 24 13076845 ps
T187 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.288036946 Aug 17 06:34:02 PM PDT 24 Aug 17 06:34:18 PM PDT 24 711593324 ps
T1112 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.256903215 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:08 PM PDT 24 184826616 ps
T188 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.328979924 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:14 PM PDT 24 298076280 ps
T1113 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2803502044 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:10 PM PDT 24 44434008 ps
T89 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1920509284 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:10 PM PDT 24 80492299 ps
T1114 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3198570794 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:06 PM PDT 24 39543748 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3868879353 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:06 PM PDT 24 40786283 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2569187953 Aug 17 06:33:52 PM PDT 24 Aug 17 06:33:53 PM PDT 24 34295008 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1236713802 Aug 17 06:33:53 PM PDT 24 Aug 17 06:33:58 PM PDT 24 765759274 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3404704747 Aug 17 06:33:57 PM PDT 24 Aug 17 06:34:04 PM PDT 24 530715030 ps
T1118 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4185624544 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:07 PM PDT 24 17564697 ps
T1119 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.418621834 Aug 17 06:34:11 PM PDT 24 Aug 17 06:34:15 PM PDT 24 306959984 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.29656334 Aug 17 06:34:10 PM PDT 24 Aug 17 06:34:12 PM PDT 24 338626372 ps
T1121 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.814561780 Aug 17 06:34:06 PM PDT 24 Aug 17 06:34:10 PM PDT 24 56582337 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3095295747 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:05 PM PDT 24 28447474 ps
T1123 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1980781167 Aug 17 06:34:08 PM PDT 24 Aug 17 06:34:11 PM PDT 24 189304890 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.346025223 Aug 17 06:34:03 PM PDT 24 Aug 17 06:34:05 PM PDT 24 611721744 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4140714984 Aug 17 06:34:09 PM PDT 24 Aug 17 06:34:13 PM PDT 24 109208325 ps
T1126 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1732977451 Aug 17 06:34:05 PM PDT 24 Aug 17 06:34:09 PM PDT 24 233855889 ps
T1127 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1655883055 Aug 17 06:34:07 PM PDT 24 Aug 17 06:34:09 PM PDT 24 120845271 ps
T1128 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.58193241 Aug 17 06:33:58 PM PDT 24 Aug 17 06:33:59 PM PDT 24 21138812 ps
T1129 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2499652813 Aug 17 06:34:04 PM PDT 24 Aug 17 06:34:06 PM PDT 24 327318866 ps
T1130 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3606903557 Aug 17 06:34:13 PM PDT 24 Aug 17 06:34:14 PM PDT 24 11507257 ps
T1131 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2956541786 Aug 17 06:34:02 PM PDT 24 Aug 17 06:34:10 PM PDT 24 353752257 ps


Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2178834214
Short name T1
Test name
Test status
Simulation time 5367328963 ps
CPU time 56.79 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 254040 kb
Host smart-8a286bee-bbdb-4a01-b36d-bbc5e92e555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178834214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2178834214
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/35.spi_device_tpm_all.2288503323
Short name T3
Test name
Test status
Simulation time 8675784720 ps
CPU time 11.35 seconds
Started Aug 17 06:36:39 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 221524 kb
Host smart-9425ee18-0cc1-43f4-87d4-1b2947d73161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288503323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2288503323
Directory /workspace/35.spi_device_tpm_all/latest


Test location /workspace/coverage/default/41.spi_device_stress_all.3541788889
Short name T24
Test name
Test status
Simulation time 120295944104 ps
CPU time 638.76 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:47:34 PM PDT 24
Peak memory 274400 kb
Host smart-a99945f6-69ea-4d43-8293-c6f0c2503221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541788889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3541788889
Directory /workspace/41.spi_device_stress_all/latest


Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3481788128
Short name T50
Test name
Test status
Simulation time 41747574450 ps
CPU time 117.87 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 264972 kb
Host smart-49022500-033c-4087-a5d6-bc7e90dea752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481788128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3481788128
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1659914910
Short name T67
Test name
Test status
Simulation time 138183516 ps
CPU time 3.35 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 216896 kb
Host smart-0772e243-115c-4ed9-9809-cf43ce2f47b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659914910 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1659914910
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/default/42.spi_device_stress_all.2370262475
Short name T20
Test name
Test status
Simulation time 13193836134 ps
CPU time 209.42 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:40:24 PM PDT 24
Peak memory 274524 kb
Host smart-66872651-e38b-4d56-9d99-cdb4a30da22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370262475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2370262475
Directory /workspace/42.spi_device_stress_all/latest


Test location /workspace/coverage/default/0.spi_device_ram_cfg.901015712
Short name T69
Test name
Test status
Simulation time 18919317 ps
CPU time 0.76 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 216760 kb
Host smart-00f6697a-a7e0-4558-a4a8-c2e59b8a9b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901015712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.901015712
Directory /workspace/0.spi_device_ram_cfg/latest


Test location /workspace/coverage/default/19.spi_device_stress_all.3445159844
Short name T203
Test name
Test status
Simulation time 11705868014 ps
CPU time 235.79 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:39:51 PM PDT 24
Peak memory 286888 kb
Host smart-1acaf75c-1881-4e42-ba5f-9487d6999d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445159844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3445159844
Directory /workspace/19.spi_device_stress_all/latest


Test location /workspace/coverage/default/33.spi_device_stress_all.706652486
Short name T33
Test name
Test status
Simulation time 116419461947 ps
CPU time 596.66 seconds
Started Aug 17 06:36:33 PM PDT 24
Finished Aug 17 06:46:29 PM PDT 24
Peak memory 268320 kb
Host smart-9e2fb3e3-656a-4b3f-a0d6-cfbdb9cdaf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706652486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.706652486
Directory /workspace/33.spi_device_stress_all/latest


Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3145641609
Short name T43
Test name
Test status
Simulation time 130940903020 ps
CPU time 133.25 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 254796 kb
Host smart-5a133082-b40f-4fee-8d9a-60dbaf9ced31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145641609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3145641609
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2239375094
Short name T103
Test name
Test status
Simulation time 859789935 ps
CPU time 22.4 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:25 PM PDT 24
Peak memory 215104 kb
Host smart-82575e56-8177-4778-8164-e46fff8946a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239375094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2239375094
Directory /workspace/10.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/36.spi_device_stress_all.1312881101
Short name T198
Test name
Test status
Simulation time 23336484473 ps
CPU time 344.28 seconds
Started Aug 17 06:36:39 PM PDT 24
Finished Aug 17 06:42:23 PM PDT 24
Peak memory 264936 kb
Host smart-7c8bc6dc-1f6c-476d-81a9-111ab2a9d82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312881101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1312881101
Directory /workspace/36.spi_device_stress_all/latest


Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4224373470
Short name T39
Test name
Test status
Simulation time 295321301 ps
CPU time 3.32 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 220152 kb
Host smart-37f1890b-9d98-472d-810e-c05afc6721c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4224373470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4224373470
Directory /workspace/4.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/1.spi_device_alert_test.3852831508
Short name T347
Test name
Test status
Simulation time 23592970 ps
CPU time 0.74 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 206288 kb
Host smart-b3e8ac48-47b5-4c59-adc8-9581e23eb3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852831508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
852831508
Directory /workspace/1.spi_device_alert_test/latest


Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2497735069
Short name T47
Test name
Test status
Simulation time 14495682557 ps
CPU time 102.88 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:36:44 PM PDT 24
Peak memory 266124 kb
Host smart-bd03dc06-5fb0-47a1-a396-e469c88e137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497735069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2497735069
Directory /workspace/10.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3017421519
Short name T118
Test name
Test status
Simulation time 139977200 ps
CPU time 2.4 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215072 kb
Host smart-40a78add-f91f-4e8f-8465-26d7c5fe8a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017421519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3017421519
Directory /workspace/14.spi_device_csr_rw/latest


Test location /workspace/coverage/default/7.spi_device_stress_all.2773646365
Short name T22
Test name
Test status
Simulation time 40285397867 ps
CPU time 378.22 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:41:28 PM PDT 24
Peak memory 258420 kb
Host smart-4531de7f-a41f-4812-9b04-83747acbee88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773646365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2773646365
Directory /workspace/7.spi_device_stress_all/latest


Test location /workspace/coverage/default/40.spi_device_stress_all.2698606173
Short name T78
Test name
Test status
Simulation time 33507398584 ps
CPU time 174.14 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:39:48 PM PDT 24
Peak memory 257660 kb
Host smart-0486f208-6d38-44af-ad90-2a64710a0e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698606173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2698606173
Directory /workspace/40.spi_device_stress_all/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.324107159
Short name T99
Test name
Test status
Simulation time 1092981041 ps
CPU time 5.26 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215268 kb
Host smart-c0aa9a6e-0cb6-45fa-8360-18e717a44abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324107159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.324107159
Directory /workspace/5.spi_device_tl_errors/latest


Test location /workspace/coverage/default/10.spi_device_stress_all.122114026
Short name T202
Test name
Test status
Simulation time 91068175028 ps
CPU time 623.52 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:45:30 PM PDT 24
Peak memory 266596 kb
Host smart-9bd59191-8f29-4066-8002-75437b7e6af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122114026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.122114026
Directory /workspace/10.spi_device_stress_all/latest


Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.563221872
Short name T231
Test name
Test status
Simulation time 26154764473 ps
CPU time 321.68 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:41:21 PM PDT 24
Peak memory 270652 kb
Host smart-9b998d3e-4289-4063-9da2-3e141abd64e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563221872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.563221872
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3690809757
Short name T237
Test name
Test status
Simulation time 33113491253 ps
CPU time 275.78 seconds
Started Aug 17 06:36:48 PM PDT 24
Finished Aug 17 06:41:24 PM PDT 24
Peak memory 257096 kb
Host smart-4550d45a-8e72-4d1c-a023-883580e6f109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690809757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3690809757
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/0.spi_device_sec_cm.3565976269
Short name T71
Test name
Test status
Simulation time 86692990 ps
CPU time 1.17 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 237136 kb
Host smart-61e2a981-e587-4d3a-91a5-79ecfc63a361
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565976269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3565976269
Directory /workspace/0.spi_device_sec_cm/latest


Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.692284102
Short name T349
Test name
Test status
Simulation time 1458117201 ps
CPU time 3.38 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 217216 kb
Host smart-954b8a42-2f4c-4acb-8341-53165b1d15ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692284102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.692284102
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/40.spi_device_flash_all.1170219439
Short name T233
Test name
Test status
Simulation time 45574920822 ps
CPU time 93.8 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:38:26 PM PDT 24
Peak memory 265820 kb
Host smart-1e8890c1-b58d-4e63-98f1-d8cf6490f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170219439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1170219439
Directory /workspace/40.spi_device_flash_all/latest


Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3337227451
Short name T201
Test name
Test status
Simulation time 237436299644 ps
CPU time 605.65 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:45:19 PM PDT 24
Peak memory 257288 kb
Host smart-5645d5fa-a898-4da9-8a60-93efc62e1e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337227451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3337227451
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/31.spi_device_flash_mode.2054158979
Short name T315
Test name
Test status
Simulation time 8364743712 ps
CPU time 30.7 seconds
Started Aug 17 06:36:14 PM PDT 24
Finished Aug 17 06:36:45 PM PDT 24
Peak memory 252508 kb
Host smart-1f06b889-5baa-4af3-b497-6bc27041bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054158979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2054158979
Directory /workspace/31.spi_device_flash_mode/latest


Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2069781175
Short name T204
Test name
Test status
Simulation time 177841135650 ps
CPU time 410.79 seconds
Started Aug 17 06:35:40 PM PDT 24
Finished Aug 17 06:42:31 PM PDT 24
Peak memory 259740 kb
Host smart-cac2d2cd-c569-4236-8d52-5ba0f9fec70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069781175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2069781175
Directory /workspace/15.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4126630493
Short name T271
Test name
Test status
Simulation time 117842795762 ps
CPU time 213.02 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:39:29 PM PDT 24
Peak memory 266496 kb
Host smart-51ad03db-1cdd-4123-af75-2b46bf3c0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126630493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4126630493
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2304766510
Short name T1104
Test name
Test status
Simulation time 192345159 ps
CPU time 4.98 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215288 kb
Host smart-eb08b12d-6f71-4fd2-88f2-45923fbfdd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304766510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2304766510
Directory /workspace/10.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3362061008
Short name T183
Test name
Test status
Simulation time 418874852 ps
CPU time 12.15 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:22 PM PDT 24
Peak memory 215544 kb
Host smart-36f40fda-30df-42e1-9f83-790a81db1240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362061008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3362061008
Directory /workspace/18.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/13.spi_device_tpm_all.2165555320
Short name T342
Test name
Test status
Simulation time 10268940422 ps
CPU time 22.52 seconds
Started Aug 17 06:35:37 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 217276 kb
Host smart-b7129806-fc11-4618-a234-5dc2820932b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165555320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2165555320
Directory /workspace/13.spi_device_tpm_all/latest


Test location /workspace/coverage/default/1.spi_device_tpm_all.4059114621
Short name T91
Test name
Test status
Simulation time 7733316880 ps
CPU time 17.74 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:16 PM PDT 24
Peak memory 217420 kb
Host smart-63c81629-e044-49c8-8a7c-eb3edfa3e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059114621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4059114621
Directory /workspace/1.spi_device_tpm_all/latest


Test location /workspace/coverage/default/11.spi_device_mailbox.4285085913
Short name T14
Test name
Test status
Simulation time 621447324 ps
CPU time 12.19 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:18 PM PDT 24
Peak memory 236084 kb
Host smart-2046dc76-6272-42bd-91b6-3294dc23a552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285085913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4285085913
Directory /workspace/11.spi_device_mailbox/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.288036946
Short name T187
Test name
Test status
Simulation time 711593324 ps
CPU time 15.66 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 215100 kb
Host smart-5217f3b7-12a1-4f1f-a7e1-173619797c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288036946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.288036946
Directory /workspace/3.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/14.spi_device_flash_all.4176218652
Short name T298
Test name
Test status
Simulation time 2892413692 ps
CPU time 66.98 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 255212 kb
Host smart-9547ae05-b2eb-43f5-b5fe-682f8bad4897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176218652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4176218652
Directory /workspace/14.spi_device_flash_all/latest


Test location /workspace/coverage/default/18.spi_device_flash_all.1242581209
Short name T1006
Test name
Test status
Simulation time 30782036795 ps
CPU time 101.78 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 255624 kb
Host smart-475c4083-3eb2-4734-9726-b3defb4dd1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242581209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1242581209
Directory /workspace/18.spi_device_flash_all/latest


Test location /workspace/coverage/default/24.spi_device_stress_all.3569377436
Short name T839
Test name
Test status
Simulation time 21003151484 ps
CPU time 102.12 seconds
Started Aug 17 06:36:04 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 263700 kb
Host smart-cdd56aa1-253e-4195-ba0f-e5775b4511b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569377436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3569377436
Directory /workspace/24.spi_device_stress_all/latest


Test location /workspace/coverage/default/49.spi_device_flash_all.2819698846
Short name T313
Test name
Test status
Simulation time 81026724554 ps
CPU time 287.55 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:41:45 PM PDT 24
Peak memory 255236 kb
Host smart-ec9e61f4-c3b8-428a-9e33-6de7ec9c24a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819698846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2819698846
Directory /workspace/49.spi_device_flash_all/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4081865113
Short name T184
Test name
Test status
Simulation time 209237381 ps
CPU time 12.7 seconds
Started Aug 17 06:34:18 PM PDT 24
Finished Aug 17 06:34:30 PM PDT 24
Peak memory 216612 kb
Host smart-4eb46e1c-2971-42eb-b807-db254ae73187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081865113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4081865113
Directory /workspace/16.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1210138676
Short name T720
Test name
Test status
Simulation time 984771614 ps
CPU time 10.01 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 233580 kb
Host smart-5a823326-53a3-414e-ba9e-8ec22ad9dd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210138676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1210138676
Directory /workspace/1.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3966675284
Short name T303
Test name
Test status
Simulation time 9474857830 ps
CPU time 67.32 seconds
Started Aug 17 06:35:25 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 240672 kb
Host smart-57b91a31-0529-412e-8d69-b1e7d165c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966675284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3966675284
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/10.spi_device_flash_mode.3657467791
Short name T676
Test name
Test status
Simulation time 995119948 ps
CPU time 5.06 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 233576 kb
Host smart-216a9054-7fa5-443a-a4f5-efa4c0746ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657467791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3657467791
Directory /workspace/10.spi_device_flash_mode/latest


Test location /workspace/coverage/default/11.spi_device_flash_mode.3540549824
Short name T326
Test name
Test status
Simulation time 519323817 ps
CPU time 10.69 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 225352 kb
Host smart-09185ea0-dfb4-4da8-8e81-243eeda90bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540549824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3540549824
Directory /workspace/11.spi_device_flash_mode/latest


Test location /workspace/coverage/default/14.spi_device_stress_all.4087906959
Short name T129
Test name
Test status
Simulation time 32912570120 ps
CPU time 156.26 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:38:26 PM PDT 24
Peak memory 250224 kb
Host smart-640b0a42-82a9-455b-a054-f1ecd61fc464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087906959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4087906959
Directory /workspace/14.spi_device_stress_all/latest


Test location /workspace/coverage/default/15.spi_device_flash_all.91405691
Short name T297
Test name
Test status
Simulation time 23931007694 ps
CPU time 180.99 seconds
Started Aug 17 06:35:48 PM PDT 24
Finished Aug 17 06:38:49 PM PDT 24
Peak memory 257028 kb
Host smart-a16a5aaa-b701-48ed-9ca1-3757bc036856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91405691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.91405691
Directory /workspace/15.spi_device_flash_all/latest


Test location /workspace/coverage/default/16.spi_device_flash_all.2296003862
Short name T197
Test name
Test status
Simulation time 210888395664 ps
CPU time 423.39 seconds
Started Aug 17 06:35:50 PM PDT 24
Finished Aug 17 06:42:53 PM PDT 24
Peak memory 265700 kb
Host smart-222ab092-102c-4a81-b6ce-8ebee6632198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296003862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2296003862
Directory /workspace/16.spi_device_flash_all/latest


Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3235522959
Short name T219
Test name
Test status
Simulation time 62560716058 ps
CPU time 135.09 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:38:10 PM PDT 24
Peak memory 251344 kb
Host smart-d975ec8d-01ec-4c1f-9e1b-cfc7cdc64d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235522959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3235522959
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1579296059
Short name T48
Test name
Test status
Simulation time 95759034018 ps
CPU time 131.48 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 252712 kb
Host smart-520ad806-343c-4fba-bb67-d66f968ae7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579296059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1579296059
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.710799956
Short name T305
Test name
Test status
Simulation time 39377041774 ps
CPU time 198.93 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:39:15 PM PDT 24
Peak memory 266480 kb
Host smart-ebc02039-eeb1-4760-bd70-375c083ab4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710799956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.710799956
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/39.spi_device_flash_mode.4294846400
Short name T321
Test name
Test status
Simulation time 527909506 ps
CPU time 8.16 seconds
Started Aug 17 06:36:47 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 233500 kb
Host smart-0d28aaef-ad92-41a5-818b-91f7a8653b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294846400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4294846400
Directory /workspace/39.spi_device_flash_mode/latest


Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3923711267
Short name T307
Test name
Test status
Simulation time 156223131874 ps
CPU time 208.41 seconds
Started Aug 17 06:36:43 PM PDT 24
Finished Aug 17 06:40:11 PM PDT 24
Peak memory 268456 kb
Host smart-20f68bac-2f8a-401f-8a0d-4bf01ca09317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923711267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3923711267
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.858483573
Short name T248
Test name
Test status
Simulation time 20661937666 ps
CPU time 22.61 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 236036 kb
Host smart-26baf73a-381f-4f47-9364-176666c43189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858483573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.858483573
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1920509284
Short name T89
Test name
Test status
Simulation time 80492299 ps
CPU time 0.99 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 206520 kb
Host smart-3ca22d4f-5dcb-4f87-af20-d8087f9c902b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920509284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1920509284
Directory /workspace/0.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1240389106
Short name T1100
Test name
Test status
Simulation time 864859895 ps
CPU time 5.32 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 215220 kb
Host smart-0b266698-3502-404d-9fde-b4c1471e3f62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240389106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1240389106
Directory /workspace/14.spi_device_tl_errors/latest


Test location /workspace/coverage/default/47.spi_device_stress_all.69108861
Short name T41
Test name
Test status
Simulation time 46325279456 ps
CPU time 190.82 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:40:05 PM PDT 24
Peak memory 264404 kb
Host smart-f7a89d2a-757e-438b-9643-4c12fc8323e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69108861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress
_all.69108861
Directory /workspace/47.spi_device_stress_all/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.935094711
Short name T1072
Test name
Test status
Simulation time 307117389 ps
CPU time 19.7 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 215176 kb
Host smart-10a95211-95d3-4169-bfe4-b1b3c4108327
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935094711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.935094711
Directory /workspace/0.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.379587414
Short name T1068
Test name
Test status
Simulation time 1885696024 ps
CPU time 37.44 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:42 PM PDT 24
Peak memory 206876 kb
Host smart-829d2610-6d98-401a-ac74-4ba5e1701ca7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379587414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.379587414
Directory /workspace/0.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.256903215
Short name T1112
Test name
Test status
Simulation time 184826616 ps
CPU time 4.27 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 218560 kb
Host smart-d29fb8ac-f851-4320-adb7-babcc8a5847e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256903215 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.256903215
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.346025223
Short name T1124
Test name
Test status
Simulation time 611721744 ps
CPU time 2.03 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:05 PM PDT 24
Peak memory 214972 kb
Host smart-b5546cb2-26d2-4ec4-af18-dc067ab2ff86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346025223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.346025223
Directory /workspace/0.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.846685798
Short name T1012
Test name
Test status
Simulation time 14740804 ps
CPU time 0.71 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 203948 kb
Host smart-c140c6c3-f019-4953-b0b2-a31477cc0b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846685798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.846685798
Directory /workspace/0.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.822367799
Short name T1106
Test name
Test status
Simulation time 59232081 ps
CPU time 1.26 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 215092 kb
Host smart-c1a54b4c-f2dc-49c0-91b3-546e423c55ab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822367799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.822367799
Directory /workspace/0.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.641565397
Short name T1020
Test name
Test status
Simulation time 34234489 ps
CPU time 0.66 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:33:57 PM PDT 24
Peak memory 203496 kb
Host smart-57f73ad6-920b-4d65-aa03-d4696cfd7eb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641565397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.641565397
Directory /workspace/0.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1180593706
Short name T1029
Test name
Test status
Simulation time 357565835 ps
CPU time 2.8 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:34:00 PM PDT 24
Peak memory 215020 kb
Host smart-f1e35e8b-7d67-4e10-bcb8-9409c488a74f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180593706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1180593706
Directory /workspace/0.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1228143712
Short name T109
Test name
Test status
Simulation time 22027312 ps
CPU time 1.47 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215420 kb
Host smart-70201ec4-5b67-420e-a2d3-4bb51afe9465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228143712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
228143712
Directory /workspace/0.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3404704747
Short name T1117
Test name
Test status
Simulation time 530715030 ps
CPU time 7.26 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 222284 kb
Host smart-40920592-fa7a-4447-9d29-a6d30bbe3591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404704747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3404704747
Directory /workspace/0.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3479669759
Short name T1081
Test name
Test status
Simulation time 1329088250 ps
CPU time 8.55 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 206716 kb
Host smart-2786b1d1-02a9-4afa-a69f-6421c799d492
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479669759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3479669759
Directory /workspace/1.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3294750360
Short name T127
Test name
Test status
Simulation time 2629448026 ps
CPU time 25.83 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:28 PM PDT 24
Peak memory 206904 kb
Host smart-60cb77b6-314f-4a20-a316-bfd14fb7552d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294750360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3294750360
Directory /workspace/1.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.422914721
Short name T88
Test name
Test status
Simulation time 40353834 ps
CPU time 1.52 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 206856 kb
Host smart-aca84e95-92ef-4191-aaee-8d6211ac28df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422914721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.422914721
Directory /workspace/1.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3201997321
Short name T1065
Test name
Test status
Simulation time 61636749 ps
CPU time 1.8 seconds
Started Aug 17 06:33:59 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 215192 kb
Host smart-04ea4c84-8556-4708-b918-75cde58f165a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201997321 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3201997321
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.742517644
Short name T1099
Test name
Test status
Simulation time 78987926 ps
CPU time 2.07 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:34:00 PM PDT 24
Peak memory 215052 kb
Host smart-c42eb3c7-730c-43da-a019-8dd4e3268090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742517644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.742517644
Directory /workspace/1.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2569187953
Short name T1115
Test name
Test status
Simulation time 34295008 ps
CPU time 0.71 seconds
Started Aug 17 06:33:52 PM PDT 24
Finished Aug 17 06:33:53 PM PDT 24
Peak memory 203728 kb
Host smart-04dc2280-a542-4049-99ae-4e5693a96e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569187953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
569187953
Directory /workspace/1.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1023847729
Short name T1101
Test name
Test status
Simulation time 39658806 ps
CPU time 1.32 seconds
Started Aug 17 06:33:54 PM PDT 24
Finished Aug 17 06:33:55 PM PDT 24
Peak memory 215116 kb
Host smart-6727da1b-71ef-4ab1-bf93-d21365415ea6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023847729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1023847729
Directory /workspace/1.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3837323883
Short name T1026
Test name
Test status
Simulation time 11225021 ps
CPU time 0.72 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 203580 kb
Host smart-c5ed26d7-ef3b-4341-b087-ec2b80efb9e6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837323883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3837323883
Directory /workspace/1.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2197670542
Short name T1093
Test name
Test status
Simulation time 30543038 ps
CPU time 1.95 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:34:00 PM PDT 24
Peak memory 215024 kb
Host smart-988f13e0-4afc-46ba-8a06-54796917a834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197670542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2197670542
Directory /workspace/1.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2182454965
Short name T110
Test name
Test status
Simulation time 177504192 ps
CPU time 4.15 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215272 kb
Host smart-2ecd72d1-289d-4726-b31f-18d0a47e172d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182454965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
182454965
Directory /workspace/1.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3647553833
Short name T100
Test name
Test status
Simulation time 447492372 ps
CPU time 6.68 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 215148 kb
Host smart-3162fdd8-45fd-4ab7-8cc0-e5a1282e2b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647553833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3647553833
Directory /workspace/1.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1655883055
Short name T1127
Test name
Test status
Simulation time 120845271 ps
CPU time 1.79 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 216256 kb
Host smart-52da4254-5f51-400a-a1cf-0dc9173c5404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655883055 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1655883055
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.816964840
Short name T125
Test name
Test status
Simulation time 148914678 ps
CPU time 1.31 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:02 PM PDT 24
Peak memory 206812 kb
Host smart-1f9a7793-7c81-4370-a4b6-03f680efe83c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816964840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.816964840
Directory /workspace/10.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1940723362
Short name T1087
Test name
Test status
Simulation time 44475365 ps
CPU time 0.74 seconds
Started Aug 17 06:34:01 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 203808 kb
Host smart-c8897b76-b936-4ab2-ad39-89b8e91c66cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940723362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1940723362
Directory /workspace/10.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1622688085
Short name T153
Test name
Test status
Simulation time 138049004 ps
CPU time 1.82 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 215080 kb
Host smart-c70f17dd-95be-4fb6-a3c7-e8382cb1a172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622688085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1622688085
Directory /workspace/10.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3208231608
Short name T104
Test name
Test status
Simulation time 23573321 ps
CPU time 1.69 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 215584 kb
Host smart-3f9271f9-e359-4609-b61e-ef279e9f0509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208231608 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3208231608
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2609035616
Short name T144
Test name
Test status
Simulation time 73344912 ps
CPU time 1.23 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 206812 kb
Host smart-79f0a70a-5084-4db8-b676-6bad52dc8cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609035616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2609035616
Directory /workspace/11.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1929588095
Short name T1025
Test name
Test status
Simulation time 34404573 ps
CPU time 0.68 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 203712 kb
Host smart-42b2a739-2ae2-4cca-b3d5-38c1ccb55e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929588095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1929588095
Directory /workspace/11.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4140714984
Short name T1125
Test name
Test status
Simulation time 109208325 ps
CPU time 2.87 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215016 kb
Host smart-2f45b951-d444-40b3-bfaa-42a7ea52aa7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140714984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4140714984
Directory /workspace/11.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2289263116
Short name T107
Test name
Test status
Simulation time 283879142 ps
CPU time 5.51 seconds
Started Aug 17 06:33:59 PM PDT 24
Finished Aug 17 06:34:05 PM PDT 24
Peak memory 215208 kb
Host smart-3d8f9111-8a33-483c-9787-d9c8f9310799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289263116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2289263116
Directory /workspace/11.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.338445140
Short name T156
Test name
Test status
Simulation time 1392864110 ps
CPU time 8.74 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215740 kb
Host smart-c40d7f00-e0ad-46e9-8893-0a644f9250ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338445140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.338445140
Directory /workspace/11.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.172513800
Short name T1043
Test name
Test status
Simulation time 479885534 ps
CPU time 3.44 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 217360 kb
Host smart-f740b9de-9feb-4e81-87b4-c3427cc4fb39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172513800 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.172513800
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3143743434
Short name T1059
Test name
Test status
Simulation time 137000869 ps
CPU time 2.49 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 215092 kb
Host smart-c24c263b-ff32-41ea-b14e-7234d7fb50ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143743434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3143743434
Directory /workspace/12.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.685726019
Short name T1021
Test name
Test status
Simulation time 14193939 ps
CPU time 0.78 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 203740 kb
Host smart-f0cceef0-1287-41c0-b356-f47ab100cce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685726019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.685726019
Directory /workspace/12.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1094158093
Short name T1084
Test name
Test status
Simulation time 151524820 ps
CPU time 3.54 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 215152 kb
Host smart-3009c3cf-cf77-41a4-b7a0-4504edf7320d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094158093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1094158093
Directory /workspace/12.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.29656334
Short name T1120
Test name
Test status
Simulation time 338626372 ps
CPU time 2.11 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 207040 kb
Host smart-97823e86-8a4f-4b33-9bb3-9e18319915d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29656334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.29656334
Directory /workspace/12.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2032502374
Short name T1045
Test name
Test status
Simulation time 889626111 ps
CPU time 14.97 seconds
Started Aug 17 06:34:21 PM PDT 24
Finished Aug 17 06:34:36 PM PDT 24
Peak memory 215212 kb
Host smart-97915d19-8c91-415e-b461-e3d5ad9d9cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032502374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2032502374
Directory /workspace/12.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.875901044
Short name T1058
Test name
Test status
Simulation time 81855888 ps
CPU time 1.21 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 215052 kb
Host smart-e780cdbc-bbca-4366-9bf4-e7b83d979570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875901044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.875901044
Directory /workspace/13.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.24007464
Short name T1086
Test name
Test status
Simulation time 18206077 ps
CPU time 0.75 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 203752 kb
Host smart-9a94ace6-afab-425b-813b-80e4d16cd109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24007464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.24007464
Directory /workspace/13.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2327450850
Short name T1066
Test name
Test status
Simulation time 47816158 ps
CPU time 3.05 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 206844 kb
Host smart-0876e51c-5dfe-4297-87c9-12b2c01c7bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327450850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2327450850
Directory /workspace/13.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1530100037
Short name T111
Test name
Test status
Simulation time 387407036 ps
CPU time 4.05 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215284 kb
Host smart-dff63646-badc-4407-9c92-6772b0aa20fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530100037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1530100037
Directory /workspace/13.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3077602581
Short name T101
Test name
Test status
Simulation time 408102135 ps
CPU time 6.7 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 215168 kb
Host smart-da2d5194-13ff-472b-b7f4-a66f97d65be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077602581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3077602581
Directory /workspace/13.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1840841636
Short name T152
Test name
Test status
Simulation time 229916920 ps
CPU time 1.69 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215288 kb
Host smart-0e6f091c-2c4b-4a94-9084-7ec20476229f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840841636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1840841636
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1643028991
Short name T1050
Test name
Test status
Simulation time 32782979 ps
CPU time 0.76 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 204060 kb
Host smart-ad59bb7f-a62f-43d0-a073-0d015670b701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643028991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1643028991
Directory /workspace/14.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3735412975
Short name T1110
Test name
Test status
Simulation time 402220567 ps
CPU time 2.89 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215012 kb
Host smart-3996e2c8-d3dc-49e1-a0c9-a27f7f81d64b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735412975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3735412975
Directory /workspace/14.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3197195779
Short name T150
Test name
Test status
Simulation time 571123989 ps
CPU time 7.82 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 215348 kb
Host smart-c342da25-4737-41fe-a1d7-324f5567b422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197195779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3197195779
Directory /workspace/14.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.639838390
Short name T1041
Test name
Test status
Simulation time 197465491 ps
CPU time 3.86 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 217768 kb
Host smart-8e26c670-3629-4a58-b94e-88bc60203b0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639838390 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.639838390
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1498098098
Short name T122
Test name
Test status
Simulation time 86026986 ps
CPU time 2.17 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215004 kb
Host smart-0e85f135-252a-47d3-ab2b-e95ea9830f9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498098098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1498098098
Directory /workspace/15.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4028788492
Short name T1051
Test name
Test status
Simulation time 79471239 ps
CPU time 0.7 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 203572 kb
Host smart-6334d96f-859a-4fa2-8c08-001071a35214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028788492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4028788492
Directory /workspace/15.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.618097015
Short name T1063
Test name
Test status
Simulation time 51214281 ps
CPU time 1.59 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 215088 kb
Host smart-a7446069-f173-489e-b733-390e7599308d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618097015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.618097015
Directory /workspace/15.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.14238548
Short name T113
Test name
Test status
Simulation time 656931575 ps
CPU time 3.94 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 215336 kb
Host smart-756ac5ca-afc7-47a5-bede-6a475b7e5482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14238548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.14238548
Directory /workspace/15.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3700157857
Short name T181
Test name
Test status
Simulation time 1059688082 ps
CPU time 22.32 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:35 PM PDT 24
Peak memory 223384 kb
Host smart-404a26ee-1190-423d-9808-487abb5e86b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700157857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3700157857
Directory /workspace/15.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1236863932
Short name T1033
Test name
Test status
Simulation time 133694120 ps
CPU time 2.57 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 216396 kb
Host smart-5e0bab0c-baca-4cd2-9162-5b589cee1597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236863932 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1236863932
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3668223686
Short name T1060
Test name
Test status
Simulation time 56620837 ps
CPU time 2.07 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:05 PM PDT 24
Peak memory 215116 kb
Host smart-8ec80a75-0b4f-4416-8d11-d31d735dae7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668223686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3668223686
Directory /workspace/16.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1900164303
Short name T1028
Test name
Test status
Simulation time 69491433 ps
CPU time 0.7 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 203748 kb
Host smart-976de182-548a-4ec0-8aff-edbe8c6d91cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900164303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1900164303
Directory /workspace/16.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2349680949
Short name T1083
Test name
Test status
Simulation time 141164501 ps
CPU time 3.1 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 214884 kb
Host smart-e1969e84-3293-47ab-90af-9e526010cb2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349680949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2349680949
Directory /workspace/16.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.271163372
Short name T102
Test name
Test status
Simulation time 1558476037 ps
CPU time 5.41 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:18 PM PDT 24
Peak memory 215208 kb
Host smart-0a5cecca-6f77-42da-a728-98d047b5f8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271163372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.271163372
Directory /workspace/16.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1107302612
Short name T65
Test name
Test status
Simulation time 53078325 ps
CPU time 1.96 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 215076 kb
Host smart-5fb44199-5c4f-4e1b-8088-18668d3efa30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107302612 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1107302612
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.196843483
Short name T128
Test name
Test status
Simulation time 77086095 ps
CPU time 2.13 seconds
Started Aug 17 06:34:01 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 215064 kb
Host smart-86182d56-916e-4611-8926-bf24957c9861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196843483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.196843483
Directory /workspace/17.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1499279282
Short name T1032
Test name
Test status
Simulation time 17762827 ps
CPU time 0.76 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 204056 kb
Host smart-535652e8-00b1-41a0-a9d5-bf15b3882efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499279282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1499279282
Directory /workspace/17.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1136413191
Short name T1071
Test name
Test status
Simulation time 240127295 ps
CPU time 3.61 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215052 kb
Host smart-0f416479-76af-4814-ab21-68fe6256e972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136413191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1136413191
Directory /workspace/17.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2991926360
Short name T106
Test name
Test status
Simulation time 92896429 ps
CPU time 1.56 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 216304 kb
Host smart-556c4c7c-c794-4d67-aaaf-a018c95d4079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991926360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2991926360
Directory /workspace/17.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2968547013
Short name T185
Test name
Test status
Simulation time 537928677 ps
CPU time 13.15 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:26 PM PDT 24
Peak memory 215360 kb
Host smart-6d38f7bb-c6b0-4985-beb5-59b4e4f51906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968547013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2968547013
Directory /workspace/17.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.418621834
Short name T1119
Test name
Test status
Simulation time 306959984 ps
CPU time 3.72 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 218252 kb
Host smart-294ff122-31ff-42db-ab22-61f4c4c9af28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418621834 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.418621834
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2499652813
Short name T1129
Test name
Test status
Simulation time 327318866 ps
CPU time 1.87 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 215068 kb
Host smart-4e19ccf1-b1ab-4706-98c2-f00155a6f427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499652813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2499652813
Directory /workspace/18.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3456841903
Short name T1073
Test name
Test status
Simulation time 23744615 ps
CPU time 0.72 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 204004 kb
Host smart-a40a2a7a-f9a7-4d7e-ba18-fcdb5b6c9055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456841903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3456841903
Directory /workspace/18.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1468785224
Short name T143
Test name
Test status
Simulation time 62793907 ps
CPU time 3.92 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215160 kb
Host smart-41226506-301a-49db-8937-ec77d23b6e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468785224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1468785224
Directory /workspace/18.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.319502029
Short name T1108
Test name
Test status
Simulation time 46268491 ps
CPU time 2.82 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 215272 kb
Host smart-c82cd782-9e10-4cab-97df-da904ef5cdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319502029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.319502029
Directory /workspace/18.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.208601296
Short name T1091
Test name
Test status
Simulation time 135335125 ps
CPU time 2.42 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 216164 kb
Host smart-f9d77f97-bdcf-4534-a068-fdefb91e45ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208601296 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.208601296
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3578543641
Short name T1092
Test name
Test status
Simulation time 74716455 ps
CPU time 2.01 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 219656 kb
Host smart-66330c38-bfdb-42b8-a4ae-3c84837d2a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578543641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3578543641
Directory /workspace/19.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2760981208
Short name T1016
Test name
Test status
Simulation time 102467267 ps
CPU time 0.69 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 203752 kb
Host smart-1accdca9-9594-4806-863c-be36fcce395e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760981208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2760981208
Directory /workspace/19.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1931809187
Short name T1053
Test name
Test status
Simulation time 107366143 ps
CPU time 2.77 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 215160 kb
Host smart-ed59c479-9840-4902-8af0-201ea035eca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931809187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1931809187
Directory /workspace/19.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4058420493
Short name T1090
Test name
Test status
Simulation time 32768104 ps
CPU time 1.75 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215228 kb
Host smart-d3845181-806b-417b-89d8-772fd82095a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058420493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4058420493
Directory /workspace/19.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4155042433
Short name T155
Test name
Test status
Simulation time 7065188071 ps
CPU time 19.96 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:26 PM PDT 24
Peak memory 223496 kb
Host smart-75133580-e1dd-4501-b069-ee198a63335e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155042433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4155042433
Directory /workspace/19.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2988588364
Short name T1077
Test name
Test status
Simulation time 1241367197 ps
CPU time 24.53 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:34:21 PM PDT 24
Peak memory 215048 kb
Host smart-3a872c86-4a6f-4b56-ba04-23a118cee4f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988588364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2988588364
Directory /workspace/2.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2207737447
Short name T1039
Test name
Test status
Simulation time 649143561 ps
CPU time 12.3 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 215104 kb
Host smart-d6c9b110-3c5e-4053-9787-51338a5a01a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207737447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2207737447
Directory /workspace/2.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2729124899
Short name T87
Test name
Test status
Simulation time 77186708 ps
CPU time 0.96 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 206680 kb
Host smart-6b3957a9-02b3-4b51-9382-9b60f97595e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729124899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2729124899
Directory /workspace/2.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1369137826
Short name T1046
Test name
Test status
Simulation time 42820140 ps
CPU time 1.7 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:33:56 PM PDT 24
Peak memory 215464 kb
Host smart-5c72c275-613a-4b59-804d-4a1fabd29fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369137826 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1369137826
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1209293466
Short name T126
Test name
Test status
Simulation time 47314880 ps
CPU time 1.38 seconds
Started Aug 17 06:33:57 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 206780 kb
Host smart-4d05dee8-40b7-49e6-bd8f-fcd524e16d65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209293466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
209293466
Directory /workspace/2.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3228499676
Short name T1036
Test name
Test status
Simulation time 14299069 ps
CPU time 0.76 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 203700 kb
Host smart-20c03772-44eb-49f5-9e7b-47b7349f1378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228499676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
228499676
Directory /workspace/2.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3131101360
Short name T121
Test name
Test status
Simulation time 168650487 ps
CPU time 1.13 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 215060 kb
Host smart-4279f3d6-971e-4617-931d-e4c2dd83869e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131101360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3131101360
Directory /workspace/2.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.58193241
Short name T1128
Test name
Test status
Simulation time 21138812 ps
CPU time 0.69 seconds
Started Aug 17 06:33:58 PM PDT 24
Finished Aug 17 06:33:59 PM PDT 24
Peak memory 203584 kb
Host smart-d2adf0fb-71ee-439c-92a0-3c17b0873778
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58193241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_
walk.58193241
Directory /workspace/2.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1258052762
Short name T1067
Test name
Test status
Simulation time 375900994 ps
CPU time 2.98 seconds
Started Aug 17 06:33:51 PM PDT 24
Finished Aug 17 06:33:54 PM PDT 24
Peak memory 215076 kb
Host smart-1b4e736d-0b29-4871-9386-8cadd6d57778
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258052762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1258052762
Directory /workspace/2.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1236713802
Short name T1116
Test name
Test status
Simulation time 765759274 ps
CPU time 5.08 seconds
Started Aug 17 06:33:53 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 216240 kb
Host smart-4717b9a6-fdff-4cee-b75d-c686c6c11b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236713802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
236713802
Directory /workspace/2.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2222844298
Short name T112
Test name
Test status
Simulation time 391894469 ps
CPU time 12.69 seconds
Started Aug 17 06:33:56 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 215172 kb
Host smart-6e024bd0-6792-4bf2-acd1-76e48f7e4146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222844298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2222844298
Directory /workspace/2.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.336953977
Short name T1094
Test name
Test status
Simulation time 14090550 ps
CPU time 0.75 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 204052 kb
Host smart-80b5b95b-a10f-418e-b264-df623a779f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336953977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.336953977
Directory /workspace/20.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3854455876
Short name T1031
Test name
Test status
Simulation time 104833830 ps
CPU time 0.77 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 203700 kb
Host smart-5ca5448f-ed25-4188-abae-b370709a5986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854455876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3854455876
Directory /workspace/21.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2354988082
Short name T1015
Test name
Test status
Simulation time 54207787 ps
CPU time 0.75 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 204064 kb
Host smart-f526edec-1385-4fca-8bbf-7a6be0056076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354988082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2354988082
Directory /workspace/22.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.961318779
Short name T1062
Test name
Test status
Simulation time 135443995 ps
CPU time 0.74 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 203708 kb
Host smart-f4b2c236-0cd1-4cd3-9baa-0ed07a395543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961318779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.961318779
Directory /workspace/23.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2573457956
Short name T1042
Test name
Test status
Simulation time 16070773 ps
CPU time 0.7 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 203696 kb
Host smart-081094fe-1e2d-46f4-9e4a-e75737385d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573457956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2573457956
Directory /workspace/24.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3467446173
Short name T1018
Test name
Test status
Simulation time 49592817 ps
CPU time 0.73 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 203660 kb
Host smart-ab8b24d0-16a3-48e2-9aee-5602ace0481d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467446173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3467446173
Directory /workspace/25.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1896193038
Short name T1055
Test name
Test status
Simulation time 43042600 ps
CPU time 0.73 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 203704 kb
Host smart-613341aa-0a22-4195-8063-fd6e35a5b725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896193038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1896193038
Directory /workspace/26.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1509411122
Short name T1102
Test name
Test status
Simulation time 37828794 ps
CPU time 0.75 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 203692 kb
Host smart-25b971a9-2c00-4790-a196-1e3c89dbc2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509411122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1509411122
Directory /workspace/27.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.151125792
Short name T1048
Test name
Test status
Simulation time 46974534 ps
CPU time 0.75 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 204028 kb
Host smart-b15a984e-8cf0-4306-806f-3c803907eed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151125792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.151125792
Directory /workspace/28.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2278631038
Short name T1037
Test name
Test status
Simulation time 36394959 ps
CPU time 0.77 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 203648 kb
Host smart-93c411ac-c2c8-46d9-b6f6-77d10e19a502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278631038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2278631038
Directory /workspace/29.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2249316409
Short name T1075
Test name
Test status
Simulation time 5883714060 ps
CPU time 21.28 seconds
Started Aug 17 06:33:56 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 206972 kb
Host smart-fc282f86-c68a-45eb-af55-88775a98a054
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249316409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2249316409
Directory /workspace/3.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2153794466
Short name T1095
Test name
Test status
Simulation time 610014890 ps
CPU time 13.53 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:24 PM PDT 24
Peak memory 206884 kb
Host smart-b36a1294-89fa-4ccc-9c1b-73403bf12866
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153794466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2153794466
Directory /workspace/3.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3868879353
Short name T90
Test name
Test status
Simulation time 40786283 ps
CPU time 0.94 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 206700 kb
Host smart-056335ed-b23b-496b-a761-33f68a4e022c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868879353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3868879353
Directory /workspace/3.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.917984116
Short name T1107
Test name
Test status
Simulation time 41218480 ps
CPU time 2.79 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 217776 kb
Host smart-96613382-b2df-48a1-9483-07a196d90826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917984116 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.917984116
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.184236294
Short name T120
Test name
Test status
Simulation time 80532970 ps
CPU time 2.58 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 215204 kb
Host smart-d8b8bca2-4cea-4b92-a425-ae9c32403c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184236294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.184236294
Directory /workspace/3.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2223688242
Short name T1103
Test name
Test status
Simulation time 94805292 ps
CPU time 0.82 seconds
Started Aug 17 06:33:55 PM PDT 24
Finished Aug 17 06:33:56 PM PDT 24
Peak memory 203776 kb
Host smart-68404587-e438-43dc-89d5-2a37ed448c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223688242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
223688242
Directory /workspace/3.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1606068183
Short name T1061
Test name
Test status
Simulation time 44471232 ps
CPU time 1.56 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215108 kb
Host smart-3f438116-af46-4735-bba6-0a1eb1a0c6f0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606068183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1606068183
Directory /workspace/3.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3095295747
Short name T1122
Test name
Test status
Simulation time 28447474 ps
CPU time 0.7 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:05 PM PDT 24
Peak memory 203544 kb
Host smart-e86dfa69-c0c4-43a9-ba53-1c6720fc6c45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095295747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3095295747
Directory /workspace/3.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.627745542
Short name T1057
Test name
Test status
Simulation time 108668422 ps
CPU time 2.95 seconds
Started Aug 17 06:34:01 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 215100 kb
Host smart-d5f96d41-a8ff-40fd-9aae-fd410b84ab17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627745542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.627745542
Directory /workspace/3.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.810784851
Short name T115
Test name
Test status
Simulation time 304556617 ps
CPU time 3.55 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 215344 kb
Host smart-2f583bad-2ce1-4b02-879e-871f69893ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810784851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.810784851
Directory /workspace/3.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.821167941
Short name T1078
Test name
Test status
Simulation time 12040254 ps
CPU time 0.72 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 203864 kb
Host smart-ba4aa188-1e20-4332-aaa8-16522dac1406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821167941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.821167941
Directory /workspace/30.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.709467271
Short name T1098
Test name
Test status
Simulation time 26290930 ps
CPU time 0.75 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 203728 kb
Host smart-01e40bf8-3a76-4bda-9120-5a04a09b730c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709467271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.709467271
Directory /workspace/31.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.976500356
Short name T1089
Test name
Test status
Simulation time 15422556 ps
CPU time 0.67 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 203764 kb
Host smart-d6489385-5b3b-4937-bed5-2cfdea5a4cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976500356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.976500356
Directory /workspace/32.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.943548005
Short name T1040
Test name
Test status
Simulation time 25250501 ps
CPU time 0.72 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 204048 kb
Host smart-e95838a6-938d-429e-bbf1-fe7de8a644cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943548005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.943548005
Directory /workspace/33.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2196933010
Short name T1013
Test name
Test status
Simulation time 14493982 ps
CPU time 0.72 seconds
Started Aug 17 06:34:00 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 203780 kb
Host smart-83c2c910-89d0-4083-aea8-5e70ad2c4b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196933010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2196933010
Directory /workspace/34.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2396286545
Short name T1034
Test name
Test status
Simulation time 29509221 ps
CPU time 0.75 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:16 PM PDT 24
Peak memory 203752 kb
Host smart-af16f1e3-987a-4f39-85ea-206980554c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396286545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2396286545
Directory /workspace/35.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3596165534
Short name T1105
Test name
Test status
Simulation time 18459156 ps
CPU time 0.68 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 203732 kb
Host smart-b32b9055-b9ec-4765-a4f5-1051260f44d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596165534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3596165534
Directory /workspace/36.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4198835768
Short name T1027
Test name
Test status
Simulation time 11695022 ps
CPU time 0.71 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 203728 kb
Host smart-e7ab45ba-775f-4248-8819-ea0bc621df5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198835768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4198835768
Directory /workspace/37.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1971718214
Short name T1014
Test name
Test status
Simulation time 13616514 ps
CPU time 0.7 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 204064 kb
Host smart-47bb278f-b84d-4e3a-84a7-9dd308b91980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971718214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1971718214
Directory /workspace/38.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2803502044
Short name T1113
Test name
Test status
Simulation time 44434008 ps
CPU time 0.72 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 203764 kb
Host smart-acefe9bc-dca5-4541-b976-84d2890610c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803502044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2803502044
Directory /workspace/39.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4067540531
Short name T124
Test name
Test status
Simulation time 1319169922 ps
CPU time 8.64 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 215032 kb
Host smart-95ade26c-ba90-4bb0-bcf1-6b81ca60c847
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067540531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4067540531
Directory /workspace/4.spi_device_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3763806587
Short name T123
Test name
Test status
Simulation time 7516757603 ps
CPU time 36.64 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:45 PM PDT 24
Peak memory 215080 kb
Host smart-156a6c01-f550-41da-9cd5-de5e49113134
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763806587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3763806587
Directory /workspace/4.spi_device_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2173915822
Short name T86
Test name
Test status
Simulation time 75994618 ps
CPU time 1.37 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 216048 kb
Host smart-bdeb9ca1-995c-4b0b-9142-97df0f89ead2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173915822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2173915822
Directory /workspace/4.spi_device_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2939284688
Short name T1047
Test name
Test status
Simulation time 48065311 ps
CPU time 1.97 seconds
Started Aug 17 06:33:59 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 215156 kb
Host smart-e4ad26f5-c87e-42c6-90eb-4a4fe10b8f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939284688 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2939284688
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2396837549
Short name T1082
Test name
Test status
Simulation time 35967778 ps
CPU time 1.34 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 215056 kb
Host smart-d2c1f414-0684-4ec7-bc11-9d4fb7b8ac5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396837549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
396837549
Directory /workspace/4.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3770859707
Short name T1088
Test name
Test status
Simulation time 18099713 ps
CPU time 0.75 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 204020 kb
Host smart-03da7faf-2f9e-4096-a0cc-d9ef9af00447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770859707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
770859707
Directory /workspace/4.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1361007071
Short name T1076
Test name
Test status
Simulation time 30515815 ps
CPU time 1.29 seconds
Started Aug 17 06:34:01 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 215028 kb
Host smart-6a38f37f-2f1c-4bd4-bf89-d7a2cabfcf99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361007071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1361007071
Directory /workspace/4.spi_device_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1883592624
Short name T1019
Test name
Test status
Simulation time 35309875 ps
CPU time 0.65 seconds
Started Aug 17 06:34:12 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 203568 kb
Host smart-45187f96-ec1f-4721-8e88-baed5c25236b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883592624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1883592624
Directory /workspace/4.spi_device_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.641503653
Short name T1097
Test name
Test status
Simulation time 242928526 ps
CPU time 3.5 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215116 kb
Host smart-42ec4b65-517e-4b0c-b83d-c9a9fac7e99c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641503653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.641503653
Directory /workspace/4.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3720314955
Short name T108
Test name
Test status
Simulation time 642283121 ps
CPU time 4.13 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215320 kb
Host smart-6b1006e9-5528-434c-86c1-b7a3b40fa18b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720314955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
720314955
Directory /workspace/4.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1486382405
Short name T116
Test name
Test status
Simulation time 2384541076 ps
CPU time 8.17 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 215140 kb
Host smart-23d43ac2-5384-4268-9a64-de683e129c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486382405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1486382405
Directory /workspace/4.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3198570794
Short name T1114
Test name
Test status
Simulation time 39543748 ps
CPU time 0.76 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 204064 kb
Host smart-dc9415cb-0f7e-4737-9324-8002c1c4ffa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198570794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3198570794
Directory /workspace/40.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3486305062
Short name T1064
Test name
Test status
Simulation time 15689124 ps
CPU time 0.69 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 204040 kb
Host smart-ac54e7a5-9b08-4c50-8106-9138d6a2f17d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486305062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3486305062
Directory /workspace/41.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.424504254
Short name T1035
Test name
Test status
Simulation time 17719215 ps
CPU time 0.71 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 203764 kb
Host smart-7738bf17-dc92-4597-84ce-fca231b0e551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424504254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.424504254
Directory /workspace/42.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3364348444
Short name T1022
Test name
Test status
Simulation time 33225481 ps
CPU time 0.69 seconds
Started Aug 17 06:34:19 PM PDT 24
Finished Aug 17 06:34:19 PM PDT 24
Peak memory 204024 kb
Host smart-5c0ec638-6616-4d92-9ac7-c060c6d4578f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364348444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3364348444
Directory /workspace/43.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2066643135
Short name T1096
Test name
Test status
Simulation time 164361292 ps
CPU time 0.66 seconds
Started Aug 17 06:34:14 PM PDT 24
Finished Aug 17 06:34:15 PM PDT 24
Peak memory 204064 kb
Host smart-dcb6e7c6-89a3-4700-a0cb-79aba8809e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066643135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2066643135
Directory /workspace/44.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3606903557
Short name T1130
Test name
Test status
Simulation time 11507257 ps
CPU time 0.74 seconds
Started Aug 17 06:34:13 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 203752 kb
Host smart-cade723b-087b-4861-a05f-fc396a08ddca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606903557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3606903557
Directory /workspace/45.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4214924551
Short name T1111
Test name
Test status
Simulation time 13076845 ps
CPU time 0.74 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 203772 kb
Host smart-50d96f3c-52cc-4ad8-a7d2-2b52d2a17105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214924551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4214924551
Directory /workspace/46.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3277132816
Short name T1017
Test name
Test status
Simulation time 28911095 ps
CPU time 0.74 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 203704 kb
Host smart-40fd6b7b-c2fa-45cd-aa9b-902db1372c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277132816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3277132816
Directory /workspace/47.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2032501495
Short name T1109
Test name
Test status
Simulation time 43516526 ps
CPU time 0.72 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 203712 kb
Host smart-6e21f13c-fee2-4b42-871d-7b1dd3825910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032501495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2032501495
Directory /workspace/48.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1374757669
Short name T1079
Test name
Test status
Simulation time 77842648 ps
CPU time 0.73 seconds
Started Aug 17 06:34:25 PM PDT 24
Finished Aug 17 06:34:26 PM PDT 24
Peak memory 203752 kb
Host smart-f6b1e8e4-668f-4981-8d80-935c532630ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374757669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1374757669
Directory /workspace/49.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3368138643
Short name T1023
Test name
Test status
Simulation time 118461341 ps
CPU time 2.66 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 216328 kb
Host smart-7d1a2de1-8bc3-40b5-8c24-03e1886c1c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368138643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3368138643
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2289223508
Short name T1038
Test name
Test status
Simulation time 29791158 ps
CPU time 1.75 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:08 PM PDT 24
Peak memory 206780 kb
Host smart-6e49225e-70a7-4f5e-901a-e4c45c50cf2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289223508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
289223508
Directory /workspace/5.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1670920619
Short name T1030
Test name
Test status
Simulation time 63092339 ps
CPU time 0.71 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 204068 kb
Host smart-2855a3d5-dfec-422d-b355-c0f9f224eece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670920619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
670920619
Directory /workspace/5.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1834302442
Short name T1074
Test name
Test status
Simulation time 57307095 ps
CPU time 4.03 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215052 kb
Host smart-781eacfe-7a7b-4038-809b-d28c897110fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834302442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1834302442
Directory /workspace/5.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2956541786
Short name T1131
Test name
Test status
Simulation time 353752257 ps
CPU time 7.86 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215592 kb
Host smart-81b24e77-316d-4787-9cae-2a2ad30cd754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956541786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2956541786
Directory /workspace/5.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1467195816
Short name T66
Test name
Test status
Simulation time 346007232 ps
CPU time 2.57 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 216200 kb
Host smart-da6a4317-f514-4226-b1f2-8aab258f123a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467195816 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1467195816
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2461644947
Short name T119
Test name
Test status
Simulation time 596626768 ps
CPU time 2.46 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 215016 kb
Host smart-e197779e-8626-4b30-b025-3e5c2640ccf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461644947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
461644947
Directory /workspace/6.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4185624544
Short name T1118
Test name
Test status
Simulation time 17564697 ps
CPU time 0.69 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 204064 kb
Host smart-16880a64-2fa0-49be-be4f-ce135d6d3dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185624544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
185624544
Directory /workspace/6.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4054237422
Short name T1052
Test name
Test status
Simulation time 605807475 ps
CPU time 3.16 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215048 kb
Host smart-29d376c3-0bc2-434e-b42c-1b0c069e6317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054237422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4054237422
Directory /workspace/6.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2581797231
Short name T114
Test name
Test status
Simulation time 227277520 ps
CPU time 1.84 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215180 kb
Host smart-51114e52-f766-4d90-a364-67a67999cb66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581797231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
581797231
Directory /workspace/6.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3455564859
Short name T154
Test name
Test status
Simulation time 353109260 ps
CPU time 7.91 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:17 PM PDT 24
Peak memory 215064 kb
Host smart-25ba85bc-1a0c-47a4-9e3b-4235f16029fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455564859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3455564859
Directory /workspace/6.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1732977451
Short name T1126
Test name
Test status
Simulation time 233855889 ps
CPU time 3.3 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:09 PM PDT 24
Peak memory 218280 kb
Host smart-f87dd4b1-8f11-4a6a-8bb5-ff70ec1a81a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732977451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1732977451
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2548495870
Short name T142
Test name
Test status
Simulation time 60830270 ps
CPU time 1.36 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:06 PM PDT 24
Peak memory 215076 kb
Host smart-618a7732-851a-448b-9219-6066d0a4176a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548495870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
548495870
Directory /workspace/7.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1547900637
Short name T1049
Test name
Test status
Simulation time 74816576 ps
CPU time 0.7 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 204044 kb
Host smart-24a205da-f1cc-4f3a-8a7f-09b473a9208b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547900637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
547900637
Directory /workspace/7.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1866090991
Short name T1054
Test name
Test status
Simulation time 226032032 ps
CPU time 1.82 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 215056 kb
Host smart-179dfbad-d34b-4b88-85c8-e2a7d68562d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866090991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1866090991
Directory /workspace/7.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2538473120
Short name T1085
Test name
Test status
Simulation time 136670392 ps
CPU time 2.59 seconds
Started Aug 17 06:34:04 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 215288 kb
Host smart-731f4e08-8617-4535-b7bf-8375c3523fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538473120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
538473120
Directory /workspace/7.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.135237316
Short name T182
Test name
Test status
Simulation time 1665915224 ps
CPU time 21.71 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:27 PM PDT 24
Peak memory 215192 kb
Host smart-25f9441f-5c4d-4671-81f4-6e563dfb66c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135237316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.135237316
Directory /workspace/7.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2536645854
Short name T180
Test name
Test status
Simulation time 84788009 ps
CPU time 2.59 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 216384 kb
Host smart-85ed94d8-ef2d-4571-9d12-420632e828a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536645854 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2536645854
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2493387427
Short name T1070
Test name
Test status
Simulation time 86846734 ps
CPU time 1.38 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:07 PM PDT 24
Peak memory 206832 kb
Host smart-b1002382-9c3f-40bc-9a77-d3c5b6cfab59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493387427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
493387427
Directory /workspace/8.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2546716861
Short name T1069
Test name
Test status
Simulation time 44051470 ps
CPU time 0.75 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:03 PM PDT 24
Peak memory 204084 kb
Host smart-6ded8a17-111f-426b-ba42-ba0face589e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546716861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
546716861
Directory /workspace/8.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1943210240
Short name T1024
Test name
Test status
Simulation time 45924367 ps
CPU time 2.94 seconds
Started Aug 17 06:34:09 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215048 kb
Host smart-5d5c131c-2291-4bec-a66e-8455528af53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943210240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1943210240
Directory /workspace/8.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.814561780
Short name T1121
Test name
Test status
Simulation time 56582337 ps
CPU time 3.24 seconds
Started Aug 17 06:34:06 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215240 kb
Host smart-3287504d-fe25-4506-bdf1-bb5dd89f8263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814561780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.814561780
Directory /workspace/8.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1036393320
Short name T186
Test name
Test status
Simulation time 200843766 ps
CPU time 6.69 seconds
Started Aug 17 06:34:03 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 215164 kb
Host smart-3736ed86-73d9-45eb-abf9-bdf8270a289c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036393320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1036393320
Directory /workspace/8.spi_device_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1269156367
Short name T1056
Test name
Test status
Simulation time 451628537 ps
CPU time 2.85 seconds
Started Aug 17 06:34:10 PM PDT 24
Finished Aug 17 06:34:13 PM PDT 24
Peak memory 217368 kb
Host smart-60d3ecca-0b41-490f-9e6c-4be750a75709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269156367 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1269156367
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4243834587
Short name T1080
Test name
Test status
Simulation time 222374459 ps
CPU time 1.81 seconds
Started Aug 17 06:34:07 PM PDT 24
Finished Aug 17 06:34:10 PM PDT 24
Peak memory 214928 kb
Host smart-4be91f50-7b7f-4dd7-a4b9-b1f2a1c5ab3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243834587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
243834587
Directory /workspace/9.spi_device_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3353248460
Short name T1044
Test name
Test status
Simulation time 63178785 ps
CPU time 0.72 seconds
Started Aug 17 06:34:11 PM PDT 24
Finished Aug 17 06:34:12 PM PDT 24
Peak memory 203672 kb
Host smart-96767c97-02bf-49f2-9cb4-23f2103cfa12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353248460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
353248460
Directory /workspace/9.spi_device_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.795126664
Short name T151
Test name
Test status
Simulation time 273706033 ps
CPU time 1.88 seconds
Started Aug 17 06:34:02 PM PDT 24
Finished Aug 17 06:34:04 PM PDT 24
Peak memory 206900 kb
Host smart-a7f5f3de-5f4b-4cb8-bcc0-27fef50e2cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795126664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.795126664
Directory /workspace/9.spi_device_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1980781167
Short name T1123
Test name
Test status
Simulation time 189304890 ps
CPU time 2.64 seconds
Started Aug 17 06:34:08 PM PDT 24
Finished Aug 17 06:34:11 PM PDT 24
Peak memory 215284 kb
Host smart-87a196b9-21b1-43df-b4d7-91e693c2eaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980781167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
980781167
Directory /workspace/9.spi_device_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.328979924
Short name T188
Test name
Test status
Simulation time 298076280 ps
CPU time 8.37 seconds
Started Aug 17 06:34:05 PM PDT 24
Finished Aug 17 06:34:14 PM PDT 24
Peak memory 215220 kb
Host smart-657fe2bd-e631-46ec-adff-d1914b3d49c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328979924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.328979924
Directory /workspace/9.spi_device_tl_intg_err/latest


Test location /workspace/coverage/default/0.spi_device_alert_test.2822650012
Short name T411
Test name
Test status
Simulation time 15514743 ps
CPU time 0.7 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 206224 kb
Host smart-69c3f307-00d7-4e5e-b2df-f8cb85fadb93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822650012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
822650012
Directory /workspace/0.spi_device_alert_test/latest


Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2857683643
Short name T261
Test name
Test status
Simulation time 448317313 ps
CPU time 6.25 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 233588 kb
Host smart-a7210c3c-97e6-438c-9d85-ef1cb373c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857683643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2857683643
Directory /workspace/0.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/0.spi_device_csb_read.4252091265
Short name T64
Test name
Test status
Simulation time 163135006 ps
CPU time 0.79 seconds
Started Aug 17 06:35:19 PM PDT 24
Finished Aug 17 06:35:20 PM PDT 24
Peak memory 207768 kb
Host smart-3d6f8cb7-c40e-44bf-9ff6-f2aa66ea55c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252091265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4252091265
Directory /workspace/0.spi_device_csb_read/latest


Test location /workspace/coverage/default/0.spi_device_flash_all.128137493
Short name T951
Test name
Test status
Simulation time 1690470511 ps
CPU time 22.34 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:20 PM PDT 24
Peak memory 237784 kb
Host smart-180a58e9-4a2a-4bb3-8b69-b94291d3dfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128137493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.128137493
Directory /workspace/0.spi_device_flash_all/latest


Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4017624338
Short name T779
Test name
Test status
Simulation time 494939230 ps
CPU time 6.26 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 225392 kb
Host smart-122aba2b-e980-4b9e-abd9-0b6a75ec319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017624338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4017624338
Directory /workspace/0.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1268012648
Short name T311
Test name
Test status
Simulation time 3328055854 ps
CPU time 50.73 seconds
Started Aug 17 06:35:17 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 253264 kb
Host smart-b96397b3-7897-4b86-b83a-4fb1fb8a6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268012648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1268012648
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/0.spi_device_flash_mode.4229202572
Short name T375
Test name
Test status
Simulation time 104394154 ps
CPU time 2.78 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 225384 kb
Host smart-5a469bb3-f5ae-4d36-a010-aec57d70186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229202572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4229202572
Directory /workspace/0.spi_device_flash_mode/latest


Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.935379999
Short name T84
Test name
Test status
Simulation time 33881660278 ps
CPU time 236.22 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:38:58 PM PDT 24
Peak memory 255012 kb
Host smart-7b26a0e8-d51a-4710-be98-33f962f9c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935379999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
935379999
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/0.spi_device_intercept.4100100804
Short name T958
Test name
Test status
Simulation time 3016602897 ps
CPU time 11.32 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 225404 kb
Host smart-840fb205-4777-4a88-8ad5-d3244e6ad1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100100804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4100100804
Directory /workspace/0.spi_device_intercept/latest


Test location /workspace/coverage/default/0.spi_device_mailbox.1223327828
Short name T265
Test name
Test status
Simulation time 16501205487 ps
CPU time 124.51 seconds
Started Aug 17 06:35:14 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 249796 kb
Host smart-34132861-19d4-41fe-8af1-0a335b784e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223327828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1223327828
Directory /workspace/0.spi_device_mailbox/latest


Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2131355177
Short name T778
Test name
Test status
Simulation time 1145119012 ps
CPU time 3.73 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 225312 kb
Host smart-fbc1022d-9cfc-4ac2-8573-fe41c63a4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131355177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2131355177
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.793315493
Short name T26
Test name
Test status
Simulation time 106859239 ps
CPU time 2.21 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 223972 kb
Host smart-9b9c10f5-a472-4c9f-82f4-5213fe53461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793315493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.793315493
Directory /workspace/0.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.814429819
Short name T415
Test name
Test status
Simulation time 426336525 ps
CPU time 3.94 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 220272 kb
Host smart-f2c57ce3-8b92-4da1-98a5-c1a3555c511d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=814429819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.814429819
Directory /workspace/0.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/0.spi_device_stress_all.356759449
Short name T68
Test name
Test status
Simulation time 33805249563 ps
CPU time 120.8 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 239084 kb
Host smart-0930f4ea-c672-45c3-a053-b4726bf52d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356759449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.356759449
Directory /workspace/0.spi_device_stress_all/latest


Test location /workspace/coverage/default/0.spi_device_tpm_all.4258981880
Short name T92
Test name
Test status
Simulation time 12383884081 ps
CPU time 19.14 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 217304 kb
Host smart-9a4b6492-f53f-443d-84d6-c23bc6d26cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258981880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4258981880
Directory /workspace/0.spi_device_tpm_all/latest


Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4264819210
Short name T801
Test name
Test status
Simulation time 4112417726 ps
CPU time 8.52 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 217284 kb
Host smart-6ee56c45-a16e-4e00-8024-59c21bd7583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264819210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4264819210
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/0.spi_device_tpm_rw.12103672
Short name T79
Test name
Test status
Simulation time 60081917 ps
CPU time 0.91 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 206864 kb
Host smart-86f1bf11-5f0f-4a53-b67c-17f75e04f416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12103672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.12103672
Directory /workspace/0.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1740802857
Short name T809
Test name
Test status
Simulation time 49978154 ps
CPU time 0.87 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:00 PM PDT 24
Peak memory 206744 kb
Host smart-a7dfe55d-2036-455c-96b7-e25dda7c0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740802857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1740802857
Directory /workspace/0.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/0.spi_device_upload.4224942845
Short name T692
Test name
Test status
Simulation time 137747308060 ps
CPU time 20.87 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 225476 kb
Host smart-83f9a5ea-cf03-4e78-9483-ee50f8e62660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224942845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4224942845
Directory /workspace/0.spi_device_upload/latest


Test location /workspace/coverage/default/1.spi_device_csb_read.662160092
Short name T529
Test name
Test status
Simulation time 35844275 ps
CPU time 0.76 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 207384 kb
Host smart-f31be36b-117b-40f3-95d7-da57d95bd5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662160092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.662160092
Directory /workspace/1.spi_device_csb_read/latest


Test location /workspace/coverage/default/1.spi_device_flash_all.1136773246
Short name T886
Test name
Test status
Simulation time 18823291 ps
CPU time 0.75 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:39 PM PDT 24
Peak memory 216616 kb
Host smart-93f59945-42e9-4e8e-8fc4-915ab2b31760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136773246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1136773246
Directory /workspace/1.spi_device_flash_all/latest


Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.97731787
Short name T1000
Test name
Test status
Simulation time 2538317361 ps
CPU time 35.59 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:40 PM PDT 24
Peak memory 255516 kb
Host smart-13186342-9b46-40a8-8e3f-1d3b1b2be04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97731787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.97731787
Directory /workspace/1.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2791539151
Short name T140
Test name
Test status
Simulation time 11409428090 ps
CPU time 136.22 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:37:19 PM PDT 24
Peak memory 250152 kb
Host smart-c73c765b-bcc8-4356-a534-e01e03adb5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791539151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2791539151
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/1.spi_device_flash_mode.3115124292
Short name T245
Test name
Test status
Simulation time 31761953 ps
CPU time 2.45 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 233548 kb
Host smart-87ef9b09-e153-43b0-be06-0969875f62d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115124292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3115124292
Directory /workspace/1.spi_device_flash_mode/latest


Test location /workspace/coverage/default/1.spi_device_intercept.2221785751
Short name T943
Test name
Test status
Simulation time 1166169499 ps
CPU time 9.53 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 233584 kb
Host smart-2214126b-437f-42f1-883e-684ecfb50799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221785751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2221785751
Directory /workspace/1.spi_device_intercept/latest


Test location /workspace/coverage/default/1.spi_device_mailbox.2478834237
Short name T268
Test name
Test status
Simulation time 8143097132 ps
CPU time 30.47 seconds
Started Aug 17 06:35:14 PM PDT 24
Finished Aug 17 06:35:50 PM PDT 24
Peak memory 233736 kb
Host smart-07367426-0a72-4ef4-8ab1-1a96e8c52ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478834237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2478834237
Directory /workspace/1.spi_device_mailbox/latest


Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1397886150
Short name T13
Test name
Test status
Simulation time 409827646 ps
CPU time 8.49 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 249468 kb
Host smart-f603e8e3-6535-4f8c-b6cf-c49648931e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397886150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1397886150
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1186702479
Short name T217
Test name
Test status
Simulation time 32644856923 ps
CPU time 22.15 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 225440 kb
Host smart-c43719d2-a8dc-4462-9c47-c078b40dc2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186702479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1186702479
Directory /workspace/1.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2612718834
Short name T572
Test name
Test status
Simulation time 1843429280 ps
CPU time 7.33 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:19 PM PDT 24
Peak memory 221536 kb
Host smart-a07ec3f0-8c38-43c2-8fe6-1a49f0d0396c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2612718834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2612718834
Directory /workspace/1.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/1.spi_device_sec_cm.1168374731
Short name T74
Test name
Test status
Simulation time 94154801 ps
CPU time 1.21 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 236740 kb
Host smart-3c46a2f1-d490-479c-be16-4a79f7f47d88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168374731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1168374731
Directory /workspace/1.spi_device_sec_cm/latest


Test location /workspace/coverage/default/1.spi_device_stress_all.290939773
Short name T254
Test name
Test status
Simulation time 47748146126 ps
CPU time 225.39 seconds
Started Aug 17 06:35:15 PM PDT 24
Finished Aug 17 06:39:00 PM PDT 24
Peak memory 264456 kb
Host smart-ff938a7d-c755-4162-a2a1-f57c6ee91592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290939773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.290939773
Directory /workspace/1.spi_device_stress_all/latest


Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1077638644
Short name T95
Test name
Test status
Simulation time 22427106641 ps
CPU time 12.7 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 218552 kb
Host smart-14638e28-c286-48b5-9a79-176b0d150f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077638644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1077638644
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/1.spi_device_tpm_rw.3851814813
Short name T786
Test name
Test status
Simulation time 185585952 ps
CPU time 2.53 seconds
Started Aug 17 06:34:58 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 217092 kb
Host smart-053137a0-8bf0-418b-9601-3fe1f677efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851814813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3851814813
Directory /workspace/1.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2657420136
Short name T634
Test name
Test status
Simulation time 335403566 ps
CPU time 0.77 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 206728 kb
Host smart-b5e07ecc-d53d-4644-8547-903d9e61d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657420136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2657420136
Directory /workspace/1.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/1.spi_device_upload.1054311814
Short name T285
Test name
Test status
Simulation time 556517114 ps
CPU time 7.11 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 233544 kb
Host smart-d6d44c5c-ae75-4d4c-86ca-f61fcdbe3c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054311814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1054311814
Directory /workspace/1.spi_device_upload/latest


Test location /workspace/coverage/default/10.spi_device_alert_test.63027409
Short name T459
Test name
Test status
Simulation time 38276959 ps
CPU time 0.74 seconds
Started Aug 17 06:35:32 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 205724 kb
Host smart-6f04ca20-757e-478a-b030-54c46409d7d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63027409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.63027409
Directory /workspace/10.spi_device_alert_test/latest


Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1659308994
Short name T511
Test name
Test status
Simulation time 423432650 ps
CPU time 2.4 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 225296 kb
Host smart-26bd0009-3e0b-45f1-a703-9bc355cbfce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659308994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1659308994
Directory /workspace/10.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/10.spi_device_csb_read.2453545630
Short name T844
Test name
Test status
Simulation time 21229682 ps
CPU time 0.82 seconds
Started Aug 17 06:35:32 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 207740 kb
Host smart-414332a3-b301-4271-ba13-df1cf5246b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453545630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2453545630
Directory /workspace/10.spi_device_csb_read/latest


Test location /workspace/coverage/default/10.spi_device_flash_all.4257131981
Short name T715
Test name
Test status
Simulation time 579659938 ps
CPU time 4.64 seconds
Started Aug 17 06:35:28 PM PDT 24
Finished Aug 17 06:35:38 PM PDT 24
Peak memory 233564 kb
Host smart-015d3e02-fe46-40be-8859-38e4c2ff14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257131981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4257131981
Directory /workspace/10.spi_device_flash_all/latest


Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1861144508
Short name T189
Test name
Test status
Simulation time 1525877416 ps
CPU time 18.78 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 241796 kb
Host smart-41914a2c-c32a-4ccd-866d-102c201d737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861144508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1861144508
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/10.spi_device_intercept.3332934453
Short name T117
Test name
Test status
Simulation time 634944444 ps
CPU time 2.95 seconds
Started Aug 17 06:35:30 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 225292 kb
Host smart-910eedfa-55bb-4b56-8b46-d53789d0bc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332934453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3332934453
Directory /workspace/10.spi_device_intercept/latest


Test location /workspace/coverage/default/10.spi_device_mailbox.4102040337
Short name T528
Test name
Test status
Simulation time 63934202860 ps
CPU time 126.11 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 250376 kb
Host smart-b7365495-daf1-4c9b-8ba4-aa76abc25fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102040337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4102040337
Directory /workspace/10.spi_device_mailbox/latest


Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.671796593
Short name T773
Test name
Test status
Simulation time 69586678 ps
CPU time 2.24 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 233592 kb
Host smart-f8f2d527-d0b0-466f-8352-eac4d2a80114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671796593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.671796593
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1123980135
Short name T235
Test name
Test status
Simulation time 347529996 ps
CPU time 4.42 seconds
Started Aug 17 06:35:28 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 225404 kb
Host smart-eb4134fa-d238-4e0c-907a-988a5e8d67b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123980135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1123980135
Directory /workspace/10.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4131794877
Short name T398
Test name
Test status
Simulation time 1467787799 ps
CPU time 6.34 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 223860 kb
Host smart-e95adfe8-58a1-4202-b8da-08e7d3551f1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131794877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4131794877
Directory /workspace/10.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/10.spi_device_tpm_all.2524722153
Short name T334
Test name
Test status
Simulation time 18593435343 ps
CPU time 23.14 seconds
Started Aug 17 06:35:21 PM PDT 24
Finished Aug 17 06:35:45 PM PDT 24
Peak memory 217332 kb
Host smart-17606b6d-3af5-4f19-ad99-19b63b56e090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524722153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2524722153
Directory /workspace/10.spi_device_tpm_all/latest


Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2738811551
Short name T805
Test name
Test status
Simulation time 3614367464 ps
CPU time 5.62 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:40 PM PDT 24
Peak memory 217352 kb
Host smart-3538c646-8ad7-4044-8d19-f1838cc09cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738811551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2738811551
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/10.spi_device_tpm_rw.297071418
Short name T538
Test name
Test status
Simulation time 50719026 ps
CPU time 1.2 seconds
Started Aug 17 06:35:44 PM PDT 24
Finished Aug 17 06:35:45 PM PDT 24
Peak memory 208780 kb
Host smart-b7019e13-bd2a-44ad-a3a2-704199c46767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297071418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.297071418
Directory /workspace/10.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2083850277
Short name T358
Test name
Test status
Simulation time 71748632 ps
CPU time 0.84 seconds
Started Aug 17 06:35:36 PM PDT 24
Finished Aug 17 06:35:37 PM PDT 24
Peak memory 206872 kb
Host smart-160a11ba-d740-41e3-98a3-9a84af6071df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083850277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2083850277
Directory /workspace/10.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/10.spi_device_upload.3486452933
Short name T241
Test name
Test status
Simulation time 3379479609 ps
CPU time 17.78 seconds
Started Aug 17 06:35:29 PM PDT 24
Finished Aug 17 06:35:47 PM PDT 24
Peak memory 241856 kb
Host smart-42a90dd2-6f13-4a98-b343-bce8fcea45d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486452933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3486452933
Directory /workspace/10.spi_device_upload/latest


Test location /workspace/coverage/default/11.spi_device_alert_test.2751351363
Short name T346
Test name
Test status
Simulation time 37070635 ps
CPU time 0.73 seconds
Started Aug 17 06:35:34 PM PDT 24
Finished Aug 17 06:35:35 PM PDT 24
Peak memory 206308 kb
Host smart-29e18ff1-9811-4269-8e3a-402b05512c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751351363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2751351363
Directory /workspace/11.spi_device_alert_test/latest


Test location /workspace/coverage/default/11.spi_device_cfg_cmd.461750645
Short name T643
Test name
Test status
Simulation time 108798055 ps
CPU time 3.09 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 225288 kb
Host smart-987f3485-7a07-4eda-b473-084377e4148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461750645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.461750645
Directory /workspace/11.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/11.spi_device_csb_read.293841877
Short name T512
Test name
Test status
Simulation time 20937520 ps
CPU time 0.82 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 207712 kb
Host smart-d4fee1be-a720-4cd8-8e7b-12f908c496c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293841877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.293841877
Directory /workspace/11.spi_device_csb_read/latest


Test location /workspace/coverage/default/11.spi_device_flash_all.3038876637
Short name T938
Test name
Test status
Simulation time 4970029558 ps
CPU time 57.2 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 265104 kb
Host smart-cc666c9b-05bc-425b-bb4d-fd421835b840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038876637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3038876637
Directory /workspace/11.spi_device_flash_all/latest


Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3279925194
Short name T905
Test name
Test status
Simulation time 17374057865 ps
CPU time 76.29 seconds
Started Aug 17 06:35:19 PM PDT 24
Finished Aug 17 06:36:36 PM PDT 24
Peak memory 235780 kb
Host smart-1f7ff078-79d9-4eff-b8f4-2d5b749631af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279925194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3279925194
Directory /workspace/11.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3085303727
Short name T987
Test name
Test status
Simulation time 42695257890 ps
CPU time 362.91 seconds
Started Aug 17 06:35:13 PM PDT 24
Finished Aug 17 06:41:16 PM PDT 24
Peak memory 250208 kb
Host smart-42e27e32-9e76-4202-8e86-f6ab94bc951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085303727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3085303727
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1905334206
Short name T276
Test name
Test status
Simulation time 3825750368 ps
CPU time 25.28 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:35 PM PDT 24
Peak memory 225484 kb
Host smart-b9f4ebc2-efe2-42f1-b90b-a1cf07557529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905334206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1905334206
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/11.spi_device_intercept.3808912576
Short name T532
Test name
Test status
Simulation time 355891060 ps
CPU time 5.99 seconds
Started Aug 17 06:35:26 PM PDT 24
Finished Aug 17 06:35:32 PM PDT 24
Peak memory 233564 kb
Host smart-a8981b9d-120c-4476-8375-76465e6377fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808912576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3808912576
Directory /workspace/11.spi_device_intercept/latest


Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1793074140
Short name T81
Test name
Test status
Simulation time 77381044610 ps
CPU time 15.51 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:35:47 PM PDT 24
Peak memory 225452 kb
Host smart-42e5ac9c-1e0e-4972-a525-2fbbc73df28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793074140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1793074140
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4277192336
Short name T725
Test name
Test status
Simulation time 35022412 ps
CPU time 2.38 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 233128 kb
Host smart-398288eb-42a9-410c-a5da-594daf4fda93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277192336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4277192336
Directory /workspace/11.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1922641585
Short name T166
Test name
Test status
Simulation time 6509249701 ps
CPU time 16.91 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:27 PM PDT 24
Peak memory 220456 kb
Host smart-9fd4f119-8f30-4701-92f6-8e7e869936a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1922641585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1922641585
Directory /workspace/11.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/11.spi_device_stress_all.928176865
Short name T776
Test name
Test status
Simulation time 125392618 ps
CPU time 1.07 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 207904 kb
Host smart-35c571e0-5f89-4752-8e53-e357c3de2444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928176865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.928176865
Directory /workspace/11.spi_device_stress_all/latest


Test location /workspace/coverage/default/11.spi_device_tpm_all.3022033381
Short name T534
Test name
Test status
Simulation time 492492814 ps
CPU time 5.94 seconds
Started Aug 17 06:35:23 PM PDT 24
Finished Aug 17 06:35:29 PM PDT 24
Peak memory 220256 kb
Host smart-bacf605c-ad14-40ad-9a17-4747a0d194e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022033381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3022033381
Directory /workspace/11.spi_device_tpm_all/latest


Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2731977332
Short name T407
Test name
Test status
Simulation time 8489328436 ps
CPU time 9.11 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:35:40 PM PDT 24
Peak memory 217288 kb
Host smart-71f284fd-f550-4f0b-b76d-2fbc27e3e87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731977332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2731977332
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/11.spi_device_tpm_rw.2856629364
Short name T784
Test name
Test status
Simulation time 34475665 ps
CPU time 1.17 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 208992 kb
Host smart-65dbde05-e0a3-40ab-9039-4dbf8e13cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856629364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2856629364
Directory /workspace/11.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1595987817
Short name T851
Test name
Test status
Simulation time 71837475 ps
CPU time 0.8 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 206836 kb
Host smart-6cb03200-91a4-463e-9604-1af78abb1922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595987817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1595987817
Directory /workspace/11.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/11.spi_device_upload.621145885
Short name T618
Test name
Test status
Simulation time 22125521607 ps
CPU time 16.02 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:28 PM PDT 24
Peak memory 225516 kb
Host smart-015688a6-dc99-4dbb-966d-24ee33968c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621145885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.621145885
Directory /workspace/11.spi_device_upload/latest


Test location /workspace/coverage/default/12.spi_device_alert_test.2853220206
Short name T896
Test name
Test status
Simulation time 35659301 ps
CPU time 0.72 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:43 PM PDT 24
Peak memory 206300 kb
Host smart-afbf5636-13fe-4146-84fa-a439569cbef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853220206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2853220206
Directory /workspace/12.spi_device_alert_test/latest


Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1233525508
Short name T458
Test name
Test status
Simulation time 1033964536 ps
CPU time 12.25 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:35:51 PM PDT 24
Peak memory 225312 kb
Host smart-724496d5-4256-4b4b-b7d6-1682969f5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233525508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1233525508
Directory /workspace/12.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/12.spi_device_csb_read.1750113987
Short name T386
Test name
Test status
Simulation time 19083408 ps
CPU time 0.84 seconds
Started Aug 17 06:35:37 PM PDT 24
Finished Aug 17 06:35:38 PM PDT 24
Peak memory 206396 kb
Host smart-9e64a96c-8105-4fc2-abc3-335538316984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750113987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1750113987
Directory /workspace/12.spi_device_csb_read/latest


Test location /workspace/coverage/default/12.spi_device_flash_all.3979109596
Short name T793
Test name
Test status
Simulation time 73630908 ps
CPU time 0.78 seconds
Started Aug 17 06:35:32 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 216944 kb
Host smart-623c7f48-ee31-48e6-984f-31d43d6fe9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979109596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3979109596
Directory /workspace/12.spi_device_flash_all/latest


Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2267337871
Short name T309
Test name
Test status
Simulation time 2958364269 ps
CPU time 33.76 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 237716 kb
Host smart-65540e0f-d1c4-4386-9ab2-7e27d4697c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267337871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2267337871
Directory /workspace/12.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/12.spi_device_flash_mode.2479464187
Short name T325
Test name
Test status
Simulation time 1712142496 ps
CPU time 31.48 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:26 PM PDT 24
Peak memory 241792 kb
Host smart-d2aac537-b8d2-4b42-bd2f-05d8d9b249fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479464187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2479464187
Directory /workspace/12.spi_device_flash_mode/latest


Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2097571851
Short name T576
Test name
Test status
Simulation time 55378359635 ps
CPU time 160.09 seconds
Started Aug 17 06:35:40 PM PDT 24
Finished Aug 17 06:38:20 PM PDT 24
Peak memory 250132 kb
Host smart-6d7b824f-1f09-4942-8501-2e993ac2904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097571851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2097571851
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/12.spi_device_intercept.1202216068
Short name T565
Test name
Test status
Simulation time 157102126 ps
CPU time 2.82 seconds
Started Aug 17 06:35:24 PM PDT 24
Finished Aug 17 06:35:27 PM PDT 24
Peak memory 233612 kb
Host smart-dff1e1ba-1dc8-4dc2-8e86-03230a56dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202216068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1202216068
Directory /workspace/12.spi_device_intercept/latest


Test location /workspace/coverage/default/12.spi_device_mailbox.1776642208
Short name T664
Test name
Test status
Simulation time 200148431 ps
CPU time 3.22 seconds
Started Aug 17 06:35:32 PM PDT 24
Finished Aug 17 06:35:35 PM PDT 24
Peak memory 225352 kb
Host smart-956e12d1-2a19-420b-822e-d31ecd7c0aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776642208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1776642208
Directory /workspace/12.spi_device_mailbox/latest


Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1626255981
Short name T46
Test name
Test status
Simulation time 3038551399 ps
CPU time 5.72 seconds
Started Aug 17 06:35:47 PM PDT 24
Finished Aug 17 06:35:53 PM PDT 24
Peak memory 233724 kb
Host smart-6bde049e-ef31-4104-9023-f106954c0273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626255981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1626255981
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1110293708
Short name T1010
Test name
Test status
Simulation time 975276826 ps
CPU time 3 seconds
Started Aug 17 06:35:29 PM PDT 24
Finished Aug 17 06:35:32 PM PDT 24
Peak memory 225304 kb
Host smart-4ec90747-b32d-41c1-af0f-ee0d92b0a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110293708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1110293708
Directory /workspace/12.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.247605240
Short name T405
Test name
Test status
Simulation time 5657556838 ps
CPU time 6.27 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:35:37 PM PDT 24
Peak memory 220816 kb
Host smart-8e2fa18c-fc1e-4ac2-a185-0d11842d1cc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=247605240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.247605240
Directory /workspace/12.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/12.spi_device_stress_all.1518140492
Short name T310
Test name
Test status
Simulation time 54613878209 ps
CPU time 263.39 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:40:02 PM PDT 24
Peak memory 258396 kb
Host smart-619a76cc-664d-4489-9fd9-2852731035f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518140492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1518140492
Directory /workspace/12.spi_device_stress_all/latest


Test location /workspace/coverage/default/12.spi_device_tpm_all.560733377
Short name T991
Test name
Test status
Simulation time 4735079308 ps
CPU time 15.05 seconds
Started Aug 17 06:35:29 PM PDT 24
Finished Aug 17 06:35:44 PM PDT 24
Peak memory 220864 kb
Host smart-7e17f0ea-3de2-4b5a-b9e2-661e418dc8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560733377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.560733377
Directory /workspace/12.spi_device_tpm_all/latest


Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4228751810
Short name T674
Test name
Test status
Simulation time 29195124080 ps
CPU time 19.61 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 217252 kb
Host smart-89ce0597-1f03-4378-a725-e4d9d89390e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228751810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4228751810
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/12.spi_device_tpm_rw.446992551
Short name T940
Test name
Test status
Simulation time 36342106 ps
CPU time 0.69 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:48 PM PDT 24
Peak memory 206376 kb
Host smart-91ccb20a-0893-40b3-b486-64f04e99e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446992551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.446992551
Directory /workspace/12.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1530615338
Short name T350
Test name
Test status
Simulation time 67744757 ps
CPU time 0.95 seconds
Started Aug 17 06:35:36 PM PDT 24
Finished Aug 17 06:35:37 PM PDT 24
Peak memory 207904 kb
Host smart-4556a82c-b692-4149-8430-20b964fc4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530615338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1530615338
Directory /workspace/12.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/12.spi_device_upload.801925796
Short name T597
Test name
Test status
Simulation time 1013588996 ps
CPU time 7.1 seconds
Started Aug 17 06:35:25 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 225336 kb
Host smart-c7fa1070-2abf-4f54-9c82-d92b0535c89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801925796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.801925796
Directory /workspace/12.spi_device_upload/latest


Test location /workspace/coverage/default/13.spi_device_alert_test.855730038
Short name T849
Test name
Test status
Simulation time 23668727 ps
CPU time 0.72 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:39 PM PDT 24
Peak memory 205760 kb
Host smart-1adc752e-80aa-4943-a78c-404138cd7f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855730038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.855730038
Directory /workspace/13.spi_device_alert_test/latest


Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1031719702
Short name T419
Test name
Test status
Simulation time 267572418 ps
CPU time 3.1 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:46 PM PDT 24
Peak memory 225356 kb
Host smart-bd33c2d5-90fb-43b4-89c4-8baffa6003cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031719702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1031719702
Directory /workspace/13.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/13.spi_device_csb_read.427001176
Short name T588
Test name
Test status
Simulation time 36823436 ps
CPU time 0.83 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:39 PM PDT 24
Peak memory 207440 kb
Host smart-5284b246-0482-4211-aa0d-849a0ec43bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427001176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.427001176
Directory /workspace/13.spi_device_csb_read/latest


Test location /workspace/coverage/default/13.spi_device_flash_all.580448539
Short name T792
Test name
Test status
Simulation time 153684949530 ps
CPU time 289.64 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:40:28 PM PDT 24
Peak memory 250092 kb
Host smart-7c9c0a8e-3efd-4956-96d3-7760284c88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580448539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.580448539
Directory /workspace/13.spi_device_flash_all/latest


Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1978065752
Short name T57
Test name
Test status
Simulation time 80576905085 ps
CPU time 184.65 seconds
Started Aug 17 06:35:37 PM PDT 24
Finished Aug 17 06:38:42 PM PDT 24
Peak memory 250188 kb
Host smart-ce74bca8-f956-424e-9acf-d1eaa6151e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978065752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1978065752
Directory /workspace/13.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.930662554
Short name T798
Test name
Test status
Simulation time 146500232017 ps
CPU time 240.3 seconds
Started Aug 17 06:35:47 PM PDT 24
Finished Aug 17 06:39:47 PM PDT 24
Peak memory 272944 kb
Host smart-5baaa6b3-b3ef-4e20-8011-a0f333c0c63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930662554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.930662554
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/13.spi_device_flash_mode.3110675852
Short name T705
Test name
Test status
Simulation time 779771462 ps
CPU time 12.36 seconds
Started Aug 17 06:35:43 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 241580 kb
Host smart-3ef7289a-8f29-4b12-8338-c751b92b9631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110675852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3110675852
Directory /workspace/13.spi_device_flash_mode/latest


Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.220831451
Short name T171
Test name
Test status
Simulation time 67177877398 ps
CPU time 191.98 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:39:03 PM PDT 24
Peak memory 266144 kb
Host smart-87580e0c-5099-4cc0-b715-aeffce21dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220831451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.220831451
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/13.spi_device_intercept.2009737077
Short name T544
Test name
Test status
Simulation time 4321057338 ps
CPU time 4.8 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:43 PM PDT 24
Peak memory 233760 kb
Host smart-7a2a13fa-bf3c-44dd-b94f-7936f8439c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009737077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2009737077
Directory /workspace/13.spi_device_intercept/latest


Test location /workspace/coverage/default/13.spi_device_mailbox.740806756
Short name T179
Test name
Test status
Simulation time 23513913891 ps
CPU time 150.38 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 236464 kb
Host smart-bf71002a-ccb0-4671-97f0-47b236ab04d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740806756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.740806756
Directory /workspace/13.spi_device_mailbox/latest


Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.551702385
Short name T615
Test name
Test status
Simulation time 49318113 ps
CPU time 2.06 seconds
Started Aug 17 06:35:34 PM PDT 24
Finished Aug 17 06:35:36 PM PDT 24
Peak memory 224908 kb
Host smart-2290d12b-85c7-4770-82f1-91a35e24917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551702385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.551702385
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.328785737
Short name T695
Test name
Test status
Simulation time 3146651643 ps
CPU time 12.45 seconds
Started Aug 17 06:35:34 PM PDT 24
Finished Aug 17 06:35:47 PM PDT 24
Peak memory 225452 kb
Host smart-d98ca418-d0c2-4eb5-9fcd-2795772741f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328785737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.328785737
Directory /workspace/13.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3879855650
Short name T351
Test name
Test status
Simulation time 1846809221 ps
CPU time 8.04 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:47 PM PDT 24
Peak memory 221088 kb
Host smart-a8534581-0298-4b1e-98ca-76725e59145b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3879855650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3879855650
Directory /workspace/13.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/13.spi_device_stress_all.2244917326
Short name T764
Test name
Test status
Simulation time 42692908617 ps
CPU time 122.55 seconds
Started Aug 17 06:35:46 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 253336 kb
Host smart-8c07469f-d758-42a3-8d7a-510f957f85c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244917326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2244917326
Directory /workspace/13.spi_device_stress_all/latest


Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2640802485
Short name T479
Test name
Test status
Simulation time 2254703199 ps
CPU time 6.49 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:41 PM PDT 24
Peak memory 217356 kb
Host smart-75a9086f-b2c7-45cf-bee6-fcc2185d75fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640802485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2640802485
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/13.spi_device_tpm_rw.4161880996
Short name T608
Test name
Test status
Simulation time 586947153 ps
CPU time 1.92 seconds
Started Aug 17 06:35:24 PM PDT 24
Finished Aug 17 06:35:26 PM PDT 24
Peak memory 217204 kb
Host smart-38c00230-498e-4355-bcfb-a4c8a9bc8e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161880996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4161880996
Directory /workspace/13.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.174272375
Short name T654
Test name
Test status
Simulation time 43797408 ps
CPU time 0.7 seconds
Started Aug 17 06:35:30 PM PDT 24
Finished Aug 17 06:35:31 PM PDT 24
Peak memory 206848 kb
Host smart-2bc1e7b3-028d-49de-9cce-11156a04b434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174272375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.174272375
Directory /workspace/13.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/13.spi_device_upload.2343630048
Short name T492
Test name
Test status
Simulation time 11571650122 ps
CPU time 9.19 seconds
Started Aug 17 06:35:40 PM PDT 24
Finished Aug 17 06:35:49 PM PDT 24
Peak memory 233708 kb
Host smart-cc62cb23-caf3-4166-ad35-9cd33c172229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343630048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2343630048
Directory /workspace/13.spi_device_upload/latest


Test location /workspace/coverage/default/14.spi_device_alert_test.3300861741
Short name T799
Test name
Test status
Simulation time 11321192 ps
CPU time 0.71 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:36 PM PDT 24
Peak memory 206584 kb
Host smart-0330fb44-1639-42c7-b1fa-5d5f85165410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300861741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3300861741
Directory /workspace/14.spi_device_alert_test/latest


Test location /workspace/coverage/default/14.spi_device_cfg_cmd.469069375
Short name T97
Test name
Test status
Simulation time 102346122 ps
CPU time 2.24 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:35:51 PM PDT 24
Peak memory 225384 kb
Host smart-227ac9e3-738f-4509-9848-d0c8cdc5b941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469069375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.469069375
Directory /workspace/14.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/14.spi_device_csb_read.2711025734
Short name T473
Test name
Test status
Simulation time 29045078 ps
CPU time 0.8 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:35:39 PM PDT 24
Peak memory 206396 kb
Host smart-34d282e9-51fb-48ef-a50f-4720a9ec1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711025734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2711025734
Directory /workspace/14.spi_device_csb_read/latest


Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.854127455
Short name T750
Test name
Test status
Simulation time 7879777910 ps
CPU time 116.2 seconds
Started Aug 17 06:35:48 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 266492 kb
Host smart-74157582-9809-42f8-b1de-07af8adbdb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854127455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.854127455
Directory /workspace/14.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2129757951
Short name T684
Test name
Test status
Simulation time 240018562697 ps
CPU time 243.76 seconds
Started Aug 17 06:35:47 PM PDT 24
Finished Aug 17 06:39:51 PM PDT 24
Peak memory 252604 kb
Host smart-46f61a81-cd3d-4364-9da8-ebd2b9c1de36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129757951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2129757951
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/14.spi_device_flash_mode.4110057199
Short name T831
Test name
Test status
Simulation time 2747701688 ps
CPU time 39.86 seconds
Started Aug 17 06:35:48 PM PDT 24
Finished Aug 17 06:36:28 PM PDT 24
Peak memory 249968 kb
Host smart-a7eb8bcf-9620-4840-b6be-db7042fa75d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110057199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4110057199
Directory /workspace/14.spi_device_flash_mode/latest


Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3638849868
Short name T228
Test name
Test status
Simulation time 29935548769 ps
CPU time 75.25 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 252644 kb
Host smart-b73018a0-b006-4851-9d9e-acf98aa5d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638849868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3638849868
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/14.spi_device_intercept.3283776306
Short name T920
Test name
Test status
Simulation time 454296956 ps
CPU time 2.94 seconds
Started Aug 17 06:35:47 PM PDT 24
Finished Aug 17 06:35:50 PM PDT 24
Peak memory 225296 kb
Host smart-7f58885a-1b7c-4a0c-a69e-f9d33db92222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283776306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3283776306
Directory /workspace/14.spi_device_intercept/latest


Test location /workspace/coverage/default/14.spi_device_mailbox.3986919931
Short name T496
Test name
Test status
Simulation time 14738228908 ps
CPU time 64.08 seconds
Started Aug 17 06:35:38 PM PDT 24
Finished Aug 17 06:36:42 PM PDT 24
Peak memory 225440 kb
Host smart-748e1df3-47c0-4a06-a2bc-ee6aafdbeeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986919931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3986919931
Directory /workspace/14.spi_device_mailbox/latest


Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.236254339
Short name T278
Test name
Test status
Simulation time 2832179917 ps
CPU time 5.18 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:35:44 PM PDT 24
Peak memory 233708 kb
Host smart-60a6d036-e5df-4f37-befe-fb5d809b76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236254339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.236254339
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1715204075
Short name T977
Test name
Test status
Simulation time 561433849 ps
CPU time 2.77 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:38 PM PDT 24
Peak memory 225404 kb
Host smart-6490500f-d285-4cf4-8b5f-916d4244e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715204075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1715204075
Directory /workspace/14.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.339314532
Short name T522
Test name
Test status
Simulation time 547590767 ps
CPU time 8.71 seconds
Started Aug 17 06:35:44 PM PDT 24
Finished Aug 17 06:35:53 PM PDT 24
Peak memory 223864 kb
Host smart-23899a8c-d01f-4ade-83f5-380374a487d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=339314532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.339314532
Directory /workspace/14.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/14.spi_device_tpm_all.128168554
Short name T560
Test name
Test status
Simulation time 3902074383 ps
CPU time 28.57 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 217668 kb
Host smart-a017b945-4952-4f3d-9ca7-a1f9a592440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128168554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.128168554
Directory /workspace/14.spi_device_tpm_all/latest


Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4210522299
Short name T579
Test name
Test status
Simulation time 843130970 ps
CPU time 5.84 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:35:45 PM PDT 24
Peak memory 217216 kb
Host smart-3ce2792d-11e4-445e-b10a-a62cbe63be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210522299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4210522299
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/14.spi_device_tpm_rw.3503266126
Short name T428
Test name
Test status
Simulation time 225022641 ps
CPU time 1.98 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:37 PM PDT 24
Peak memory 217232 kb
Host smart-6d28eaec-a793-4453-8a19-1874ad6f1916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503266126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3503266126
Directory /workspace/14.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1642612890
Short name T621
Test name
Test status
Simulation time 67657982 ps
CPU time 0.8 seconds
Started Aug 17 06:35:32 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 206816 kb
Host smart-6d194095-204e-4eed-ad98-4a9ef1bc5492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642612890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1642612890
Directory /workspace/14.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/14.spi_device_upload.1291725059
Short name T163
Test name
Test status
Simulation time 1351062902 ps
CPU time 6.38 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:49 PM PDT 24
Peak memory 225360 kb
Host smart-49bbbeab-9f39-45ec-8da4-5930fd33fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291725059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1291725059
Directory /workspace/14.spi_device_upload/latest


Test location /workspace/coverage/default/15.spi_device_alert_test.2275820565
Short name T652
Test name
Test status
Simulation time 46721956 ps
CPU time 0.76 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 206244 kb
Host smart-e3595c63-351c-4b56-9b5b-8eb9beb32226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275820565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2275820565
Directory /workspace/15.spi_device_alert_test/latest


Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1963565865
Short name T901
Test name
Test status
Simulation time 1083591879 ps
CPU time 6.94 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:49 PM PDT 24
Peak memory 233520 kb
Host smart-3e71e86f-04c1-49b3-a436-5cff8e28bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963565865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1963565865
Directory /workspace/15.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/15.spi_device_csb_read.4265755443
Short name T748
Test name
Test status
Simulation time 18564684 ps
CPU time 0.79 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 207604 kb
Host smart-0c6bb3b9-dbdf-48d5-8ee0-58316749c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265755443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4265755443
Directory /workspace/15.spi_device_csb_read/latest


Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3333009878
Short name T913
Test name
Test status
Simulation time 12738691650 ps
CPU time 208.86 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:39:18 PM PDT 24
Peak memory 274416 kb
Host smart-0e69e1f7-0fe3-4fb4-8555-3e7c59db9876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333009878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3333009878
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/15.spi_device_flash_mode.3386686841
Short name T859
Test name
Test status
Simulation time 47589704 ps
CPU time 3.1 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 233584 kb
Host smart-2a730726-6afd-4397-8abc-250c06c38b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386686841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3386686841
Directory /workspace/15.spi_device_flash_mode/latest


Test location /workspace/coverage/default/15.spi_device_intercept.873118733
Short name T982
Test name
Test status
Simulation time 211107824 ps
CPU time 2.84 seconds
Started Aug 17 06:35:40 PM PDT 24
Finished Aug 17 06:35:43 PM PDT 24
Peak memory 233632 kb
Host smart-61fe1a02-d0fb-45e9-abc0-74f2520843f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873118733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.873118733
Directory /workspace/15.spi_device_intercept/latest


Test location /workspace/coverage/default/15.spi_device_mailbox.1542763814
Short name T727
Test name
Test status
Simulation time 76706390 ps
CPU time 2.27 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:57 PM PDT 24
Peak memory 223888 kb
Host smart-e612a02f-60b2-433b-b806-d1b946b41664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542763814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1542763814
Directory /workspace/15.spi_device_mailbox/latest


Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4278941104
Short name T282
Test name
Test status
Simulation time 6166604513 ps
CPU time 6.97 seconds
Started Aug 17 06:35:40 PM PDT 24
Finished Aug 17 06:35:47 PM PDT 24
Peak memory 225452 kb
Host smart-109e2881-f4eb-4f60-b67b-a3c263e59280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278941104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4278941104
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.899480735
Short name T976
Test name
Test status
Simulation time 2005448846 ps
CPU time 6.95 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:49 PM PDT 24
Peak memory 241684 kb
Host smart-48e2feb3-41d9-4e0b-bd2f-b5665bbc846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899480735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.899480735
Directory /workspace/15.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.970592233
Short name T361
Test name
Test status
Simulation time 15595853096 ps
CPU time 13.52 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 222508 kb
Host smart-cd7ad3da-64c6-4fe1-9313-f0a2fa4b490a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=970592233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.970592233
Directory /workspace/15.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/15.spi_device_stress_all.380505149
Short name T847
Test name
Test status
Simulation time 30989459314 ps
CPU time 132.86 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 241032 kb
Host smart-1997efac-edea-4880-95e2-9507e8887fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380505149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.380505149
Directory /workspace/15.spi_device_stress_all/latest


Test location /workspace/coverage/default/15.spi_device_tpm_all.2637547194
Short name T520
Test name
Test status
Simulation time 2251323128 ps
CPU time 13.72 seconds
Started Aug 17 06:35:46 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 217284 kb
Host smart-8c69a4e1-90ac-4de6-a8b3-a86d3927ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637547194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2637547194
Directory /workspace/15.spi_device_tpm_all/latest


Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3796446047
Short name T747
Test name
Test status
Simulation time 5620844210 ps
CPU time 9.54 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:35:49 PM PDT 24
Peak memory 217352 kb
Host smart-5013d7e9-3a9d-4e70-9c4d-878ae1fb790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796446047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3796446047
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/15.spi_device_tpm_rw.644731383
Short name T556
Test name
Test status
Simulation time 166317179 ps
CPU time 3.05 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 217084 kb
Host smart-c7c8cfe5-9427-43d5-b90e-bea38e37828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644731383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.644731383
Directory /workspace/15.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.409001593
Short name T915
Test name
Test status
Simulation time 56325753 ps
CPU time 0.71 seconds
Started Aug 17 06:35:44 PM PDT 24
Finished Aug 17 06:35:45 PM PDT 24
Peak memory 206844 kb
Host smart-49476b10-e5a7-4c14-83c3-a806a960b6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409001593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.409001593
Directory /workspace/15.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/15.spi_device_upload.2047030200
Short name T49
Test name
Test status
Simulation time 2157287846 ps
CPU time 9.23 seconds
Started Aug 17 06:35:46 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 225464 kb
Host smart-a4c3e8ee-f93b-4e1f-a2b9-1a1d45aa4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047030200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2047030200
Directory /workspace/15.spi_device_upload/latest


Test location /workspace/coverage/default/16.spi_device_alert_test.706823457
Short name T422
Test name
Test status
Simulation time 42710057 ps
CPU time 0.75 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 205700 kb
Host smart-94397f35-a52e-4182-b48b-68c57062e35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706823457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.706823457
Directory /workspace/16.spi_device_alert_test/latest


Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1260606374
Short name T371
Test name
Test status
Simulation time 339474152 ps
CPU time 3.87 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 225412 kb
Host smart-5950ec6b-3b40-4805-ae41-c5d54c84d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260606374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1260606374
Directory /workspace/16.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/16.spi_device_csb_read.952851856
Short name T376
Test name
Test status
Simulation time 26512830 ps
CPU time 0.81 seconds
Started Aug 17 06:35:40 PM PDT 24
Finished Aug 17 06:35:41 PM PDT 24
Peak memory 207440 kb
Host smart-f7f74fbf-127c-4f9b-b8ea-b86020435484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952851856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.952851856
Directory /workspace/16.spi_device_csb_read/latest


Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2507134522
Short name T791
Test name
Test status
Simulation time 5730824363 ps
CPU time 77.29 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 258432 kb
Host smart-a93e7ade-239d-4148-acb4-0bd5b8cc994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507134522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2507134522
Directory /workspace/16.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2143593153
Short name T985
Test name
Test status
Simulation time 18150585500 ps
CPU time 61.08 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 240324 kb
Host smart-84a10c50-8a4a-47c3-bca9-acca3dd0e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143593153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2143593153
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/16.spi_device_flash_mode.887051590
Short name T435
Test name
Test status
Simulation time 39460334 ps
CPU time 2.55 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 233564 kb
Host smart-e9f7e485-3e45-49b9-a28a-76ca1f79e1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887051590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.887051590
Directory /workspace/16.spi_device_flash_mode/latest


Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.658821751
Short name T753
Test name
Test status
Simulation time 15725145736 ps
CPU time 91.25 seconds
Started Aug 17 06:35:39 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 266340 kb
Host smart-bdf94ed1-36d8-4433-b5ea-7c7448c71844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658821751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.658821751
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/16.spi_device_intercept.729030879
Short name T986
Test name
Test status
Simulation time 5105497546 ps
CPU time 19.74 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 225364 kb
Host smart-729a9bb2-ac3d-474f-8c5f-2ce3b97dc375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729030879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.729030879
Directory /workspace/16.spi_device_intercept/latest


Test location /workspace/coverage/default/16.spi_device_mailbox.2264147910
Short name T37
Test name
Test status
Simulation time 3561567444 ps
CPU time 14.89 seconds
Started Aug 17 06:35:41 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 233724 kb
Host smart-da475f53-6e3c-4563-93d2-e2c81107852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264147910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2264147910
Directory /workspace/16.spi_device_mailbox/latest


Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2355928506
Short name T881
Test name
Test status
Simulation time 9017157643 ps
CPU time 22.6 seconds
Started Aug 17 06:35:47 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 225432 kb
Host smart-7b913de5-1571-4436-987f-6eecbf81a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355928506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2355928506
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1587592054
Short name T968
Test name
Test status
Simulation time 616815402 ps
CPU time 3.78 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 225356 kb
Host smart-f0cd65e3-16e6-4d8b-95f1-292b92a9eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587592054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1587592054
Directory /workspace/16.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.322952114
Short name T132
Test name
Test status
Simulation time 219000163 ps
CPU time 4.43 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 225120 kb
Host smart-b0075c23-a35a-4d61-a651-afeed599462f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=322952114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.322952114
Directory /workspace/16.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/16.spi_device_stress_all.1682241149
Short name T884
Test name
Test status
Simulation time 56793861549 ps
CPU time 114.43 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 250920 kb
Host smart-4ee7ac34-8115-4ffa-b08c-53be207c3202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682241149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1682241149
Directory /workspace/16.spi_device_stress_all/latest


Test location /workspace/coverage/default/16.spi_device_tpm_all.489756666
Short name T329
Test name
Test status
Simulation time 7050702517 ps
CPU time 28.73 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 221196 kb
Host smart-4df7cc00-c276-4a54-963e-53397b163267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489756666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.489756666
Directory /workspace/16.spi_device_tpm_all/latest


Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2986324563
Short name T466
Test name
Test status
Simulation time 2233486394 ps
CPU time 4.08 seconds
Started Aug 17 06:35:43 PM PDT 24
Finished Aug 17 06:35:47 PM PDT 24
Peak memory 217296 kb
Host smart-bd9b1dc9-ecf0-4bb8-9d0c-ce37b5aa9bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986324563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2986324563
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/16.spi_device_tpm_rw.2901787465
Short name T907
Test name
Test status
Simulation time 154357791 ps
CPU time 5.6 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 217132 kb
Host smart-6f9ba6bd-1a17-4a24-b832-193ba7a0fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901787465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2901787465
Directory /workspace/16.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1294134127
Short name T385
Test name
Test status
Simulation time 62164641 ps
CPU time 0.71 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 206788 kb
Host smart-f9d74db4-00c5-4139-8152-c946edd2d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294134127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1294134127
Directory /workspace/16.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/16.spi_device_upload.995396554
Short name T232
Test name
Test status
Simulation time 1844684919 ps
CPU time 5.03 seconds
Started Aug 17 06:35:48 PM PDT 24
Finished Aug 17 06:35:53 PM PDT 24
Peak memory 233616 kb
Host smart-08b910e3-6308-4082-89ce-c150b06b3d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995396554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.995396554
Directory /workspace/16.spi_device_upload/latest


Test location /workspace/coverage/default/17.spi_device_alert_test.3523659823
Short name T971
Test name
Test status
Simulation time 30174182 ps
CPU time 0.7 seconds
Started Aug 17 06:35:50 PM PDT 24
Finished Aug 17 06:35:51 PM PDT 24
Peak memory 206248 kb
Host smart-0f732240-3b7b-429b-944e-f8d015049fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523659823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3523659823
Directory /workspace/17.spi_device_alert_test/latest


Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3842304483
Short name T491
Test name
Test status
Simulation time 2228654067 ps
CPU time 12.21 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 233728 kb
Host smart-5ead9a8d-1eef-432c-a410-ea1684e48d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842304483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3842304483
Directory /workspace/17.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/17.spi_device_csb_read.849149780
Short name T820
Test name
Test status
Simulation time 45616370 ps
CPU time 0.77 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 207412 kb
Host smart-7db104b0-9728-4780-8705-5970f705f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849149780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.849149780
Directory /workspace/17.spi_device_csb_read/latest


Test location /workspace/coverage/default/17.spi_device_flash_all.430960303
Short name T604
Test name
Test status
Simulation time 25094517228 ps
CPU time 178.71 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:38:48 PM PDT 24
Peak memory 256572 kb
Host smart-55ad9851-3a67-4ad4-95bf-2b1eacf9b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430960303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.430960303
Directory /workspace/17.spi_device_flash_all/latest


Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1411778833
Short name T712
Test name
Test status
Simulation time 11350200399 ps
CPU time 34.01 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:30 PM PDT 24
Peak memory 239244 kb
Host smart-d044d43a-57bc-41b1-98e5-cdc2362dff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411778833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1411778833
Directory /workspace/17.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2298795252
Short name T524
Test name
Test status
Simulation time 94872434999 ps
CPU time 230.32 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:39:44 PM PDT 24
Peak memory 254608 kb
Host smart-5e8c700e-02e5-42e5-b0ee-51f5b5bf002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298795252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2298795252
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/17.spi_device_flash_mode.3070010285
Short name T316
Test name
Test status
Simulation time 1401917647 ps
CPU time 6.87 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 249956 kb
Host smart-6594cbf8-0e03-486b-8c82-4cbb47b8f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070010285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3070010285
Directory /workspace/17.spi_device_flash_mode/latest


Test location /workspace/coverage/default/17.spi_device_intercept.3960166759
Short name T485
Test name
Test status
Simulation time 434082848 ps
CPU time 8.72 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 233628 kb
Host smart-2414515a-e89e-406b-a0f1-eb716a0f28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960166759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3960166759
Directory /workspace/17.spi_device_intercept/latest


Test location /workspace/coverage/default/17.spi_device_mailbox.3699913104
Short name T493
Test name
Test status
Simulation time 1630787407 ps
CPU time 22.41 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:36:16 PM PDT 24
Peak memory 249688 kb
Host smart-59d57749-8380-4567-8112-7fbe74dec5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699913104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3699913104
Directory /workspace/17.spi_device_mailbox/latest


Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1182703802
Short name T246
Test name
Test status
Simulation time 2265587879 ps
CPU time 8.6 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 233644 kb
Host smart-f327402c-77a5-4b9d-ab3a-32d35e216084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182703802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1182703802
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2217528462
Short name T208
Test name
Test status
Simulation time 7848205250 ps
CPU time 9.52 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 225448 kb
Host smart-12ae5a36-4dce-4f91-a5e9-687379894a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217528462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2217528462
Directory /workspace/17.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.954510000
Short name T956
Test name
Test status
Simulation time 749662960 ps
CPU time 3.53 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 224084 kb
Host smart-c9fd5d38-bb2c-4377-a6d4-37dd04e279ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=954510000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.954510000
Directory /workspace/17.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/17.spi_device_stress_all.2622636861
Short name T893
Test name
Test status
Simulation time 34127308411 ps
CPU time 64.63 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 234744 kb
Host smart-8307a3ad-777e-4e42-b3b8-48daae017993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622636861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2622636861
Directory /workspace/17.spi_device_stress_all/latest


Test location /workspace/coverage/default/17.spi_device_tpm_all.2223084187
Short name T416
Test name
Test status
Simulation time 4251229024 ps
CPU time 20.71 seconds
Started Aug 17 06:35:52 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 217484 kb
Host smart-4f6a1f69-60dd-48c2-961f-37a40e1b8056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223084187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2223084187
Directory /workspace/17.spi_device_tpm_all/latest


Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1436566932
Short name T487
Test name
Test status
Simulation time 6224717728 ps
CPU time 11.21 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 217300 kb
Host smart-889702c0-02db-4569-bf23-be459b4664f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436566932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1436566932
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/17.spi_device_tpm_rw.4063505782
Short name T770
Test name
Test status
Simulation time 17058856 ps
CPU time 0.86 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 207504 kb
Host smart-d1e140d4-a0c5-4177-8e92-f9e1e5e9e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063505782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4063505782
Directory /workspace/17.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.945098721
Short name T970
Test name
Test status
Simulation time 96144857 ps
CPU time 1.01 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 207332 kb
Host smart-af7651d9-a417-48b1-b808-7042d8ece664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945098721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.945098721
Directory /workspace/17.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/17.spi_device_upload.2256468360
Short name T656
Test name
Test status
Simulation time 808316138 ps
CPU time 4.41 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 225380 kb
Host smart-c32fbeb3-d3d9-4c8c-bb51-b025b6ed0779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256468360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2256468360
Directory /workspace/17.spi_device_upload/latest


Test location /workspace/coverage/default/18.spi_device_alert_test.2697131004
Short name T515
Test name
Test status
Simulation time 39419614 ps
CPU time 0.72 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 205624 kb
Host smart-bd053fd2-c6c1-4126-a425-2e9b772e4ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697131004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2697131004
Directory /workspace/18.spi_device_alert_test/latest


Test location /workspace/coverage/default/18.spi_device_cfg_cmd.197540870
Short name T721
Test name
Test status
Simulation time 1312134057 ps
CPU time 15.56 seconds
Started Aug 17 06:35:46 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 225300 kb
Host smart-92a43f2c-e461-4980-8b30-f5cc7fe9963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197540870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.197540870
Directory /workspace/18.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/18.spi_device_csb_read.1104258809
Short name T30
Test name
Test status
Simulation time 36729006 ps
CPU time 0.76 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 206400 kb
Host smart-15d73558-c9ef-4672-8988-a1e9d00d3102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104258809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1104258809
Directory /workspace/18.spi_device_csb_read/latest


Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.690721133
Short name T716
Test name
Test status
Simulation time 2550313241 ps
CPU time 23.66 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 218796 kb
Host smart-391d0221-7d30-435a-bddc-65a4ff8cda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690721133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.690721133
Directory /workspace/18.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1423613320
Short name T994
Test name
Test status
Simulation time 13220258217 ps
CPU time 123.8 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 241156 kb
Host smart-3455066d-435f-4956-bae1-06657d39ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423613320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1423613320
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/18.spi_device_flash_mode.3102279783
Short name T946
Test name
Test status
Simulation time 4291393560 ps
CPU time 22.93 seconds
Started Aug 17 06:35:45 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 225508 kb
Host smart-50fe1988-b060-4566-adb7-e82323d2dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102279783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3102279783
Directory /workspace/18.spi_device_flash_mode/latest


Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.299432489
Short name T51
Test name
Test status
Simulation time 129067496828 ps
CPU time 259.85 seconds
Started Aug 17 06:35:45 PM PDT 24
Finished Aug 17 06:40:05 PM PDT 24
Peak memory 257520 kb
Host smart-6955abfc-18c9-4e2c-98ea-f8362cd9c50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299432489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.299432489
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/18.spi_device_intercept.195148544
Short name T865
Test name
Test status
Simulation time 564104861 ps
CPU time 4.83 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 225312 kb
Host smart-bdd2a548-a15d-44b9-8525-24e8a97cee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195148544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.195148544
Directory /workspace/18.spi_device_intercept/latest


Test location /workspace/coverage/default/18.spi_device_mailbox.2380918444
Short name T541
Test name
Test status
Simulation time 1404376327 ps
CPU time 9.98 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 233620 kb
Host smart-20d94c46-0fcd-43a2-962b-1345fa3a45f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380918444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2380918444
Directory /workspace/18.spi_device_mailbox/latest


Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1961672268
Short name T722
Test name
Test status
Simulation time 1551563074 ps
CPU time 2.35 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 225296 kb
Host smart-adab4461-0049-416a-87a4-5fbcfd0ed56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961672268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1961672268
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1239402043
Short name T620
Test name
Test status
Simulation time 7041153261 ps
CPU time 5.75 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 225384 kb
Host smart-0753ebcc-a6a1-4315-aceb-1a4b67c0bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239402043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1239402043
Directory /workspace/18.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1337047332
Short name T145
Test name
Test status
Simulation time 6683919586 ps
CPU time 18.77 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 220952 kb
Host smart-03873bc5-10a9-4bab-beb4-df04fb8e0e10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1337047332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1337047332
Directory /workspace/18.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/18.spi_device_stress_all.2006269404
Short name T162
Test name
Test status
Simulation time 173018051368 ps
CPU time 462.3 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:43:46 PM PDT 24
Peak memory 274088 kb
Host smart-d02ddadc-6040-4cde-80ef-689a475897bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006269404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2006269404
Directory /workspace/18.spi_device_stress_all/latest


Test location /workspace/coverage/default/18.spi_device_tpm_all.1827227621
Short name T693
Test name
Test status
Simulation time 13901771 ps
CPU time 0.73 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 206532 kb
Host smart-6640470c-7f96-4fb2-af20-680602422df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827227621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1827227621
Directory /workspace/18.spi_device_tpm_all/latest


Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1257147859
Short name T601
Test name
Test status
Simulation time 5398740357 ps
CPU time 8.07 seconds
Started Aug 17 06:35:50 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 217228 kb
Host smart-d9b3a337-c382-4070-8d2e-6b1d02197e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257147859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1257147859
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/18.spi_device_tpm_rw.3668328383
Short name T589
Test name
Test status
Simulation time 118922453 ps
CPU time 1.43 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:44 PM PDT 24
Peak memory 217080 kb
Host smart-6c489677-551b-4bdc-a35f-89e1b413323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668328383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3668328383
Directory /workspace/18.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1371868331
Short name T420
Test name
Test status
Simulation time 83466966 ps
CPU time 0.94 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 206772 kb
Host smart-69a4e2c5-cdab-419c-9033-781000b3883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371868331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1371868331
Directory /workspace/18.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/18.spi_device_upload.1294141854
Short name T619
Test name
Test status
Simulation time 17292099572 ps
CPU time 10.48 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 233712 kb
Host smart-ffab538b-ad1e-43da-ba6c-b5b453e9246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294141854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1294141854
Directory /workspace/18.spi_device_upload/latest


Test location /workspace/coverage/default/19.spi_device_alert_test.3581668565
Short name T408
Test name
Test status
Simulation time 15905076 ps
CPU time 0.73 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 205460 kb
Host smart-f019b3c2-c081-4f07-b931-403a5ae1d5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581668565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3581668565
Directory /workspace/19.spi_device_alert_test/latest


Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3452524397
Short name T934
Test name
Test status
Simulation time 59246423 ps
CPU time 2.99 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 233568 kb
Host smart-9bc6df39-fa1c-4543-b759-7c5f08f351b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452524397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3452524397
Directory /workspace/19.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/19.spi_device_csb_read.3886106650
Short name T665
Test name
Test status
Simulation time 38132580 ps
CPU time 0.77 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 206388 kb
Host smart-2b34154d-0436-4492-a283-80b601845a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886106650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3886106650
Directory /workspace/19.spi_device_csb_read/latest


Test location /workspace/coverage/default/19.spi_device_flash_all.166371380
Short name T675
Test name
Test status
Simulation time 58748315085 ps
CPU time 103.98 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 252784 kb
Host smart-c3cb1bc6-5164-45c7-bc5b-c086a4e06501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166371380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.166371380
Directory /workspace/19.spi_device_flash_all/latest


Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1098353831
Short name T613
Test name
Test status
Simulation time 26693438180 ps
CPU time 282.28 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:40:39 PM PDT 24
Peak memory 266600 kb
Host smart-fb3305b2-4c6a-4f4a-9623-1261c3db26e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098353831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1098353831
Directory /workspace/19.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2004292442
Short name T178
Test name
Test status
Simulation time 1203911185 ps
CPU time 15.26 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 233596 kb
Host smart-f28b26c0-907c-4e31-8583-63b1baaaceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004292442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2004292442
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/19.spi_device_flash_mode.2729135129
Short name T868
Test name
Test status
Simulation time 7453374673 ps
CPU time 15.15 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 236576 kb
Host smart-6ba98073-5f95-4be2-bd0e-92cd31004a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729135129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2729135129
Directory /workspace/19.spi_device_flash_mode/latest


Test location /workspace/coverage/default/19.spi_device_intercept.2169966082
Short name T495
Test name
Test status
Simulation time 860022297 ps
CPU time 4.35 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 230632 kb
Host smart-0231bc98-943f-4d0f-87f7-a72bbbc0a68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169966082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2169966082
Directory /workspace/19.spi_device_intercept/latest


Test location /workspace/coverage/default/19.spi_device_mailbox.1884957239
Short name T264
Test name
Test status
Simulation time 95753332 ps
CPU time 3.12 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 233616 kb
Host smart-04a0af48-001a-48ea-a961-c5c08a7d4fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884957239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1884957239
Directory /workspace/19.spi_device_mailbox/latest


Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3580015724
Short name T77
Test name
Test status
Simulation time 123647429 ps
CPU time 2.51 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 233268 kb
Host smart-9750dcf9-105c-425d-812d-38a6cee698b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580015724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3580015724
Directory /workspace/19.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1489881068
Short name T869
Test name
Test status
Simulation time 564901122 ps
CPU time 3.77 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:57 PM PDT 24
Peak memory 219700 kb
Host smart-ed96ce70-fa3e-42e0-9c9a-8cbf23d12968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1489881068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1489881068
Directory /workspace/19.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/19.spi_device_tpm_all.2138406596
Short name T858
Test name
Test status
Simulation time 23973753750 ps
CPU time 34.37 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:28 PM PDT 24
Peak memory 217556 kb
Host smart-f33edd17-d212-46e1-884e-75091d1d1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138406596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2138406596
Directory /workspace/19.spi_device_tpm_all/latest


Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4028139340
Short name T682
Test name
Test status
Simulation time 1380859206 ps
CPU time 7.32 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 217004 kb
Host smart-1f75831e-d631-449d-ab2b-e40cda083857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028139340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4028139340
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/19.spi_device_tpm_rw.698551266
Short name T474
Test name
Test status
Simulation time 189681889 ps
CPU time 1.5 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:55 PM PDT 24
Peak memory 217220 kb
Host smart-0a7f5f39-f286-4771-a4a5-454c2d3748ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698551266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.698551266
Directory /workspace/19.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4033717319
Short name T910
Test name
Test status
Simulation time 66037162 ps
CPU time 0.81 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 206852 kb
Host smart-5185f7db-810e-4bbb-8234-2bb22f666b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033717319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4033717319
Directory /workspace/19.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/19.spi_device_upload.2260916881
Short name T455
Test name
Test status
Simulation time 1265750504 ps
CPU time 10.97 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 241284 kb
Host smart-e6e9b3d5-7fea-498c-a00a-7176b27e8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260916881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2260916881
Directory /workspace/19.spi_device_upload/latest


Test location /workspace/coverage/default/2.spi_device_alert_test.3096001612
Short name T366
Test name
Test status
Simulation time 20612369 ps
CPU time 0.71 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 206208 kb
Host smart-6d771c5f-2ade-4bbb-a308-519d71c781a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096001612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
096001612
Directory /workspace/2.spi_device_alert_test/latest


Test location /workspace/coverage/default/2.spi_device_cfg_cmd.573712213
Short name T649
Test name
Test status
Simulation time 102630204 ps
CPU time 2.56 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:37 PM PDT 24
Peak memory 225380 kb
Host smart-6ae0541d-6915-4587-9142-4ce0f0b61d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573712213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.573712213
Directory /workspace/2.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/2.spi_device_csb_read.3954833236
Short name T699
Test name
Test status
Simulation time 37740264 ps
CPU time 0.79 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 207452 kb
Host smart-e1352158-030d-44a2-9290-2224d1f1f7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954833236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3954833236
Directory /workspace/2.spi_device_csb_read/latest


Test location /workspace/coverage/default/2.spi_device_flash_all.3385049852
Short name T476
Test name
Test status
Simulation time 71399045805 ps
CPU time 117.07 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 253432 kb
Host smart-2fa77eff-9f2a-4914-8a82-63c2a5c6f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385049852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3385049852
Directory /workspace/2.spi_device_flash_all/latest


Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3285730861
Short name T31
Test name
Test status
Simulation time 9552730519 ps
CPU time 46.74 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:43 PM PDT 24
Peak memory 241772 kb
Host smart-c4aad6c9-8441-43f0-a81b-9d55ca62b3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285730861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3285730861
Directory /workspace/2.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.217029635
Short name T736
Test name
Test status
Simulation time 287999020838 ps
CPU time 138.62 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:37:20 PM PDT 24
Peak memory 252968 kb
Host smart-da0aa442-224e-4b05-9dd1-138c4340eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217029635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
217029635
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/2.spi_device_flash_mode.3020969934
Short name T131
Test name
Test status
Simulation time 75481509 ps
CPU time 3.89 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 225344 kb
Host smart-4014c6ec-f3de-476a-b94d-2a3b269c3480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020969934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3020969934
Directory /workspace/2.spi_device_flash_mode/latest


Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3493731373
Short name T54
Test name
Test status
Simulation time 5546007438 ps
CPU time 38.31 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:50 PM PDT 24
Peak memory 241824 kb
Host smart-26ab484f-0091-4381-a92b-ed80cdd82338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493731373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3493731373
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/2.spi_device_intercept.1394735297
Short name T673
Test name
Test status
Simulation time 689530318 ps
CPU time 4.24 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 225344 kb
Host smart-c0ed0fca-d6fd-4847-a155-2dfa7b2a88b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394735297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1394735297
Directory /workspace/2.spi_device_intercept/latest


Test location /workspace/coverage/default/2.spi_device_mailbox.2920372788
Short name T819
Test name
Test status
Simulation time 17824737029 ps
CPU time 10.37 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 225384 kb
Host smart-11bf7b39-dfd0-4b4a-931c-2f728321da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920372788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2920372788
Directory /workspace/2.spi_device_mailbox/latest


Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1504549374
Short name T782
Test name
Test status
Simulation time 802878520 ps
CPU time 4.8 seconds
Started Aug 17 06:35:34 PM PDT 24
Finished Aug 17 06:35:38 PM PDT 24
Peak memory 240060 kb
Host smart-35869009-1eec-4dfe-9bcc-2a765cb8ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504549374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1504549374
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4127876514
Short name T443
Test name
Test status
Simulation time 6151459171 ps
CPU time 11.19 seconds
Started Aug 17 06:35:11 PM PDT 24
Finished Aug 17 06:35:23 PM PDT 24
Peak memory 241512 kb
Host smart-c5397ac9-72f7-488b-9f52-8f4ba5466b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127876514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4127876514
Directory /workspace/2.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1416666689
Short name T948
Test name
Test status
Simulation time 568260232 ps
CPU time 3.73 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 220232 kb
Host smart-85942544-4d6d-434f-842d-4d8c01a0eac5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1416666689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1416666689
Directory /workspace/2.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/2.spi_device_sec_cm.1971061976
Short name T73
Test name
Test status
Simulation time 433874331 ps
CPU time 1.36 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 236600 kb
Host smart-3a3b4fd4-b2a6-4592-ac41-505da044bc56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971061976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1971061976
Directory /workspace/2.spi_device_sec_cm/latest


Test location /workspace/coverage/default/2.spi_device_stress_all.2156013122
Short name T160
Test name
Test status
Simulation time 94502792924 ps
CPU time 206.11 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:38:29 PM PDT 24
Peak memory 265212 kb
Host smart-702e1587-66fd-412d-b289-28838f0192bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156013122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2156013122
Directory /workspace/2.spi_device_stress_all/latest


Test location /workspace/coverage/default/2.spi_device_tpm_all.3614695449
Short name T612
Test name
Test status
Simulation time 315395443 ps
CPU time 2.24 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 219312 kb
Host smart-04f4d74c-fb5d-43e7-bc00-7ce61d5e0344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614695449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3614695449
Directory /workspace/2.spi_device_tpm_all/latest


Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2884417424
Short name T599
Test name
Test status
Simulation time 18606142952 ps
CPU time 11.97 seconds
Started Aug 17 06:35:28 PM PDT 24
Finished Aug 17 06:35:40 PM PDT 24
Peak memory 218612 kb
Host smart-b12f9a94-8ce9-4500-bd1f-85e6eb087be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884417424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2884417424
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/2.spi_device_tpm_rw.2272381816
Short name T583
Test name
Test status
Simulation time 206005439 ps
CPU time 2.46 seconds
Started Aug 17 06:35:14 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 217084 kb
Host smart-803e1c64-711c-4ae6-8e55-c4a805723913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272381816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2272381816
Directory /workspace/2.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2835647305
Short name T370
Test name
Test status
Simulation time 427036594 ps
CPU time 0.83 seconds
Started Aug 17 06:35:35 PM PDT 24
Finished Aug 17 06:35:46 PM PDT 24
Peak memory 206880 kb
Host smart-094b489a-fa1a-45e1-92c7-db4633d87d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835647305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2835647305
Directory /workspace/2.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/2.spi_device_upload.4081608470
Short name T263
Test name
Test status
Simulation time 33367020680 ps
CPU time 20.93 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:20 PM PDT 24
Peak memory 236480 kb
Host smart-1a77e259-4245-44d9-b594-76749503800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081608470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4081608470
Directory /workspace/2.spi_device_upload/latest


Test location /workspace/coverage/default/20.spi_device_alert_test.1690400193
Short name T606
Test name
Test status
Simulation time 115666554 ps
CPU time 0.71 seconds
Started Aug 17 06:35:50 PM PDT 24
Finished Aug 17 06:35:51 PM PDT 24
Peak memory 206236 kb
Host smart-1493f9e3-820d-4865-9ca4-37ea458c5124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690400193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1690400193
Directory /workspace/20.spi_device_alert_test/latest


Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3222907530
Short name T267
Test name
Test status
Simulation time 452547205 ps
CPU time 2.74 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 233592 kb
Host smart-cc8d9f42-6e57-4604-a9b4-5e0c4c43b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222907530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3222907530
Directory /workspace/20.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/20.spi_device_csb_read.4148451745
Short name T381
Test name
Test status
Simulation time 162269523 ps
CPU time 0.77 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 206340 kb
Host smart-639649a4-0363-45f6-af93-e1ff3ae010f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148451745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4148451745
Directory /workspace/20.spi_device_csb_read/latest


Test location /workspace/coverage/default/20.spi_device_flash_all.1937532428
Short name T503
Test name
Test status
Simulation time 4797371049 ps
CPU time 33.4 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:29 PM PDT 24
Peak memory 250332 kb
Host smart-e10a80ec-c63e-4ba5-8f06-54fb0d91ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937532428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1937532428
Directory /workspace/20.spi_device_flash_all/latest


Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2695681309
Short name T989
Test name
Test status
Simulation time 35618219608 ps
CPU time 47.28 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:45 PM PDT 24
Peak memory 225444 kb
Host smart-212dcfce-38f5-4c1e-ae3f-ef68dbdb2d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695681309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2695681309
Directory /workspace/20.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/20.spi_device_flash_mode.730650720
Short name T475
Test name
Test status
Simulation time 284272020 ps
CPU time 2.57 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 225296 kb
Host smart-bded1fd6-b23c-488d-9e23-745192f77b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730650720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.730650720
Directory /workspace/20.spi_device_flash_mode/latest


Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3630316775
Short name T965
Test name
Test status
Simulation time 18278423710 ps
CPU time 46.79 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 239572 kb
Host smart-b76a692d-d329-42d7-b6c7-cfc3b99132f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630316775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3630316775
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/20.spi_device_intercept.1106286176
Short name T777
Test name
Test status
Simulation time 6642758546 ps
CPU time 16.72 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 233624 kb
Host smart-888cc9e3-df1f-407d-b5ed-0f79fc193d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106286176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1106286176
Directory /workspace/20.spi_device_intercept/latest


Test location /workspace/coverage/default/20.spi_device_mailbox.2733007288
Short name T558
Test name
Test status
Simulation time 2213440323 ps
CPU time 11.22 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 225504 kb
Host smart-e84f2afb-0994-4a61-860d-b3f65169bb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733007288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2733007288
Directory /workspace/20.spi_device_mailbox/latest


Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3151327073
Short name T861
Test name
Test status
Simulation time 38852123183 ps
CPU time 27.42 seconds
Started Aug 17 06:35:52 PM PDT 24
Finished Aug 17 06:36:19 PM PDT 24
Peak memory 233568 kb
Host smart-2af36173-4085-4fff-b797-121a5c841721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151327073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3151327073
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2583777990
Short name T995
Test name
Test status
Simulation time 3248488881 ps
CPU time 5.26 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 233692 kb
Host smart-4952155d-6f92-4ef8-98e1-97a139da9a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583777990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2583777990
Directory /workspace/20.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1458200677
Short name T383
Test name
Test status
Simulation time 1343123837 ps
CPU time 11.14 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 221504 kb
Host smart-2d6722c6-6a03-4f8d-84d3-90d65065f196
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1458200677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1458200677
Directory /workspace/20.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/20.spi_device_stress_all.2702872922
Short name T830
Test name
Test status
Simulation time 2396686955 ps
CPU time 45.13 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 250532 kb
Host smart-d9c026a0-a566-43a1-9c03-0e043d315aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702872922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2702872922
Directory /workspace/20.spi_device_stress_all/latest


Test location /workspace/coverage/default/20.spi_device_tpm_all.769523790
Short name T904
Test name
Test status
Simulation time 4335240043 ps
CPU time 15.08 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 217224 kb
Host smart-565d00cf-d52a-4cb9-9690-63aaebab6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769523790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.769523790
Directory /workspace/20.spi_device_tpm_all/latest


Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1768224603
Short name T483
Test name
Test status
Simulation time 666846635 ps
CPU time 4.7 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 217196 kb
Host smart-3b8c23e9-4ce5-4f69-9ae1-e0a098e98885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768224603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1768224603
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/20.spi_device_tpm_rw.862180928
Short name T80
Test name
Test status
Simulation time 65021834 ps
CPU time 0.98 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:35:50 PM PDT 24
Peak memory 208692 kb
Host smart-9713b9c8-6eb2-4b50-b9b4-734e7f8c3189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862180928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.862180928
Directory /workspace/20.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3197322019
Short name T825
Test name
Test status
Simulation time 37015478 ps
CPU time 0.73 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 206764 kb
Host smart-2c8f97b1-e603-4ed4-83d9-4bb5f667dde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197322019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3197322019
Directory /workspace/20.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/20.spi_device_upload.1532297277
Short name T688
Test name
Test status
Simulation time 6255188820 ps
CPU time 5.5 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 225528 kb
Host smart-9ca0c7c6-24b3-4734-ac99-b77a544bc76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532297277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1532297277
Directory /workspace/20.spi_device_upload/latest


Test location /workspace/coverage/default/21.spi_device_alert_test.1706445160
Short name T546
Test name
Test status
Simulation time 23429683 ps
CPU time 0.7 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 206264 kb
Host smart-93995ae4-f3b1-4fe6-9954-1d663c59dbc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706445160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1706445160
Directory /workspace/21.spi_device_alert_test/latest


Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3940513508
Short name T555
Test name
Test status
Simulation time 6155484743 ps
CPU time 17.83 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:19 PM PDT 24
Peak memory 233716 kb
Host smart-fa0138b8-f79d-4387-802b-5ba265d6d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940513508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3940513508
Directory /workspace/21.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/21.spi_device_csb_read.3812503674
Short name T561
Test name
Test status
Simulation time 16095824 ps
CPU time 0.77 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 206392 kb
Host smart-7cadb5e8-b3b9-45ac-8d0b-74ec6c6834d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812503674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3812503674
Directory /workspace/21.spi_device_csb_read/latest


Test location /workspace/coverage/default/21.spi_device_flash_all.2686813919
Short name T992
Test name
Test status
Simulation time 5852711776 ps
CPU time 52.99 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 255380 kb
Host smart-b655ab71-c2d5-4833-971a-48a3925c4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686813919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2686813919
Directory /workspace/21.spi_device_flash_all/latest


Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1451015928
Short name T640
Test name
Test status
Simulation time 1956482717 ps
CPU time 17.18 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 233596 kb
Host smart-66f8eb57-8073-4c08-9ffb-c2ad522574bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451015928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1451015928
Directory /workspace/21.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3550666568
Short name T294
Test name
Test status
Simulation time 11994180216 ps
CPU time 117.36 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 254408 kb
Host smart-942a8ec0-ebc3-4ab2-85a4-eb59b691ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550666568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3550666568
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/21.spi_device_flash_mode.2787860469
Short name T984
Test name
Test status
Simulation time 114547241 ps
CPU time 4.68 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:35:54 PM PDT 24
Peak memory 233692 kb
Host smart-8df24e5e-9019-416c-8486-902ea45e24af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787860469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2787860469
Directory /workspace/21.spi_device_flash_mode/latest


Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2112712363
Short name T457
Test name
Test status
Simulation time 149098551516 ps
CPU time 249.74 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:40:10 PM PDT 24
Peak memory 266436 kb
Host smart-4686c7dd-97f8-4020-a0c1-3385c16bd6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112712363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2112712363
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/21.spi_device_intercept.2770753327
Short name T288
Test name
Test status
Simulation time 2687534918 ps
CPU time 7.21 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 225388 kb
Host smart-5c1bf463-4fcf-4c2e-a08e-e0e773c2b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770753327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2770753327
Directory /workspace/21.spi_device_intercept/latest


Test location /workspace/coverage/default/21.spi_device_mailbox.1863894432
Short name T981
Test name
Test status
Simulation time 714839615 ps
CPU time 5.75 seconds
Started Aug 17 06:35:50 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 225400 kb
Host smart-8771e4aa-f130-472e-8ccf-bcad17586078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863894432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1863894432
Directory /workspace/21.spi_device_mailbox/latest


Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3828354267
Short name T755
Test name
Test status
Simulation time 29288279254 ps
CPU time 18.87 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 233652 kb
Host smart-aa0224e1-50ee-40f2-b347-ed5a6ee920fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828354267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3828354267
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3412078608
Short name T258
Test name
Test status
Simulation time 674969446 ps
CPU time 9.19 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 225332 kb
Host smart-afcf3f7d-bbbe-47ae-8d10-77378a058135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412078608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3412078608
Directory /workspace/21.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.600870638
Short name T983
Test name
Test status
Simulation time 957671032 ps
CPU time 3.46 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:57 PM PDT 24
Peak memory 221116 kb
Host smart-d0aea242-5748-4eaa-97ae-469d77b24d25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=600870638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.600870638
Directory /workspace/21.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/21.spi_device_stress_all.1407434057
Short name T159
Test name
Test status
Simulation time 5591029578 ps
CPU time 22.63 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:21 PM PDT 24
Peak memory 223892 kb
Host smart-9c92625d-c3bc-4cc1-9944-27f6ba42e862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407434057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1407434057
Directory /workspace/21.spi_device_stress_all/latest


Test location /workspace/coverage/default/21.spi_device_tpm_all.1902483811
Short name T330
Test name
Test status
Simulation time 11333962681 ps
CPU time 41.34 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 217248 kb
Host smart-57342c08-80e8-4974-9f5e-0e4cb003439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902483811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1902483811
Directory /workspace/21.spi_device_tpm_all/latest


Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2574382588
Short name T445
Test name
Test status
Simulation time 15895799093 ps
CPU time 3.43 seconds
Started Aug 17 06:35:48 PM PDT 24
Finished Aug 17 06:35:51 PM PDT 24
Peak memory 217352 kb
Host smart-5859c2b7-66bd-4cff-9da0-371ff848c674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574382588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2574382588
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/21.spi_device_tpm_rw.245046826
Short name T627
Test name
Test status
Simulation time 246902200 ps
CPU time 2.31 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 217124 kb
Host smart-539525fd-4ed2-4c63-81ca-a1735408544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245046826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.245046826
Directory /workspace/21.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3271213743
Short name T787
Test name
Test status
Simulation time 18867360 ps
CPU time 0.74 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:57 PM PDT 24
Peak memory 206772 kb
Host smart-00c7aba0-2842-43f1-85f8-54abc2c4fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271213743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3271213743
Directory /workspace/21.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/21.spi_device_upload.2113226577
Short name T745
Test name
Test status
Simulation time 8162489206 ps
CPU time 13.76 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 233680 kb
Host smart-a43ebaf6-dda4-497e-87da-eee3eb4b2a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113226577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2113226577
Directory /workspace/21.spi_device_upload/latest


Test location /workspace/coverage/default/22.spi_device_alert_test.293544604
Short name T484
Test name
Test status
Simulation time 44360367 ps
CPU time 0.73 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 206628 kb
Host smart-1e8eb370-5221-4fc9-8ea8-af3c9c507676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293544604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.293544604
Directory /workspace/22.spi_device_alert_test/latest


Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3827571876
Short name T249
Test name
Test status
Simulation time 258303040 ps
CPU time 2.74 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 225424 kb
Host smart-eb57baaf-c251-4dfc-9459-615cfb8d37e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827571876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3827571876
Directory /workspace/22.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/22.spi_device_csb_read.1992922558
Short name T1005
Test name
Test status
Simulation time 13985662 ps
CPU time 0.75 seconds
Started Aug 17 06:36:20 PM PDT 24
Finished Aug 17 06:36:20 PM PDT 24
Peak memory 206308 kb
Host smart-6c43207e-1971-46ce-966f-ce200f9b8bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992922558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1992922558
Directory /workspace/22.spi_device_csb_read/latest


Test location /workspace/coverage/default/22.spi_device_flash_all.539656892
Short name T644
Test name
Test status
Simulation time 38064798 ps
CPU time 0.79 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:57 PM PDT 24
Peak memory 216652 kb
Host smart-986582e4-6250-49fb-b77c-467693c77a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539656892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.539656892
Directory /workspace/22.spi_device_flash_all/latest


Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4228418717
Short name T702
Test name
Test status
Simulation time 6692148488 ps
CPU time 51.14 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 251752 kb
Host smart-b73e7c21-3e4b-4823-b5b6-2757c2c35ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228418717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4228418717
Directory /workspace/22.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1129133985
Short name T266
Test name
Test status
Simulation time 2147065560 ps
CPU time 57.77 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 255952 kb
Host smart-18e680af-c52e-416c-8323-dcfa52439fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129133985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1129133985
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/22.spi_device_flash_mode.1294726432
Short name T317
Test name
Test status
Simulation time 349591300 ps
CPU time 4.95 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 225372 kb
Host smart-705e04a9-daba-406d-8544-7e1922f06f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294726432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1294726432
Directory /workspace/22.spi_device_flash_mode/latest


Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2969056546
Short name T456
Test name
Test status
Simulation time 2947486209 ps
CPU time 54.55 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:50 PM PDT 24
Peak memory 258072 kb
Host smart-f1c5b3e0-22a9-4ab7-868f-f7e00884341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969056546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2969056546
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/22.spi_device_intercept.1473955318
Short name T105
Test name
Test status
Simulation time 2100594213 ps
CPU time 26.09 seconds
Started Aug 17 06:35:52 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 225360 kb
Host smart-f17e4308-0055-4f76-9cac-69902803909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473955318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1473955318
Directory /workspace/22.spi_device_intercept/latest


Test location /workspace/coverage/default/22.spi_device_mailbox.570176345
Short name T287
Test name
Test status
Simulation time 114934612 ps
CPU time 2.88 seconds
Started Aug 17 06:35:53 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 233520 kb
Host smart-24ca74db-978e-4918-b3df-291de74b3bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570176345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.570176345
Directory /workspace/22.spi_device_mailbox/latest


Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.18733623
Short name T308
Test name
Test status
Simulation time 3061322274 ps
CPU time 12.15 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 239496 kb
Host smart-1a206438-79d9-449b-92d5-b2b148994704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18733623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.18733623
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2000935901
Short name T730
Test name
Test status
Simulation time 16022997219 ps
CPU time 13.33 seconds
Started Aug 17 06:35:52 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 233540 kb
Host smart-a981cab6-8c02-45b4-85e1-a7eb2f2f4b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000935901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2000935901
Directory /workspace/22.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.289268531
Short name T857
Test name
Test status
Simulation time 3379150047 ps
CPU time 10.5 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 223276 kb
Host smart-6ee1eb3e-b6d6-4c02-8bb7-10ef5b895fc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=289268531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.289268531
Directory /workspace/22.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/22.spi_device_stress_all.1080104003
Short name T811
Test name
Test status
Simulation time 85471762 ps
CPU time 1.29 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 208232 kb
Host smart-c14f3028-e1b0-4ab6-86bb-2471791ab290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080104003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1080104003
Directory /workspace/22.spi_device_stress_all/latest


Test location /workspace/coverage/default/22.spi_device_tpm_all.1148677761
Short name T624
Test name
Test status
Simulation time 33407566791 ps
CPU time 50.06 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:36:44 PM PDT 24
Peak memory 217252 kb
Host smart-0059a3d9-8c66-4900-9d51-0c3d8c786d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148677761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1148677761
Directory /workspace/22.spi_device_tpm_all/latest


Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2627109707
Short name T864
Test name
Test status
Simulation time 3476246592 ps
CPU time 4.94 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 217284 kb
Host smart-788fbd93-3a1d-4fcf-8370-1aa3167192f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627109707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2627109707
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/22.spi_device_tpm_rw.513206558
Short name T953
Test name
Test status
Simulation time 14184320 ps
CPU time 0.87 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 206824 kb
Host smart-31c7f4bb-1729-48d9-b886-dcd33eecb2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513206558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.513206558
Directory /workspace/22.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1882701754
Short name T963
Test name
Test status
Simulation time 118233289 ps
CPU time 0.87 seconds
Started Aug 17 06:35:49 PM PDT 24
Finished Aug 17 06:35:50 PM PDT 24
Peak memory 206824 kb
Host smart-9d587454-448b-4268-abd7-31ec0f3079fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882701754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1882701754
Directory /workspace/22.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/22.spi_device_upload.1841571054
Short name T244
Test name
Test status
Simulation time 1468964997 ps
CPU time 8.78 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 236760 kb
Host smart-9cbc8029-deab-4eb4-ad23-461506031231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841571054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1841571054
Directory /workspace/22.spi_device_upload/latest


Test location /workspace/coverage/default/23.spi_device_alert_test.212500202
Short name T568
Test name
Test status
Simulation time 17396992 ps
CPU time 0.68 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 206240 kb
Host smart-07cc30e5-aa35-4a96-be63-0f12e065230f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212500202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.212500202
Directory /workspace/23.spi_device_alert_test/latest


Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1544416612
Short name T761
Test name
Test status
Simulation time 992141845 ps
CPU time 3.6 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 225356 kb
Host smart-2d852578-e757-4a75-8784-09ce67c396d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544416612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1544416612
Directory /workspace/23.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/23.spi_device_csb_read.3345918288
Short name T393
Test name
Test status
Simulation time 40564531 ps
CPU time 0.77 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 207412 kb
Host smart-c3a3d8af-6249-4574-82a6-58e31e6aa5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345918288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3345918288
Directory /workspace/23.spi_device_csb_read/latest


Test location /workspace/coverage/default/23.spi_device_flash_all.1018014979
Short name T677
Test name
Test status
Simulation time 370116791970 ps
CPU time 226.25 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:39:40 PM PDT 24
Peak memory 252156 kb
Host smart-d4d61c9f-e5ca-4811-bf69-bd0d9c663ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018014979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1018014979
Directory /workspace/23.spi_device_flash_all/latest


Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1520459453
Short name T711
Test name
Test status
Simulation time 81586041322 ps
CPU time 151.59 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:38:30 PM PDT 24
Peak memory 250212 kb
Host smart-301fbc58-b586-4145-b6ca-bfc3f41d5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520459453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1520459453
Directory /workspace/23.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.242497960
Short name T436
Test name
Test status
Simulation time 101575042826 ps
CPU time 209.58 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:39:37 PM PDT 24
Peak memory 250184 kb
Host smart-b35de691-8ea5-40ae-a760-fa7e16b9c249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242497960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.242497960
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/23.spi_device_flash_mode.447297627
Short name T324
Test name
Test status
Simulation time 2273394816 ps
CPU time 18.53 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:20 PM PDT 24
Peak memory 233696 kb
Host smart-e9e73f78-4dd7-4587-bcf4-371d343f5d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447297627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.447297627
Directory /workspace/23.spi_device_flash_mode/latest


Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.378701267
Short name T950
Test name
Test status
Simulation time 103339098908 ps
CPU time 94.93 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 241812 kb
Host smart-3e18ba8d-be1f-445a-b028-9ff70866bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378701267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.378701267
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/23.spi_device_intercept.1996387067
Short name T813
Test name
Test status
Simulation time 1804308346 ps
CPU time 7.23 seconds
Started Aug 17 06:36:07 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 233600 kb
Host smart-9348e336-d2a6-4d73-9c19-05c97cadd849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996387067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1996387067
Directory /workspace/23.spi_device_intercept/latest


Test location /workspace/coverage/default/23.spi_device_mailbox.1654538007
Short name T243
Test name
Test status
Simulation time 335454239 ps
CPU time 4.1 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 233604 kb
Host smart-c55f1e8c-798e-4c59-baf6-64561e1d63ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654538007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1654538007
Directory /workspace/23.spi_device_mailbox/latest


Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1897519512
Short name T452
Test name
Test status
Simulation time 1101434854 ps
CPU time 4.74 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 225376 kb
Host smart-d53731ff-7313-4432-8c6e-c85d82530ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897519512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1897519512
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1671612756
Short name T400
Test name
Test status
Simulation time 8970987941 ps
CPU time 24.92 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:27 PM PDT 24
Peak memory 236944 kb
Host smart-0cc4258e-f7e4-4e65-afcc-b3f962c6ab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671612756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1671612756
Directory /workspace/23.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.312634740
Short name T577
Test name
Test status
Simulation time 4056710486 ps
CPU time 6.6 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 221120 kb
Host smart-0be0ebbe-89c5-48ea-a78a-6340ab9f549b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=312634740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.312634740
Directory /workspace/23.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/23.spi_device_stress_all.125276799
Short name T161
Test name
Test status
Simulation time 151044622 ps
CPU time 1.31 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 216292 kb
Host smart-ad39d80a-85e4-4f40-afd4-2c733af51d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125276799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.125276799
Directory /workspace/23.spi_device_stress_all/latest


Test location /workspace/coverage/default/23.spi_device_tpm_all.3708757992
Short name T912
Test name
Test status
Simulation time 16725276 ps
CPU time 0.7 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 206528 kb
Host smart-c65ec618-ba22-48b4-8c44-e86afe4e3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708757992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3708757992
Directory /workspace/23.spi_device_tpm_all/latest


Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2185334834
Short name T863
Test name
Test status
Simulation time 1510860738 ps
CPU time 6.38 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 217016 kb
Host smart-2cee2367-b105-4d03-b5ed-803470ca569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185334834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2185334834
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/23.spi_device_tpm_rw.2141235238
Short name T437
Test name
Test status
Simulation time 201274669 ps
CPU time 2.03 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 217248 kb
Host smart-3a0cd3d6-2387-4194-a174-8b675fae34d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141235238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2141235238
Directory /workspace/23.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4114052707
Short name T585
Test name
Test status
Simulation time 82654118 ps
CPU time 0.89 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 206856 kb
Host smart-f6df749c-426a-40ce-a6ca-55405382c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114052707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4114052707
Directory /workspace/23.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/23.spi_device_upload.2769311834
Short name T270
Test name
Test status
Simulation time 3106486431 ps
CPU time 11.02 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 233484 kb
Host smart-37888f56-7c69-40fc-94ab-23c365a34571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769311834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2769311834
Directory /workspace/23.spi_device_upload/latest


Test location /workspace/coverage/default/24.spi_device_alert_test.137144458
Short name T738
Test name
Test status
Simulation time 38583331 ps
CPU time 0.69 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 206260 kb
Host smart-301d7b00-dbe6-47b4-8b44-d6c13042368e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137144458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.137144458
Directory /workspace/24.spi_device_alert_test/latest


Test location /workspace/coverage/default/24.spi_device_cfg_cmd.33655675
Short name T631
Test name
Test status
Simulation time 3647654090 ps
CPU time 9.74 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 233696 kb
Host smart-15113d90-cb91-4488-8aaf-59d7837c4026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33655675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.33655675
Directory /workspace/24.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/24.spi_device_csb_read.307623022
Short name T850
Test name
Test status
Simulation time 33987913 ps
CPU time 0.81 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 207404 kb
Host smart-0fcd5559-3e2c-4924-ae66-3b5893bfa857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307623022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.307623022
Directory /workspace/24.spi_device_csb_read/latest


Test location /workspace/coverage/default/24.spi_device_flash_all.3330770881
Short name T173
Test name
Test status
Simulation time 101544466540 ps
CPU time 118.12 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 254484 kb
Host smart-3adfc37a-22a9-4734-a759-8977982db875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330770881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3330770881
Directory /workspace/24.spi_device_flash_all/latest


Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1848789308
Short name T302
Test name
Test status
Simulation time 58711770234 ps
CPU time 137.46 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:38:19 PM PDT 24
Peak memory 257400 kb
Host smart-349e9618-488d-4ee2-a20f-cd98a5ea33af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848789308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1848789308
Directory /workspace/24.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4126121257
Short name T580
Test name
Test status
Simulation time 1882246746 ps
CPU time 36.93 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 250104 kb
Host smart-f0af877c-ae7b-454f-8ea9-90641b6c834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126121257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4126121257
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/24.spi_device_flash_mode.3728965244
Short name T714
Test name
Test status
Simulation time 130741513 ps
CPU time 3.29 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 233448 kb
Host smart-30e237a2-89e4-445e-9559-b7397fdce6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728965244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3728965244
Directory /workspace/24.spi_device_flash_mode/latest


Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2858522112
Short name T314
Test name
Test status
Simulation time 29775884001 ps
CPU time 102.51 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 256632 kb
Host smart-dac6c9b7-91bf-42e2-ab72-5f0b3e739d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858522112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2858522112
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/24.spi_device_intercept.1869537682
Short name T872
Test name
Test status
Simulation time 454072842 ps
CPU time 5.48 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 225356 kb
Host smart-f96bd5ff-7f93-4bd6-8322-c37d3db4f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869537682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1869537682
Directory /workspace/24.spi_device_intercept/latest


Test location /workspace/coverage/default/24.spi_device_mailbox.2861804961
Short name T836
Test name
Test status
Simulation time 623718852 ps
CPU time 4.15 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 233636 kb
Host smart-061b844e-73c3-4104-84aa-d8a75bb86331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861804961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2861804961
Directory /workspace/24.spi_device_mailbox/latest


Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2190947541
Short name T296
Test name
Test status
Simulation time 1108849853 ps
CPU time 8.27 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 225292 kb
Host smart-03fa419f-d17e-4db9-b2e1-92e8cf721fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190947541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2190947541
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3209822458
Short name T900
Test name
Test status
Simulation time 8453113789 ps
CPU time 8.76 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 240708 kb
Host smart-d0b63d9d-9e78-4523-8d15-b9470d91b162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209822458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3209822458
Directory /workspace/24.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.693002693
Short name T887
Test name
Test status
Simulation time 1149493521 ps
CPU time 11.46 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 219620 kb
Host smart-1fbb036e-8247-4a0b-92fd-c6a4b1c0600d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693002693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.693002693
Directory /workspace/24.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/24.spi_device_tpm_all.1721743073
Short name T328
Test name
Test status
Simulation time 4417540282 ps
CPU time 22.23 seconds
Started Aug 17 06:36:18 PM PDT 24
Finished Aug 17 06:36:40 PM PDT 24
Peak memory 217196 kb
Host smart-85c1d558-a3ea-47a4-bc29-cc5ed57e1984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721743073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1721743073
Directory /workspace/24.spi_device_tpm_all/latest


Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3239645456
Short name T413
Test name
Test status
Simulation time 6028456707 ps
CPU time 16.23 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 217336 kb
Host smart-964d4e90-f179-4ca6-8c8d-ab612514e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239645456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3239645456
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/24.spi_device_tpm_rw.668210980
Short name T418
Test name
Test status
Simulation time 53329656 ps
CPU time 0.71 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 206448 kb
Host smart-0ad8bb53-6c94-4196-bf1c-edec3ec4f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668210980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.668210980
Directory /workspace/24.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.896148507
Short name T883
Test name
Test status
Simulation time 27118358 ps
CPU time 0.88 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 206860 kb
Host smart-e2c6e55d-3ab5-4096-a786-32f9e60de68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896148507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.896148507
Directory /workspace/24.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/24.spi_device_upload.2634359455
Short name T462
Test name
Test status
Simulation time 711535301 ps
CPU time 2.95 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 233588 kb
Host smart-e5884fdb-4db7-4c43-87d2-3c509ccc3a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634359455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2634359455
Directory /workspace/24.spi_device_upload/latest


Test location /workspace/coverage/default/25.spi_device_alert_test.992126858
Short name T6
Test name
Test status
Simulation time 15519400 ps
CPU time 0.71 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:56 PM PDT 24
Peak memory 206584 kb
Host smart-49111e3c-d7d3-4b36-aff6-79b93fbf4668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992126858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.992126858
Directory /workspace/25.spi_device_alert_test/latest


Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2824017978
Short name T195
Test name
Test status
Simulation time 260649211 ps
CPU time 3.57 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:16 PM PDT 24
Peak memory 225332 kb
Host smart-5169e67d-d0d8-4cfa-b16b-2c5966a43a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824017978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2824017978
Directory /workspace/25.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/25.spi_device_csb_read.1465065460
Short name T824
Test name
Test status
Simulation time 70288527 ps
CPU time 0.77 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 207408 kb
Host smart-22690476-5e0a-49b5-9098-b32abc16798f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465065460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1465065460
Directory /workspace/25.spi_device_csb_read/latest


Test location /workspace/coverage/default/25.spi_device_flash_all.929369037
Short name T172
Test name
Test status
Simulation time 19467049192 ps
CPU time 41.13 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 263052 kb
Host smart-2ee9bc47-ba4f-4880-bc74-a7d5d2c93450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929369037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.929369037
Directory /workspace/25.spi_device_flash_all/latest


Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1936452638
Short name T739
Test name
Test status
Simulation time 9552837833 ps
CPU time 61.83 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 236112 kb
Host smart-36218672-8d07-4eab-a0f1-59e121455bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936452638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1936452638
Directory /workspace/25.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2045857489
Short name T874
Test name
Test status
Simulation time 2632465456 ps
CPU time 38.01 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:41 PM PDT 24
Peak memory 232024 kb
Host smart-e89fe7bf-fad4-47ab-8a0a-3caae58cec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045857489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2045857489
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/25.spi_device_flash_mode.4234943913
Short name T919
Test name
Test status
Simulation time 12122918336 ps
CPU time 37.63 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:36:33 PM PDT 24
Peak memory 225492 kb
Host smart-f6d5c2c2-eda4-4718-8e3e-021284af39e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234943913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4234943913
Directory /workspace/25.spi_device_flash_mode/latest


Test location /workspace/coverage/default/25.spi_device_intercept.930987460
Short name T1007
Test name
Test status
Simulation time 1306143248 ps
CPU time 12.24 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 225344 kb
Host smart-e21a36c0-b1bf-43bb-ab01-c068a454f6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930987460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.930987460
Directory /workspace/25.spi_device_intercept/latest


Test location /workspace/coverage/default/25.spi_device_mailbox.1354932802
Short name T253
Test name
Test status
Simulation time 150785738 ps
CPU time 2.54 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 225376 kb
Host smart-1c72c1df-73fa-4954-9135-e3b56201d409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354932802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1354932802
Directory /workspace/25.spi_device_mailbox/latest


Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2156940785
Short name T312
Test name
Test status
Simulation time 10045087718 ps
CPU time 8.56 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 241676 kb
Host smart-1e56d120-552d-4f59-a38c-03ab72888246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156940785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2156940785
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1016449307
Short name T737
Test name
Test status
Simulation time 2225894717 ps
CPU time 8.53 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 233700 kb
Host smart-836f7f98-219a-4dfd-b450-1daaefde7c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016449307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1016449307
Directory /workspace/25.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1640248892
Short name T15
Test name
Test status
Simulation time 89611137 ps
CPU time 4.09 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 223764 kb
Host smart-9989f90d-aa83-4ebf-bd2a-0e0c2eb52b16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1640248892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1640248892
Directory /workspace/25.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/25.spi_device_stress_all.3334519941
Short name T401
Test name
Test status
Simulation time 7877583852 ps
CPU time 52.41 seconds
Started Aug 17 06:36:11 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 253928 kb
Host smart-37eea250-e2a1-4fcc-9213-1f5361224e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334519941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3334519941
Directory /workspace/25.spi_device_stress_all/latest


Test location /workspace/coverage/default/25.spi_device_tpm_all.130368181
Short name T423
Test name
Test status
Simulation time 7825209911 ps
CPU time 12.99 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 217392 kb
Host smart-5961b5cb-8c2a-48aa-864b-861e05970390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130368181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.130368181
Directory /workspace/25.spi_device_tpm_all/latest


Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1597698681
Short name T842
Test name
Test status
Simulation time 4706386394 ps
CPU time 7.42 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 217256 kb
Host smart-105ababf-f7bb-4a97-bf37-bf2f0c15c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597698681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1597698681
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/25.spi_device_tpm_rw.359830643
Short name T771
Test name
Test status
Simulation time 79843506 ps
CPU time 1.09 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 217084 kb
Host smart-05f56baa-bfd3-4509-a280-5439f360ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359830643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.359830643
Directory /workspace/25.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.652073256
Short name T543
Test name
Test status
Simulation time 92567657 ps
CPU time 0.85 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 207912 kb
Host smart-e54715fc-023d-4457-9cd6-476fe1a48703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652073256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.652073256
Directory /workspace/25.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/25.spi_device_upload.83557979
Short name T191
Test name
Test status
Simulation time 25153877545 ps
CPU time 19.27 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 233724 kb
Host smart-0187319b-fe22-4b4b-aa28-783c1dc87c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83557979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.83557979
Directory /workspace/25.spi_device_upload/latest


Test location /workspace/coverage/default/26.spi_device_alert_test.180983254
Short name T660
Test name
Test status
Simulation time 13958257 ps
CPU time 0.73 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 206280 kb
Host smart-1a54d19d-be3a-4b9d-b22b-fa967331253d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180983254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.180983254
Directory /workspace/26.spi_device_alert_test/latest


Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1289982382
Short name T283
Test name
Test status
Simulation time 967773850 ps
CPU time 4 seconds
Started Aug 17 06:36:27 PM PDT 24
Finished Aug 17 06:36:31 PM PDT 24
Peak memory 225388 kb
Host smart-0ff34923-94cc-4f0e-8095-cb2ffc4dee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289982382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1289982382
Directory /workspace/26.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/26.spi_device_csb_read.3336385426
Short name T354
Test name
Test status
Simulation time 25343353 ps
CPU time 0.79 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 207404 kb
Host smart-f08e601a-5ab1-4e23-8af8-cf6dc59b9d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336385426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3336385426
Directory /workspace/26.spi_device_csb_read/latest


Test location /workspace/coverage/default/26.spi_device_flash_all.2221428536
Short name T663
Test name
Test status
Simulation time 33006676657 ps
CPU time 78.06 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 250108 kb
Host smart-3826287e-e77e-4e1d-8449-9475af1c5eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221428536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2221428536
Directory /workspace/26.spi_device_flash_all/latest


Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.761360903
Short name T536
Test name
Test status
Simulation time 2499781785 ps
CPU time 11.24 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 233684 kb
Host smart-17e0d7b7-2e09-46ee-9d49-d6af59ca9418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761360903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.761360903
Directory /workspace/26.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1726445162
Short name T227
Test name
Test status
Simulation time 5996915444 ps
CPU time 27.29 seconds
Started Aug 17 06:36:13 PM PDT 24
Finished Aug 17 06:36:41 PM PDT 24
Peak memory 238392 kb
Host smart-c1d23209-becf-4e45-9f0f-09b56c4225cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726445162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1726445162
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/26.spi_device_flash_mode.818483910
Short name T516
Test name
Test status
Simulation time 149008718 ps
CPU time 4.29 seconds
Started Aug 17 06:35:54 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 235920 kb
Host smart-ce2e2608-1dce-4aba-bb17-b11611eecacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818483910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.818483910
Directory /workspace/26.spi_device_flash_mode/latest


Test location /workspace/coverage/default/26.spi_device_intercept.2316090660
Short name T510
Test name
Test status
Simulation time 30069895 ps
CPU time 2.58 seconds
Started Aug 17 06:35:56 PM PDT 24
Finished Aug 17 06:35:59 PM PDT 24
Peak memory 233304 kb
Host smart-02091a47-2d4b-4c7b-8155-07c9dcde1bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316090660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2316090660
Directory /workspace/26.spi_device_intercept/latest


Test location /workspace/coverage/default/26.spi_device_mailbox.2457506206
Short name T251
Test name
Test status
Simulation time 12379123007 ps
CPU time 15.59 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 225460 kb
Host smart-fce87917-3460-486a-92c8-c01568dc15f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457506206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2457506206
Directory /workspace/26.spi_device_mailbox/latest


Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2948158193
Short name T523
Test name
Test status
Simulation time 5903537674 ps
CPU time 21.2 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:19 PM PDT 24
Peak memory 241912 kb
Host smart-dc005beb-40be-4638-a150-7f815b5ebf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948158193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2948158193
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2523107189
Short name T875
Test name
Test status
Simulation time 18328864621 ps
CPU time 28.63 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:26 PM PDT 24
Peak memory 239524 kb
Host smart-6240ed54-3cd7-4bb7-9e73-32dda4ca6225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523107189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2523107189
Directory /workspace/26.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.942978662
Short name T598
Test name
Test status
Simulation time 3362278712 ps
CPU time 13.81 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 221800 kb
Host smart-eb2117fe-4178-45bf-b19b-8e8f31f24c4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942978662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.942978662
Directory /workspace/26.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/26.spi_device_stress_all.3958823967
Short name T34
Test name
Test status
Simulation time 406493743 ps
CPU time 1.05 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 208524 kb
Host smart-204d33c7-102a-47e0-92fe-3b9f036835bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958823967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3958823967
Directory /workspace/26.spi_device_stress_all/latest


Test location /workspace/coverage/default/26.spi_device_tpm_all.3697979660
Short name T642
Test name
Test status
Simulation time 3076641752 ps
CPU time 5.89 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 217328 kb
Host smart-09b0fd03-14b1-48c2-98bc-6ddff97ed6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697979660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3697979660
Directory /workspace/26.spi_device_tpm_all/latest


Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3928942352
Short name T94
Test name
Test status
Simulation time 1165619739 ps
CPU time 1.72 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 208760 kb
Host smart-8a182d50-a310-4ba6-a5e9-29ff63294c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928942352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3928942352
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/26.spi_device_tpm_rw.3500242475
Short name T391
Test name
Test status
Simulation time 78702489 ps
CPU time 1.26 seconds
Started Aug 17 06:35:51 PM PDT 24
Finished Aug 17 06:35:53 PM PDT 24
Peak memory 217060 kb
Host smart-15bcd286-1453-4419-b908-5745afdfc27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500242475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3500242475
Directory /workspace/26.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2063818971
Short name T921
Test name
Test status
Simulation time 38518189 ps
CPU time 0.88 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 207844 kb
Host smart-c85dd3d8-1d82-4437-952d-7089bb490efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063818971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2063818971
Directory /workspace/26.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/26.spi_device_upload.151683231
Short name T955
Test name
Test status
Simulation time 737563263 ps
CPU time 2.32 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 225052 kb
Host smart-5968eb1e-fe6d-4aa4-baec-2e7a8397795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151683231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.151683231
Directory /workspace/26.spi_device_upload/latest


Test location /workspace/coverage/default/27.spi_device_alert_test.719159513
Short name T655
Test name
Test status
Simulation time 27988729 ps
CPU time 0.7 seconds
Started Aug 17 06:36:23 PM PDT 24
Finished Aug 17 06:36:24 PM PDT 24
Peak memory 205592 kb
Host smart-794385a9-ab92-4716-a797-3e6eb1625a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719159513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.719159513
Directory /workspace/27.spi_device_alert_test/latest


Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3702436643
Short name T96
Test name
Test status
Simulation time 2030547048 ps
CPU time 6.31 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 233604 kb
Host smart-cc95ce44-4e2f-4154-9e64-d7f37b6a20e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702436643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3702436643
Directory /workspace/27.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/27.spi_device_csb_read.1610837387
Short name T453
Test name
Test status
Simulation time 17983194 ps
CPU time 0.8 seconds
Started Aug 17 06:36:04 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 207408 kb
Host smart-f8ca4127-d1f5-4108-b8b7-35061943cebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610837387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1610837387
Directory /workspace/27.spi_device_csb_read/latest


Test location /workspace/coverage/default/27.spi_device_flash_all.2174992680
Short name T410
Test name
Test status
Simulation time 838256981 ps
CPU time 5.05 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 234680 kb
Host smart-b18581e8-3686-4872-9342-928898915cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174992680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2174992680
Directory /workspace/27.spi_device_flash_all/latest


Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.511712237
Short name T229
Test name
Test status
Simulation time 184672566901 ps
CPU time 418.93 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:42:59 PM PDT 24
Peak memory 253820 kb
Host smart-65b7615d-846e-4f39-a20c-272d2fd5b159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511712237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.511712237
Directory /workspace/27.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3501677125
Short name T732
Test name
Test status
Simulation time 5009295554 ps
CPU time 40.37 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:36:43 PM PDT 24
Peak memory 256136 kb
Host smart-302c5c2c-944c-47bd-b409-a64bcaf8fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501677125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3501677125
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/27.spi_device_flash_mode.2377821079
Short name T134
Test name
Test status
Simulation time 1961571576 ps
CPU time 8.05 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 249900 kb
Host smart-83f447b8-bf1d-4ea6-96a8-0f8a5ff610b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377821079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2377821079
Directory /workspace/27.spi_device_flash_mode/latest


Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.106622657
Short name T212
Test name
Test status
Simulation time 28780549098 ps
CPU time 217.64 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:39:43 PM PDT 24
Peak memory 260416 kb
Host smart-ecacfa06-8283-4e7f-abd1-78f3e6f083d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106622657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.106622657
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/27.spi_device_intercept.1435315296
Short name T494
Test name
Test status
Simulation time 201379883 ps
CPU time 3.52 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 225368 kb
Host smart-8b227944-9a15-4fe9-99a9-71190d47dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435315296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1435315296
Directory /workspace/27.spi_device_intercept/latest


Test location /workspace/coverage/default/27.spi_device_mailbox.3366485184
Short name T345
Test name
Test status
Simulation time 333371898 ps
CPU time 2.16 seconds
Started Aug 17 06:35:55 PM PDT 24
Finished Aug 17 06:35:58 PM PDT 24
Peak memory 225008 kb
Host smart-9934722c-981d-4ed1-950d-bd3cd93bfcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366485184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3366485184
Directory /workspace/27.spi_device_mailbox/latest


Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3848293482
Short name T967
Test name
Test status
Simulation time 39441650814 ps
CPU time 13.43 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 225428 kb
Host smart-a47e71e6-e944-41c2-81d0-37e977a11696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848293482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3848293482
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3663346305
Short name T269
Test name
Test status
Simulation time 535767329 ps
CPU time 4.85 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 225284 kb
Host smart-c5745506-7983-49f4-b00a-a5d51d7e8c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663346305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3663346305
Directory /workspace/27.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.321951999
Short name T609
Test name
Test status
Simulation time 106097858 ps
CPU time 3.83 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 224092 kb
Host smart-61d5699a-86dd-4a6e-9178-1d1026f4876f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=321951999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.321951999
Directory /workspace/27.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/27.spi_device_stress_all.3926165218
Short name T21
Test name
Test status
Simulation time 202402160 ps
CPU time 1.17 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 208064 kb
Host smart-89439431-7e24-4691-ab26-64ca38878b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926165218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3926165218
Directory /workspace/27.spi_device_stress_all/latest


Test location /workspace/coverage/default/27.spi_device_tpm_all.3012453510
Short name T490
Test name
Test status
Simulation time 6694650620 ps
CPU time 17.77 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 217160 kb
Host smart-89451871-2d78-413f-9336-cd962855b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012453510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3012453510
Directory /workspace/27.spi_device_tpm_all/latest


Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3008479035
Short name T628
Test name
Test status
Simulation time 13118898175 ps
CPU time 11.24 seconds
Started Aug 17 06:35:52 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 217304 kb
Host smart-47c45f36-7486-467b-ae58-03c9939a43cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008479035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3008479035
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/27.spi_device_tpm_rw.4241365765
Short name T548
Test name
Test status
Simulation time 867824083 ps
CPU time 3.65 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 217100 kb
Host smart-77c517d2-fa64-41b1-93e0-98ec655d168b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241365765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4241365765
Directory /workspace/27.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3625198798
Short name T988
Test name
Test status
Simulation time 116473487 ps
CPU time 1.05 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 207880 kb
Host smart-ec2599d0-46b1-4f59-b3ff-8ee2f6578d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625198798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3625198798
Directory /workspace/27.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/27.spi_device_upload.1796351972
Short name T260
Test name
Test status
Simulation time 1460430978 ps
CPU time 4.7 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 228780 kb
Host smart-22c02723-972f-4ab9-b3df-983ec4cc7902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796351972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1796351972
Directory /workspace/27.spi_device_upload/latest


Test location /workspace/coverage/default/28.spi_device_alert_test.1891950474
Short name T424
Test name
Test status
Simulation time 16823229 ps
CPU time 0.74 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 205676 kb
Host smart-f9758eec-858b-4e02-a727-eda9d61377af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891950474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1891950474
Directory /workspace/28.spi_device_alert_test/latest


Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2637713612
Short name T957
Test name
Test status
Simulation time 1208247393 ps
CPU time 4.53 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 225364 kb
Host smart-97c9c948-11a0-43f8-b18e-aca5d9e37521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637713612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2637713612
Directory /workspace/28.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/28.spi_device_csb_read.2241660953
Short name T514
Test name
Test status
Simulation time 22634967 ps
CPU time 0.75 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:00 PM PDT 24
Peak memory 207408 kb
Host smart-77677603-8f22-48b4-892e-b28a7bd5ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241660953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2241660953
Directory /workspace/28.spi_device_csb_read/latest


Test location /workspace/coverage/default/28.spi_device_flash_all.1559546659
Short name T723
Test name
Test status
Simulation time 5074966436 ps
CPU time 20.57 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:20 PM PDT 24
Peak memory 225532 kb
Host smart-9c77ec47-6ff2-4ae2-8c67-47c33b3c80f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559546659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1559546659
Directory /workspace/28.spi_device_flash_all/latest


Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2577711430
Short name T215
Test name
Test status
Simulation time 39017875687 ps
CPU time 239.95 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:40:05 PM PDT 24
Peak memory 255660 kb
Host smart-47eae82a-e50d-445b-a877-ac4390cb6701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577711430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2577711430
Directory /workspace/28.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.657958385
Short name T581
Test name
Test status
Simulation time 2578667104 ps
CPU time 44.66 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 241964 kb
Host smart-f92e0942-b251-4ba4-80c8-97321a6346aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657958385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.657958385
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/28.spi_device_flash_mode.923036737
Short name T635
Test name
Test status
Simulation time 629465301 ps
CPU time 14.82 seconds
Started Aug 17 06:36:16 PM PDT 24
Finished Aug 17 06:36:31 PM PDT 24
Peak memory 233528 kb
Host smart-13acb64d-1b65-471a-becb-7297dcf2d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923036737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.923036737
Directory /workspace/28.spi_device_flash_mode/latest


Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1619583088
Short name T500
Test name
Test status
Simulation time 2099951371 ps
CPU time 16.9 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:23 PM PDT 24
Peak memory 236380 kb
Host smart-2a2d587e-313f-4dfd-889a-c15f8ce0a520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619583088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1619583088
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/28.spi_device_intercept.2569666723
Short name T697
Test name
Test status
Simulation time 279991752 ps
CPU time 6.24 seconds
Started Aug 17 06:36:16 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 225300 kb
Host smart-34309984-98c7-4142-aa83-b66f4aba1e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569666723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2569666723
Directory /workspace/28.spi_device_intercept/latest


Test location /workspace/coverage/default/28.spi_device_mailbox.3500012840
Short name T535
Test name
Test status
Simulation time 781572752 ps
CPU time 9.9 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 241516 kb
Host smart-1ce13010-5c9e-4ccd-ab09-315e75c2525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500012840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3500012840
Directory /workspace/28.spi_device_mailbox/latest


Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3712352294
Short name T394
Test name
Test status
Simulation time 201813508 ps
CPU time 2.64 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 225232 kb
Host smart-4e5f9c73-4eb1-4a2c-a635-46bc7d1499aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712352294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3712352294
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4198566498
Short name T838
Test name
Test status
Simulation time 674691841 ps
CPU time 3.75 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 233500 kb
Host smart-9d10713b-58be-4bbd-a6db-c441ede50a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198566498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4198566498
Directory /workspace/28.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2073622360
Short name T61
Test name
Test status
Simulation time 1541829906 ps
CPU time 5.57 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 223940 kb
Host smart-a5b2966f-1942-4dcb-9340-635a3f3667ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2073622360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2073622360
Directory /workspace/28.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/28.spi_device_stress_all.4129110430
Short name T899
Test name
Test status
Simulation time 34485172373 ps
CPU time 122.7 seconds
Started Aug 17 06:36:10 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 266532 kb
Host smart-dafb6c81-c99e-463e-b930-a0e9efe963ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129110430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4129110430
Directory /workspace/28.spi_device_stress_all/latest


Test location /workspace/coverage/default/28.spi_device_tpm_all.537770051
Short name T670
Test name
Test status
Simulation time 5575519042 ps
CPU time 18.17 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 221472 kb
Host smart-d7ee4272-4549-4840-9430-be61988d8e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537770051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.537770051
Directory /workspace/28.spi_device_tpm_all/latest


Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3562873795
Short name T584
Test name
Test status
Simulation time 3513884195 ps
CPU time 5.14 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 217224 kb
Host smart-71d32915-9a59-4999-8f09-7b082122f333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562873795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3562873795
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/28.spi_device_tpm_rw.839233038
Short name T7
Test name
Test status
Simulation time 226366788 ps
CPU time 4.25 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 217092 kb
Host smart-8f1dbdbc-6a9b-4825-99dc-7ca201a7e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839233038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.839233038
Directory /workspace/28.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1774951625
Short name T657
Test name
Test status
Simulation time 49064944 ps
CPU time 0.74 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 206864 kb
Host smart-ac4a4b9c-1926-405a-8a26-63e4fa632b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774951625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1774951625
Directory /workspace/28.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/28.spi_device_upload.1221915449
Short name T174
Test name
Test status
Simulation time 3955382184 ps
CPU time 13.07 seconds
Started Aug 17 06:36:13 PM PDT 24
Finished Aug 17 06:36:26 PM PDT 24
Peak memory 225408 kb
Host smart-c00902f4-c58e-4a3a-8ae5-02f7e15db4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221915449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1221915449
Directory /workspace/28.spi_device_upload/latest


Test location /workspace/coverage/default/29.spi_device_alert_test.130706803
Short name T817
Test name
Test status
Simulation time 46551523 ps
CPU time 0.76 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 206352 kb
Host smart-0d6ee5f5-6b9c-41c1-a640-32f0bc512873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130706803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.130706803
Directory /workspace/29.spi_device_alert_test/latest


Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1849187667
Short name T578
Test name
Test status
Simulation time 2878232777 ps
CPU time 9.13 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 233716 kb
Host smart-9c13b328-611e-4e9b-8927-799da70f404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849187667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1849187667
Directory /workspace/29.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/29.spi_device_csb_read.517424088
Short name T766
Test name
Test status
Simulation time 15533819 ps
CPU time 0.73 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 206696 kb
Host smart-6626e1ab-d3a0-411c-b841-83947ec89328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517424088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.517424088
Directory /workspace/29.spi_device_csb_read/latest


Test location /workspace/coverage/default/29.spi_device_flash_all.2228268066
Short name T382
Test name
Test status
Simulation time 1218598091 ps
CPU time 22.99 seconds
Started Aug 17 06:36:32 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 233568 kb
Host smart-4fb2797b-b955-4304-8664-1afffb5c00da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228268066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2228268066
Directory /workspace/29.spi_device_flash_all/latest


Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2554826073
Short name T344
Test name
Test status
Simulation time 5155195582 ps
CPU time 29.1 seconds
Started Aug 17 06:35:58 PM PDT 24
Finished Aug 17 06:36:27 PM PDT 24
Peak memory 235512 kb
Host smart-cc67a30f-40d7-47e6-abce-0f660ba588b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554826073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2554826073
Directory /workspace/29.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1339595667
Short name T29
Test name
Test status
Simulation time 5798384600 ps
CPU time 31.45 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:40 PM PDT 24
Peak memory 242044 kb
Host smart-3d3582ae-79a2-455a-9264-38058ad4a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339595667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1339595667
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/29.spi_device_flash_mode.3452493437
Short name T559
Test name
Test status
Simulation time 225292537 ps
CPU time 4.27 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 225388 kb
Host smart-5f889866-c78b-4681-bac6-c3cbd2d632ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452493437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3452493437
Directory /workspace/29.spi_device_flash_mode/latest


Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3159514226
Short name T767
Test name
Test status
Simulation time 388730708 ps
CPU time 11.46 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 249952 kb
Host smart-74d972a8-5519-4320-bbc6-5b70075ccbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159514226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3159514226
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/29.spi_device_intercept.2041254673
Short name T236
Test name
Test status
Simulation time 7424447127 ps
CPU time 23.53 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 225428 kb
Host smart-f0eb8615-9be4-4e95-9e49-ccba51b7603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041254673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2041254673
Directory /workspace/29.spi_device_intercept/latest


Test location /workspace/coverage/default/29.spi_device_mailbox.854938350
Short name T999
Test name
Test status
Simulation time 2537651823 ps
CPU time 20.59 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:26 PM PDT 24
Peak memory 241632 kb
Host smart-9865c0dd-1eb2-4b9c-abbe-cb9478b5856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854938350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.854938350
Directory /workspace/29.spi_device_mailbox/latest


Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1095692424
Short name T595
Test name
Test status
Simulation time 8291080263 ps
CPU time 24.55 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 250944 kb
Host smart-613e4a7c-aca8-4856-83de-700625cfc738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095692424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1095692424
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3263443405
Short name T11
Test name
Test status
Simulation time 1526621127 ps
CPU time 5.68 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 233568 kb
Host smart-d9a9c7bc-f1ba-47bf-9ff7-95293820a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263443405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3263443405
Directory /workspace/29.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3719847139
Short name T147
Test name
Test status
Simulation time 169986066 ps
CPU time 4.6 seconds
Started Aug 17 06:36:04 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 224048 kb
Host smart-f7d3d86e-2c56-4ff9-8d23-77c004411246
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3719847139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3719847139
Directory /workspace/29.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/29.spi_device_stress_all.2773894553
Short name T35
Test name
Test status
Simulation time 18929507202 ps
CPU time 137 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:38:26 PM PDT 24
Peak memory 252388 kb
Host smart-2bdb4a8a-71ba-4463-80b6-7ea4f6c98e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773894553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2773894553
Directory /workspace/29.spi_device_stress_all/latest


Test location /workspace/coverage/default/29.spi_device_tpm_all.3819050344
Short name T964
Test name
Test status
Simulation time 5338424073 ps
CPU time 13.7 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 217228 kb
Host smart-768cb16c-042f-4ae3-9065-df44022d9a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819050344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3819050344
Directory /workspace/29.spi_device_tpm_all/latest


Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3062741661
Short name T931
Test name
Test status
Simulation time 1120150778 ps
CPU time 4.98 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 217152 kb
Host smart-8418d523-c5f7-47f6-9080-458fb5db2645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062741661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3062741661
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/29.spi_device_tpm_rw.2338953567
Short name T862
Test name
Test status
Simulation time 376866559 ps
CPU time 2.65 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 217160 kb
Host smart-982e6bda-8ee5-4d7b-8196-124d9c753000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338953567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2338953567
Directory /workspace/29.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.356359090
Short name T519
Test name
Test status
Simulation time 49425119 ps
CPU time 0.92 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:01 PM PDT 24
Peak memory 207876 kb
Host smart-e8d176e2-b4a5-48ad-ad22-43d26d94f7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356359090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.356359090
Directory /workspace/29.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/29.spi_device_upload.471719721
Short name T567
Test name
Test status
Simulation time 17159292870 ps
CPU time 10.84 seconds
Started Aug 17 06:36:17 PM PDT 24
Finished Aug 17 06:36:28 PM PDT 24
Peak memory 229452 kb
Host smart-a12893e0-141b-4d9b-9723-45b32c9f4594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471719721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.471719721
Directory /workspace/29.spi_device_upload/latest


Test location /workspace/coverage/default/3.spi_device_alert_test.566434486
Short name T505
Test name
Test status
Simulation time 46366331 ps
CPU time 0.79 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 205684 kb
Host smart-b61ba2b5-881b-44e4-ac40-d952e144debe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566434486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.566434486
Directory /workspace/3.spi_device_alert_test/latest


Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3668504062
Short name T935
Test name
Test status
Simulation time 344721457 ps
CPU time 3.96 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 233592 kb
Host smart-f7913cf7-0551-4249-810e-5940b6f75ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668504062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3668504062
Directory /workspace/3.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/3.spi_device_csb_read.3595993958
Short name T703
Test name
Test status
Simulation time 134498772 ps
CPU time 0.77 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 207712 kb
Host smart-014e08b3-7e72-46c4-b5ce-ee4aab74140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595993958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3595993958
Directory /workspace/3.spi_device_csb_read/latest


Test location /workspace/coverage/default/3.spi_device_flash_all.2689165388
Short name T650
Test name
Test status
Simulation time 6853668049 ps
CPU time 58.8 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:36:05 PM PDT 24
Peak memory 241908 kb
Host smart-341391d5-4532-4ac6-b7b6-5337bfb05502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689165388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2689165388
Directory /workspace/3.spi_device_flash_all/latest


Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4083506473
Short name T209
Test name
Test status
Simulation time 32169382967 ps
CPU time 317.74 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:40:20 PM PDT 24
Peak memory 267376 kb
Host smart-85ec6dff-9d5d-458f-94fb-e98a5fbdefba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083506473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4083506473
Directory /workspace/3.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1222594375
Short name T390
Test name
Test status
Simulation time 38282978919 ps
CPU time 182.26 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:38:11 PM PDT 24
Peak memory 266508 kb
Host smart-039b1546-bc8d-4d25-b2ac-bbdcbd72aba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222594375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1222594375
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/3.spi_device_flash_mode.231821564
Short name T506
Test name
Test status
Simulation time 1195475867 ps
CPU time 7.08 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 233620 kb
Host smart-2c1ea5a2-61a3-4088-94ab-0cb2cbfe3c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231821564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.231821564
Directory /workspace/3.spi_device_flash_mode/latest


Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1361585619
Short name T167
Test name
Test status
Simulation time 82519742982 ps
CPU time 139.07 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:37:25 PM PDT 24
Peak memory 250500 kb
Host smart-541324d9-d7d6-4352-8f7f-5dd700896f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361585619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1361585619
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/3.spi_device_intercept.3133301522
Short name T239
Test name
Test status
Simulation time 29329150630 ps
CPU time 19.02 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:23 PM PDT 24
Peak memory 225508 kb
Host smart-d10e432b-4290-45ac-9d0c-8841bb47c509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133301522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3133301522
Directory /workspace/3.spi_device_intercept/latest


Test location /workspace/coverage/default/3.spi_device_mailbox.2732393388
Short name T729
Test name
Test status
Simulation time 9072081087 ps
CPU time 17.31 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:21 PM PDT 24
Peak memory 233732 kb
Host smart-105b2d37-ab43-42b5-82cd-0d40f6c0ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732393388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2732393388
Directory /workspace/3.spi_device_mailbox/latest


Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.241335669
Short name T82
Test name
Test status
Simulation time 2102290315 ps
CPU time 5.58 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 225300 kb
Host smart-87efc44e-64bf-459c-a79c-8817bfc193b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241335669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
241335669
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.549811855
Short name T751
Test name
Test status
Simulation time 15892523767 ps
CPU time 14.25 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:21 PM PDT 24
Peak memory 233624 kb
Host smart-1556bcee-0c3c-419e-b10f-6581fed4d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549811855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.549811855
Directory /workspace/3.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.987151096
Short name T573
Test name
Test status
Simulation time 455892734 ps
CPU time 3.94 seconds
Started Aug 17 06:35:26 PM PDT 24
Finished Aug 17 06:35:30 PM PDT 24
Peak memory 220216 kb
Host smart-c8bf8b9f-096f-4c7d-bdc5-cae5a029b5f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=987151096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.987151096
Directory /workspace/3.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/3.spi_device_sec_cm.3876692281
Short name T70
Test name
Test status
Simulation time 55168780 ps
CPU time 1.04 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 237188 kb
Host smart-48f34dd9-bf07-4003-af57-14454c140df6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876692281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3876692281
Directory /workspace/3.spi_device_sec_cm/latest


Test location /workspace/coverage/default/3.spi_device_stress_all.946239592
Short name T141
Test name
Test status
Simulation time 27740334140 ps
CPU time 223.56 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:38:47 PM PDT 24
Peak memory 271912 kb
Host smart-f4f231da-6e38-421c-afa4-913b37ab9efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946239592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.946239592
Directory /workspace/3.spi_device_stress_all/latest


Test location /workspace/coverage/default/3.spi_device_tpm_all.3023810679
Short name T425
Test name
Test status
Simulation time 5763642535 ps
CPU time 31.94 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:36 PM PDT 24
Peak memory 217352 kb
Host smart-716d33d8-3044-4cb3-9ed9-30baf19c5234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023810679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3023810679
Directory /workspace/3.spi_device_tpm_all/latest


Test location /workspace/coverage/default/3.spi_device_tpm_rw.343510519
Short name T783
Test name
Test status
Simulation time 80525176 ps
CPU time 1.11 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 208868 kb
Host smart-b33915ca-5cd8-4c18-b9f7-9f1c7ea19b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343510519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.343510519
Directory /workspace/3.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3629492700
Short name T434
Test name
Test status
Simulation time 63743884 ps
CPU time 0.82 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 206820 kb
Host smart-bd2a7054-3e4b-4de9-be38-b2b6277cb10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629492700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3629492700
Directory /workspace/3.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/3.spi_device_upload.551408557
Short name T706
Test name
Test status
Simulation time 299703239 ps
CPU time 2.58 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 233568 kb
Host smart-8b0d46f5-9419-4e0d-8030-67a848133848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551408557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.551408557
Directory /workspace/3.spi_device_upload/latest


Test location /workspace/coverage/default/30.spi_device_alert_test.4260580196
Short name T352
Test name
Test status
Simulation time 14667358 ps
CPU time 0.76 seconds
Started Aug 17 06:36:13 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 205728 kb
Host smart-ff5a2280-0b57-402c-816f-8165a5e96282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260580196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4260580196
Directory /workspace/30.spi_device_alert_test/latest


Test location /workspace/coverage/default/30.spi_device_cfg_cmd.926578970
Short name T709
Test name
Test status
Simulation time 816659328 ps
CPU time 6.77 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 225296 kb
Host smart-c840d5ae-ebf0-4bb9-84a7-9d2dcbbef5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926578970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.926578970
Directory /workspace/30.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/30.spi_device_csb_read.3881943326
Short name T878
Test name
Test status
Simulation time 92032083 ps
CPU time 0.76 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 206340 kb
Host smart-61fa8220-8bb7-4d26-afd4-c86fce97b4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881943326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3881943326
Directory /workspace/30.spi_device_csb_read/latest


Test location /workspace/coverage/default/30.spi_device_flash_all.2983836393
Short name T960
Test name
Test status
Simulation time 2790700810 ps
CPU time 47.27 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 249868 kb
Host smart-982ec3da-64ff-44d9-bf98-b3992a74713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983836393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2983836393
Directory /workspace/30.spi_device_flash_all/latest


Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1470761445
Short name T467
Test name
Test status
Simulation time 17090175369 ps
CPU time 43.34 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:50 PM PDT 24
Peak memory 252112 kb
Host smart-444085c8-2c0f-4158-aca8-ff4fa49bcb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470761445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1470761445
Directory /workspace/30.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.190274164
Short name T822
Test name
Test status
Simulation time 8733469407 ps
CPU time 38.8 seconds
Started Aug 17 06:36:18 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 250244 kb
Host smart-2f19efc6-463e-4c50-bb06-98d29e05671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190274164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.190274164
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/30.spi_device_flash_mode.462504205
Short name T518
Test name
Test status
Simulation time 1931972902 ps
CPU time 13.67 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:20 PM PDT 24
Peak memory 233604 kb
Host smart-b8587de1-c547-423e-a820-26d47aaa0976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462504205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.462504205
Directory /workspace/30.spi_device_flash_mode/latest


Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.568669164
Short name T909
Test name
Test status
Simulation time 1772205203 ps
CPU time 31.83 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 241744 kb
Host smart-5820cea3-2b57-4c64-9569-6d60d9029c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568669164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.568669164
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/30.spi_device_intercept.2481402700
Short name T846
Test name
Test status
Simulation time 8169068297 ps
CPU time 30.33 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 233752 kb
Host smart-1d42bb62-ff53-488f-bb71-89c3249e98bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481402700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2481402700
Directory /workspace/30.spi_device_intercept/latest


Test location /workspace/coverage/default/30.spi_device_mailbox.204550811
Short name T256
Test name
Test status
Simulation time 1589343968 ps
CPU time 7.76 seconds
Started Aug 17 06:36:10 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 225372 kb
Host smart-c99faae0-6706-4638-81c0-1bfac038f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204550811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.204550811
Directory /workspace/30.spi_device_mailbox/latest


Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2419061225
Short name T471
Test name
Test status
Simulation time 94565234 ps
CPU time 3.11 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 233572 kb
Host smart-0ec10842-a630-4b77-b8ce-3f8acecbd4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419061225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2419061225
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4219447097
Short name T98
Test name
Test status
Simulation time 3000785025 ps
CPU time 9.88 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 233720 kb
Host smart-07cce16a-3ff2-4352-8f82-33fea3443efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219447097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4219447097
Directory /workspace/30.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.122842109
Short name T734
Test name
Test status
Simulation time 123334683 ps
CPU time 4.63 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:11 PM PDT 24
Peak memory 224068 kb
Host smart-9c14ea07-17cd-4f3f-9686-89323ab84d57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122842109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.122842109
Directory /workspace/30.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/30.spi_device_stress_all.2793598246
Short name T537
Test name
Test status
Simulation time 16257310944 ps
CPU time 105.86 seconds
Started Aug 17 06:36:14 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 263400 kb
Host smart-56e00b56-aa09-4bc1-9678-697d04393e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793598246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2793598246
Directory /workspace/30.spi_device_stress_all/latest


Test location /workspace/coverage/default/30.spi_device_tpm_all.2012031633
Short name T340
Test name
Test status
Simulation time 7211838500 ps
CPU time 42.13 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:42 PM PDT 24
Peak memory 217492 kb
Host smart-6ea73dfb-dfb7-47d7-a850-d667019b77d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012031633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2012031633
Directory /workspace/30.spi_device_tpm_all/latest


Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.99584613
Short name T603
Test name
Test status
Simulation time 330140043 ps
CPU time 2.52 seconds
Started Aug 17 06:36:07 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 217144 kb
Host smart-21b0fc48-781e-443d-ac96-4156a255d2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99584613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.99584613
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/30.spi_device_tpm_rw.2898036493
Short name T521
Test name
Test status
Simulation time 948364083 ps
CPU time 2.27 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:02 PM PDT 24
Peak memory 217124 kb
Host smart-f208d680-bb49-474a-8fa6-d02f15886ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898036493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2898036493
Directory /workspace/30.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2413565532
Short name T922
Test name
Test status
Simulation time 80162964 ps
CPU time 0.79 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 206716 kb
Host smart-132294fa-fef9-468d-8a4a-b23b8f814f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413565532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2413565532
Directory /workspace/30.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/30.spi_device_upload.2028373908
Short name T754
Test name
Test status
Simulation time 4097633599 ps
CPU time 16.33 seconds
Started Aug 17 06:35:57 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 250112 kb
Host smart-b2c53e53-a303-4946-8759-18f7490528be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028373908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2028373908
Directory /workspace/30.spi_device_upload/latest


Test location /workspace/coverage/default/31.spi_device_alert_test.2472388051
Short name T447
Test name
Test status
Simulation time 12632632 ps
CPU time 0.75 seconds
Started Aug 17 06:36:16 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 206620 kb
Host smart-f27f65aa-3cf2-4dd5-843e-c374006bc90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472388051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2472388051
Directory /workspace/31.spi_device_alert_test/latest


Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3225051186
Short name T949
Test name
Test status
Simulation time 454223020 ps
CPU time 2.61 seconds
Started Aug 17 06:36:13 PM PDT 24
Finished Aug 17 06:36:16 PM PDT 24
Peak memory 233548 kb
Host smart-7f67d4d6-362b-4ac4-9b23-d012596e6fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225051186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3225051186
Directory /workspace/31.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/31.spi_device_csb_read.983446727
Short name T525
Test name
Test status
Simulation time 49459049 ps
CPU time 0.76 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 206404 kb
Host smart-c876e378-5f86-45cd-afdb-fe359b9dfd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983446727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.983446727
Directory /workspace/31.spi_device_csb_read/latest


Test location /workspace/coverage/default/31.spi_device_flash_all.2009721806
Short name T378
Test name
Test status
Simulation time 37825463042 ps
CPU time 35.13 seconds
Started Aug 17 06:36:13 PM PDT 24
Finished Aug 17 06:36:48 PM PDT 24
Peak memory 250040 kb
Host smart-a66f5a3b-9a0b-4b08-a21a-53ed48a3f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009721806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2009721806
Directory /workspace/31.spi_device_flash_all/latest


Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.473706520
Short name T854
Test name
Test status
Simulation time 8297617115 ps
CPU time 46.23 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 234096 kb
Host smart-d8bf43eb-a1c8-4d53-b90d-1c57c86c7e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473706520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.473706520
Directory /workspace/31.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1055296215
Short name T582
Test name
Test status
Simulation time 39888410703 ps
CPU time 94.11 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:37:36 PM PDT 24
Peak memory 251256 kb
Host smart-7fe2e2f4-69da-4d27-a1e0-0120616a5d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055296215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1055296215
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3817390439
Short name T539
Test name
Test status
Simulation time 5070765079 ps
CPU time 22.46 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:24 PM PDT 24
Peak memory 241904 kb
Host smart-a86625d5-e873-44f2-ad0f-99989a6d1b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817390439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3817390439
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/31.spi_device_intercept.594656972
Short name T1009
Test name
Test status
Simulation time 5222910864 ps
CPU time 25.11 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:27 PM PDT 24
Peak memory 221044 kb
Host smart-275f5542-4e77-4d5c-905e-816aa8edf163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594656972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.594656972
Directory /workspace/31.spi_device_intercept/latest


Test location /workspace/coverage/default/31.spi_device_mailbox.3992103403
Short name T481
Test name
Test status
Simulation time 3880209395 ps
CPU time 12.22 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 233672 kb
Host smart-d3e4f1c7-e65e-40fb-a6b2-9b15935b8f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992103403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3992103403
Directory /workspace/31.spi_device_mailbox/latest


Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1206408262
Short name T990
Test name
Test status
Simulation time 107592213 ps
CPU time 2.25 seconds
Started Aug 17 06:36:07 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 227688 kb
Host smart-096e7347-fada-4608-9475-99c57259d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206408262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1206408262
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3658994993
Short name T632
Test name
Test status
Simulation time 4730272649 ps
CPU time 16.84 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:19 PM PDT 24
Peak memory 233644 kb
Host smart-dc90ce42-ba8d-4c7c-98b5-0a34c27a25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658994993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3658994993
Directory /workspace/31.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3372183196
Short name T137
Test name
Test status
Simulation time 2035052038 ps
CPU time 7.02 seconds
Started Aug 17 06:35:59 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 222904 kb
Host smart-151ba96d-4ef0-45c7-9b22-1ca44deecba3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3372183196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3372183196
Directory /workspace/31.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/31.spi_device_stress_all.1661569849
Short name T797
Test name
Test status
Simulation time 14495710262 ps
CPU time 45.56 seconds
Started Aug 17 06:36:22 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 251184 kb
Host smart-75ebc06f-ace7-4404-a75d-224e814a6adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661569849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1661569849
Directory /workspace/31.spi_device_stress_all/latest


Test location /workspace/coverage/default/31.spi_device_tpm_all.1095124348
Short name T743
Test name
Test status
Simulation time 1894041352 ps
CPU time 15.44 seconds
Started Aug 17 06:36:05 PM PDT 24
Finished Aug 17 06:36:21 PM PDT 24
Peak memory 220392 kb
Host smart-6451fdf4-ee66-44cf-a01a-e7f460dea9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095124348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1095124348
Directory /workspace/31.spi_device_tpm_all/latest


Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1049113272
Short name T890
Test name
Test status
Simulation time 2465487950 ps
CPU time 5.73 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:36:06 PM PDT 24
Peak memory 217292 kb
Host smart-e3904eab-3ffa-4e7b-b6ae-c9b7dd26bb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049113272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1049113272
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/31.spi_device_tpm_rw.2392776019
Short name T596
Test name
Test status
Simulation time 82882320 ps
CPU time 1.39 seconds
Started Aug 17 06:36:07 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 217232 kb
Host smart-e8f9a765-d348-4b07-8e49-aec35a89a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392776019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2392776019
Directory /workspace/31.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.902413489
Short name T432
Test name
Test status
Simulation time 54098215 ps
CPU time 0.89 seconds
Started Aug 17 06:36:02 PM PDT 24
Finished Aug 17 06:36:03 PM PDT 24
Peak memory 206832 kb
Host smart-3301ca93-82ed-42b3-80d7-6ef48b337850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902413489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.902413489
Directory /workspace/31.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/31.spi_device_upload.2875950311
Short name T550
Test name
Test status
Simulation time 34245045 ps
CPU time 2.39 seconds
Started Aug 17 06:36:01 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 225048 kb
Host smart-3b9ceb50-1cfc-4819-bf5d-32b426982a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875950311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2875950311
Directory /workspace/31.spi_device_upload/latest


Test location /workspace/coverage/default/32.spi_device_alert_test.947386435
Short name T700
Test name
Test status
Simulation time 58917114 ps
CPU time 0.74 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 205676 kb
Host smart-dd9e7456-f3f3-4b4e-b85d-6008f577df55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947386435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.947386435
Directory /workspace/32.spi_device_alert_test/latest


Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2891473271
Short name T821
Test name
Test status
Simulation time 5682116200 ps
CPU time 18.43 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:25 PM PDT 24
Peak memory 225396 kb
Host smart-4c9be9bb-af6f-454c-b80a-4e109e47c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891473271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2891473271
Directory /workspace/32.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/32.spi_device_csb_read.2586797411
Short name T733
Test name
Test status
Simulation time 31990728 ps
CPU time 0.76 seconds
Started Aug 17 06:36:03 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 206716 kb
Host smart-ed4cd54c-d0f9-469c-b009-8e269c58c375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586797411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2586797411
Directory /workspace/32.spi_device_csb_read/latest


Test location /workspace/coverage/default/32.spi_device_flash_all.3811332857
Short name T815
Test name
Test status
Simulation time 3276344151 ps
CPU time 68.25 seconds
Started Aug 17 06:36:00 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 257740 kb
Host smart-80474a1e-3e29-4f65-9a21-b0409a1b0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811332857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3811332857
Directory /workspace/32.spi_device_flash_all/latest


Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1396090369
Short name T238
Test name
Test status
Simulation time 48249729871 ps
CPU time 162.34 seconds
Started Aug 17 06:36:18 PM PDT 24
Finished Aug 17 06:39:01 PM PDT 24
Peak memory 257472 kb
Host smart-db376c63-3ce9-4056-ad5d-1c3a08055367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396090369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1396090369
Directory /workspace/32.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2326095287
Short name T1008
Test name
Test status
Simulation time 1760100494 ps
CPU time 27.67 seconds
Started Aug 17 06:36:20 PM PDT 24
Finished Aug 17 06:36:48 PM PDT 24
Peak memory 233680 kb
Host smart-08b3687b-be87-4602-97ed-ce425b5cc581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326095287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2326095287
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/32.spi_device_flash_mode.1238020645
Short name T888
Test name
Test status
Simulation time 1139179199 ps
CPU time 6.66 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 225324 kb
Host smart-59060248-8fac-4cae-ba8f-d5ba4db47919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238020645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1238020645
Directory /workspace/32.spi_device_flash_mode/latest


Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2964157505
Short name T220
Test name
Test status
Simulation time 22442987507 ps
CPU time 154.87 seconds
Started Aug 17 06:36:16 PM PDT 24
Finished Aug 17 06:38:51 PM PDT 24
Peak memory 251680 kb
Host smart-ebdce418-26a7-4f59-b7a5-e369733032a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964157505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2964157505
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/32.spi_device_intercept.212285333
Short name T222
Test name
Test status
Simulation time 2054252235 ps
CPU time 9.42 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:22 PM PDT 24
Peak memory 225336 kb
Host smart-99ec1586-39d2-4515-a1c8-5ff01433b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212285333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.212285333
Directory /workspace/32.spi_device_intercept/latest


Test location /workspace/coverage/default/32.spi_device_mailbox.2364419685
Short name T704
Test name
Test status
Simulation time 222235768 ps
CPU time 4.73 seconds
Started Aug 17 06:36:27 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 225308 kb
Host smart-8b315ccb-e788-4363-a733-1531f917a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364419685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2364419685
Directory /workspace/32.spi_device_mailbox/latest


Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3026483833
Short name T517
Test name
Test status
Simulation time 1942888106 ps
CPU time 6.77 seconds
Started Aug 17 06:36:25 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 233556 kb
Host smart-c05dfa38-46b3-4600-834f-85aa5ab5858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026483833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3026483833
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1683676925
Short name T829
Test name
Test status
Simulation time 986990119 ps
CPU time 8.76 seconds
Started Aug 17 06:36:11 PM PDT 24
Finished Aug 17 06:36:25 PM PDT 24
Peak memory 225340 kb
Host smart-d87591c5-0845-4ffc-9b1c-a7479c79198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683676925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1683676925
Directory /workspace/32.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3606235793
Short name T877
Test name
Test status
Simulation time 625623872 ps
CPU time 6.78 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 221360 kb
Host smart-0ed2abb0-48f3-4eaa-b5fc-ac1a74220a02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3606235793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3606235793
Directory /workspace/32.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/32.spi_device_stress_all.2454456921
Short name T397
Test name
Test status
Simulation time 209040149 ps
CPU time 1 seconds
Started Aug 17 06:36:16 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 207732 kb
Host smart-b93240b9-c167-4bb8-bbe0-3ae9f49b75e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454456921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2454456921
Directory /workspace/32.spi_device_stress_all/latest


Test location /workspace/coverage/default/32.spi_device_tpm_all.4187930513
Short name T327
Test name
Test status
Simulation time 5255780687 ps
CPU time 23.02 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 217444 kb
Host smart-e318e87b-b4d4-4ad2-b17c-e2aadac1e9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187930513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4187930513
Directory /workspace/32.spi_device_tpm_all/latest


Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.688963863
Short name T553
Test name
Test status
Simulation time 14072818379 ps
CPU time 13.65 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:25 PM PDT 24
Peak memory 217368 kb
Host smart-fa2ea88b-f1a2-4d09-abce-74030abe1050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688963863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.688963863
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/32.spi_device_tpm_rw.3127162593
Short name T335
Test name
Test status
Simulation time 310337251 ps
CPU time 2.22 seconds
Started Aug 17 06:36:26 PM PDT 24
Finished Aug 17 06:36:29 PM PDT 24
Peak memory 217176 kb
Host smart-9d4c5c44-15f4-444e-b196-089356000cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127162593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3127162593
Directory /workspace/32.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3915059643
Short name T363
Test name
Test status
Simulation time 114600230 ps
CPU time 0.79 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:07 PM PDT 24
Peak memory 206832 kb
Host smart-57c18098-0485-4709-b180-bed01cf5bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915059643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3915059643
Directory /workspace/32.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/32.spi_device_upload.1586967144
Short name T645
Test name
Test status
Simulation time 904722860 ps
CPU time 8.12 seconds
Started Aug 17 06:36:04 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 233628 kb
Host smart-71ab8c1a-c835-4aa8-8a46-e3b31a0c1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586967144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1586967144
Directory /workspace/32.spi_device_upload/latest


Test location /workspace/coverage/default/33.spi_device_alert_test.2913571835
Short name T470
Test name
Test status
Simulation time 14440309 ps
CPU time 0.72 seconds
Started Aug 17 06:36:11 PM PDT 24
Finished Aug 17 06:36:12 PM PDT 24
Peak memory 205708 kb
Host smart-eb10ac14-9804-49ad-9abb-c62893103435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913571835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2913571835
Directory /workspace/33.spi_device_alert_test/latest


Test location /workspace/coverage/default/33.spi_device_cfg_cmd.327629073
Short name T17
Test name
Test status
Simulation time 1143661448 ps
CPU time 3.89 seconds
Started Aug 17 06:36:15 PM PDT 24
Finished Aug 17 06:36:19 PM PDT 24
Peak memory 233560 kb
Host smart-e56cf610-728f-4cdc-b42f-e842f7345ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327629073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.327629073
Directory /workspace/33.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/33.spi_device_csb_read.3050577502
Short name T757
Test name
Test status
Simulation time 15389357 ps
CPU time 0.75 seconds
Started Aug 17 06:36:08 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 207464 kb
Host smart-908f8142-2efd-4a4c-a6ea-e1133a5f4440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050577502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3050577502
Directory /workspace/33.spi_device_csb_read/latest


Test location /workspace/coverage/default/33.spi_device_flash_all.3741702500
Short name T629
Test name
Test status
Simulation time 11578927 ps
CPU time 0.74 seconds
Started Aug 17 06:36:23 PM PDT 24
Finished Aug 17 06:36:24 PM PDT 24
Peak memory 216640 kb
Host smart-c919a607-2797-4148-816c-659b4b587aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741702500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3741702500
Directory /workspace/33.spi_device_flash_all/latest


Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2290817578
Short name T866
Test name
Test status
Simulation time 2092440473 ps
CPU time 42.3 seconds
Started Aug 17 06:36:25 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 256744 kb
Host smart-99edb114-8ee6-44de-bab2-c2d6f0aad2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290817578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2290817578
Directory /workspace/33.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.529186718
Short name T812
Test name
Test status
Simulation time 6563686438 ps
CPU time 56.12 seconds
Started Aug 17 06:36:27 PM PDT 24
Finished Aug 17 06:37:23 PM PDT 24
Peak memory 225620 kb
Host smart-591ccd8e-078e-401f-8a48-38ae8c8d67a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529186718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.529186718
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/33.spi_device_flash_mode.2301162394
Short name T639
Test name
Test status
Simulation time 121827645 ps
CPU time 6.85 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 225300 kb
Host smart-ad6dc13b-75b5-4eb2-8d45-d43ed921d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301162394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2301162394
Directory /workspace/33.spi_device_flash_mode/latest


Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3694248699
Short name T200
Test name
Test status
Simulation time 125564742749 ps
CPU time 134.25 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 265264 kb
Host smart-7106304d-ce69-4b53-91ac-2a6d003a6e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694248699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3694248699
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/33.spi_device_intercept.2197480309
Short name T284
Test name
Test status
Simulation time 2514097849 ps
CPU time 14.41 seconds
Started Aug 17 06:36:13 PM PDT 24
Finished Aug 17 06:36:28 PM PDT 24
Peak memory 225444 kb
Host smart-42bf6144-e568-4cd4-a870-e1bb233650ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197480309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2197480309
Directory /workspace/33.spi_device_intercept/latest


Test location /workspace/coverage/default/33.spi_device_mailbox.3526877937
Short name T707
Test name
Test status
Simulation time 671743886 ps
CPU time 9.5 seconds
Started Aug 17 06:36:04 PM PDT 24
Finished Aug 17 06:36:13 PM PDT 24
Peak memory 241512 kb
Host smart-5e3386af-e414-4281-b105-1178db46b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526877937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3526877937
Directory /workspace/33.spi_device_mailbox/latest


Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4188693862
Short name T731
Test name
Test status
Simulation time 3381202501 ps
CPU time 7.77 seconds
Started Aug 17 06:36:12 PM PDT 24
Finished Aug 17 06:36:20 PM PDT 24
Peak memory 233680 kb
Host smart-fc653e34-f2ff-490a-ae6b-9c1021a4087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188693862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4188693862
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.970814170
Short name T880
Test name
Test status
Simulation time 1899888536 ps
CPU time 6.36 seconds
Started Aug 17 06:36:16 PM PDT 24
Finished Aug 17 06:36:23 PM PDT 24
Peak memory 233604 kb
Host smart-62b2e248-3921-43bd-9e00-18fe0485d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970814170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.970814170
Directory /workspace/33.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.165425505
Short name T148
Test name
Test status
Simulation time 7144427435 ps
CPU time 15.03 seconds
Started Aug 17 06:36:10 PM PDT 24
Finished Aug 17 06:36:25 PM PDT 24
Peak memory 219856 kb
Host smart-7227b5f9-a43a-4d86-a6c0-38f5b77f2cd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=165425505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.165425505
Directory /workspace/33.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/33.spi_device_tpm_all.4003263953
Short name T853
Test name
Test status
Simulation time 10722341090 ps
CPU time 6.33 seconds
Started Aug 17 06:36:04 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 217528 kb
Host smart-44409e26-85ee-4bde-abd9-7fa61292e3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003263953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4003263953
Directory /workspace/33.spi_device_tpm_all/latest


Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2726051723
Short name T343
Test name
Test status
Simulation time 1172773440 ps
CPU time 7.26 seconds
Started Aug 17 06:36:06 PM PDT 24
Finished Aug 17 06:36:14 PM PDT 24
Peak memory 217200 kb
Host smart-847927e3-dd44-41e3-a4b1-9946bcfb1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726051723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2726051723
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/33.spi_device_tpm_rw.1012611888
Short name T710
Test name
Test status
Simulation time 24653897 ps
CPU time 0.82 seconds
Started Aug 17 06:36:07 PM PDT 24
Finished Aug 17 06:36:08 PM PDT 24
Peak memory 207356 kb
Host smart-9adaeaf0-0308-4dcb-9ac5-6e05d204e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012611888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1012611888
Directory /workspace/33.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1803831169
Short name T1003
Test name
Test status
Simulation time 68269088 ps
CPU time 0.82 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:36:10 PM PDT 24
Peak memory 206840 kb
Host smart-625f9666-a67f-410f-b5dc-abd52affbc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803831169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1803831169
Directory /workspace/33.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/33.spi_device_upload.2783984480
Short name T448
Test name
Test status
Simulation time 2711258930 ps
CPU time 6.65 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:36:15 PM PDT 24
Peak memory 233664 kb
Host smart-0c126ccd-5074-46be-aa03-6580144db3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783984480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2783984480
Directory /workspace/33.spi_device_upload/latest


Test location /workspace/coverage/default/34.spi_device_alert_test.3330728755
Short name T367
Test name
Test status
Simulation time 261914483 ps
CPU time 0.78 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:36:31 PM PDT 24
Peak memory 206284 kb
Host smart-5d9b6bb0-c6fc-4f14-a1d6-3e44bb47b2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330728755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3330728755
Directory /workspace/34.spi_device_alert_test/latest


Test location /workspace/coverage/default/34.spi_device_cfg_cmd.722275803
Short name T897
Test name
Test status
Simulation time 8112670589 ps
CPU time 26.39 seconds
Started Aug 17 06:36:32 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 233760 kb
Host smart-d065ad1d-811a-46dc-a317-ca2ad5da572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722275803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.722275803
Directory /workspace/34.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/34.spi_device_csb_read.1114978312
Short name T438
Test name
Test status
Simulation time 47876283 ps
CPU time 0.8 seconds
Started Aug 17 06:36:17 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 207416 kb
Host smart-a5a102ca-1e0f-4269-a602-5eefb06389c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114978312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1114978312
Directory /workspace/34.spi_device_csb_read/latest


Test location /workspace/coverage/default/34.spi_device_flash_all.3129256786
Short name T685
Test name
Test status
Simulation time 3520621407 ps
CPU time 50.59 seconds
Started Aug 17 06:36:28 PM PDT 24
Finished Aug 17 06:37:19 PM PDT 24
Peak memory 250068 kb
Host smart-58312660-f59b-46cb-ae07-0fa70aa5f3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129256786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3129256786
Directory /workspace/34.spi_device_flash_all/latest


Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3162365748
Short name T610
Test name
Test status
Simulation time 79087690908 ps
CPU time 64.66 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:37:14 PM PDT 24
Peak memory 238152 kb
Host smart-d1840f35-c4ce-42f0-bf98-119bb6165a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162365748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3162365748
Directory /workspace/34.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2165869515
Short name T997
Test name
Test status
Simulation time 1985620568 ps
CPU time 34.54 seconds
Started Aug 17 06:36:17 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 240360 kb
Host smart-b38a6ee2-fedc-47f6-a969-dd43fd24421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165869515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2165869515
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/34.spi_device_flash_mode.4291972006
Short name T320
Test name
Test status
Simulation time 1732646137 ps
CPU time 20.52 seconds
Started Aug 17 06:36:11 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 233588 kb
Host smart-49720ded-e69b-4206-b531-f4d59170d4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291972006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4291972006
Directory /workspace/34.spi_device_flash_mode/latest


Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1785894210
Short name T442
Test name
Test status
Simulation time 42478800 ps
CPU time 0.87 seconds
Started Aug 17 06:36:21 PM PDT 24
Finished Aug 17 06:36:21 PM PDT 24
Peak memory 216908 kb
Host smart-6962b111-30f5-4829-9cc3-de7fa549ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785894210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1785894210
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/34.spi_device_intercept.927168894
Short name T1001
Test name
Test status
Simulation time 3730865197 ps
CPU time 24.1 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 220992 kb
Host smart-47facd3b-aa7c-413b-b274-2d193235f460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927168894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.927168894
Directory /workspace/34.spi_device_intercept/latest


Test location /workspace/coverage/default/34.spi_device_mailbox.374568037
Short name T250
Test name
Test status
Simulation time 2014574556 ps
CPU time 8.44 seconds
Started Aug 17 06:36:09 PM PDT 24
Finished Aug 17 06:36:17 PM PDT 24
Peak memory 233612 kb
Host smart-2fa7aac8-2fc4-4dfc-a6bf-3319fc2966b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374568037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.374568037
Directory /workspace/34.spi_device_mailbox/latest


Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3140579082
Short name T672
Test name
Test status
Simulation time 1153047281 ps
CPU time 5.8 seconds
Started Aug 17 06:36:18 PM PDT 24
Finished Aug 17 06:36:24 PM PDT 24
Peak memory 241232 kb
Host smart-d984e3c8-2ec8-4e08-a03e-8486b01d6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140579082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3140579082
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1965409769
Short name T224
Test name
Test status
Simulation time 12200940441 ps
CPU time 11.49 seconds
Started Aug 17 06:36:10 PM PDT 24
Finished Aug 17 06:36:21 PM PDT 24
Peak memory 233628 kb
Host smart-254e3ba5-4a5c-466e-b0f0-271add1b9b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965409769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1965409769
Directory /workspace/34.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2299278717
Short name T454
Test name
Test status
Simulation time 1135194153 ps
CPU time 4.68 seconds
Started Aug 17 06:36:27 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 219772 kb
Host smart-17ac1275-2b2e-4373-afb9-ca1c54c41b3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299278717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2299278717
Directory /workspace/34.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/34.spi_device_stress_all.397732325
Short name T23
Test name
Test status
Simulation time 13203842850 ps
CPU time 25.35 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 225516 kb
Host smart-c082d8c5-4689-421b-a68e-fea23dc97bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397732325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.397732325
Directory /workspace/34.spi_device_stress_all/latest


Test location /workspace/coverage/default/34.spi_device_tpm_all.4001690617
Short name T409
Test name
Test status
Simulation time 3193989034 ps
CPU time 26.23 seconds
Started Aug 17 06:36:35 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 217648 kb
Host smart-6633cf90-4600-4514-a4dd-cbb871ab619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001690617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4001690617
Directory /workspace/34.spi_device_tpm_all/latest


Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.663993370
Short name T364
Test name
Test status
Simulation time 8777343423 ps
CPU time 6.87 seconds
Started Aug 17 06:36:24 PM PDT 24
Finished Aug 17 06:36:31 PM PDT 24
Peak memory 217284 kb
Host smart-1b8c2358-4821-48b5-858f-e0460465d7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663993370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.663993370
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/34.spi_device_tpm_rw.3538619520
Short name T687
Test name
Test status
Simulation time 117342379 ps
CPU time 1.42 seconds
Started Aug 17 06:36:23 PM PDT 24
Finished Aug 17 06:36:24 PM PDT 24
Peak memory 217216 kb
Host smart-58ecc5d6-0e3a-41df-94b9-0b6d8528c1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538619520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3538619520
Directory /workspace/34.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3783650900
Short name T374
Test name
Test status
Simulation time 124722812 ps
CPU time 0.81 seconds
Started Aug 17 06:36:28 PM PDT 24
Finished Aug 17 06:36:29 PM PDT 24
Peak memory 206836 kb
Host smart-6d6edc7b-7448-4c56-ab1e-e46cbcbf89d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783650900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3783650900
Directory /workspace/34.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/34.spi_device_upload.4012697389
Short name T226
Test name
Test status
Simulation time 6867556895 ps
CPU time 24.82 seconds
Started Aug 17 06:36:21 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 233636 kb
Host smart-ef4a7372-1050-496d-afb0-57065ac2980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012697389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4012697389
Directory /workspace/34.spi_device_upload/latest


Test location /workspace/coverage/default/35.spi_device_alert_test.1304352518
Short name T622
Test name
Test status
Simulation time 13303914 ps
CPU time 0.69 seconds
Started Aug 17 06:36:34 PM PDT 24
Finished Aug 17 06:36:34 PM PDT 24
Peak memory 206484 kb
Host smart-d21f4d20-3362-431f-b506-0d4e4b91f835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304352518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1304352518
Directory /workspace/35.spi_device_alert_test/latest


Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2726544295
Short name T586
Test name
Test status
Simulation time 973522843 ps
CPU time 9.78 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:36:40 PM PDT 24
Peak memory 225404 kb
Host smart-eeed9aeb-d51a-461f-b001-390f1d71a7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726544295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2726544295
Directory /workspace/35.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/35.spi_device_csb_read.43755088
Short name T353
Test name
Test status
Simulation time 30577183 ps
CPU time 0.79 seconds
Started Aug 17 06:36:29 PM PDT 24
Finished Aug 17 06:36:30 PM PDT 24
Peak memory 207708 kb
Host smart-42a48982-a12a-4db5-b185-7a5d02b802da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43755088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.43755088
Directory /workspace/35.spi_device_csb_read/latest


Test location /workspace/coverage/default/35.spi_device_flash_all.865530691
Short name T306
Test name
Test status
Simulation time 267240086129 ps
CPU time 460.51 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:44:11 PM PDT 24
Peak memory 266540 kb
Host smart-0a7e8cfa-038d-40e8-8881-c3054cdd8fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865530691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.865530691
Directory /workspace/35.spi_device_flash_all/latest


Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2443836580
Short name T614
Test name
Test status
Simulation time 104526354807 ps
CPU time 962.22 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:52:38 PM PDT 24
Peak memory 274708 kb
Host smart-f77eccfe-a9a9-4e29-bbd4-ccbd8db6641f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443836580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2443836580
Directory /workspace/35.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1041500021
Short name T281
Test name
Test status
Simulation time 10565454593 ps
CPU time 15.38 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 225488 kb
Host smart-31c7bf96-902f-496b-9e8d-3e6bb6e4ab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041500021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1041500021
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/35.spi_device_flash_mode.545565030
Short name T323
Test name
Test status
Simulation time 420707043 ps
CPU time 8.75 seconds
Started Aug 17 06:36:37 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 225380 kb
Host smart-1980884e-bd53-4e4c-9840-48ac821fc8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545565030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.545565030
Directory /workspace/35.spi_device_flash_mode/latest


Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.698268372
Short name T504
Test name
Test status
Simulation time 47378566990 ps
CPU time 170.1 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:39:30 PM PDT 24
Peak memory 253796 kb
Host smart-dc4eb906-f666-451a-9dff-156c5ab3a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698268372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.698268372
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/35.spi_device_intercept.1397930347
Short name T623
Test name
Test status
Simulation time 6019882276 ps
CPU time 22.07 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 233688 kb
Host smart-2f2dcf87-06be-443b-b5d2-e4a9d8aa6524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397930347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1397930347
Directory /workspace/35.spi_device_intercept/latest


Test location /workspace/coverage/default/35.spi_device_mailbox.670169696
Short name T348
Test name
Test status
Simulation time 675898166 ps
CPU time 2.22 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:36:38 PM PDT 24
Peak memory 224564 kb
Host smart-ba869ab4-fd32-4dac-a97a-a57b2f41a1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670169696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.670169696
Directory /workspace/35.spi_device_mailbox/latest


Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3954913658
Short name T593
Test name
Test status
Simulation time 172673587 ps
CPU time 3.07 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:36:33 PM PDT 24
Peak memory 225208 kb
Host smart-36dbef7c-439a-4fc8-ab37-684b07a58e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954913658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3954913658
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.596759508
Short name T717
Test name
Test status
Simulation time 255144861 ps
CPU time 4.14 seconds
Started Aug 17 06:36:34 PM PDT 24
Finished Aug 17 06:36:38 PM PDT 24
Peak memory 233572 kb
Host smart-43f0d888-5bb1-439d-991e-37ca51ff6b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596759508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.596759508
Directory /workspace/35.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3027473420
Short name T146
Test name
Test status
Simulation time 1141848301 ps
CPU time 10.9 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 223952 kb
Host smart-47d11b5f-34a1-4fae-b373-7f2776e36658
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3027473420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3027473420
Directory /workspace/35.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/35.spi_device_stress_all.2303086008
Short name T158
Test name
Test status
Simulation time 6671244063 ps
CPU time 92.53 seconds
Started Aug 17 06:36:28 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 252516 kb
Host smart-e57af54b-b6d8-40c8-9671-e8ece821f99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303086008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2303086008
Directory /workspace/35.spi_device_stress_all/latest


Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1130582928
Short name T898
Test name
Test status
Simulation time 187434665 ps
CPU time 2.18 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:36:44 PM PDT 24
Peak memory 217152 kb
Host smart-ea44b43a-5234-4e5c-b58c-01340a6381f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130582928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1130582928
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/35.spi_device_tpm_rw.3593413840
Short name T1011
Test name
Test status
Simulation time 31073024 ps
CPU time 0.72 seconds
Started Aug 17 06:36:32 PM PDT 24
Finished Aug 17 06:36:33 PM PDT 24
Peak memory 206824 kb
Host smart-e444cb51-36aa-4195-8c60-417548e64bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593413840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3593413840
Directory /workspace/35.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3666941178
Short name T680
Test name
Test status
Simulation time 115846471 ps
CPU time 0.87 seconds
Started Aug 17 06:36:28 PM PDT 24
Finished Aug 17 06:36:29 PM PDT 24
Peak memory 206860 kb
Host smart-fe266757-9b40-4ecd-a0d2-1a96ffdf3a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666941178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3666941178
Directory /workspace/35.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/35.spi_device_upload.643053289
Short name T962
Test name
Test status
Simulation time 11923817299 ps
CPU time 25.23 seconds
Started Aug 17 06:36:34 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 233512 kb
Host smart-345bc9fc-7c1c-4c0d-bc44-fd6bc38c284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643053289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.643053289
Directory /workspace/35.spi_device_upload/latest


Test location /workspace/coverage/default/36.spi_device_alert_test.4116850447
Short name T780
Test name
Test status
Simulation time 101515266 ps
CPU time 0.73 seconds
Started Aug 17 06:36:41 PM PDT 24
Finished Aug 17 06:36:41 PM PDT 24
Peak memory 205644 kb
Host smart-c3fbd28a-7363-40f8-bb84-912e29f4d06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116850447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4116850447
Directory /workspace/36.spi_device_alert_test/latest


Test location /workspace/coverage/default/36.spi_device_cfg_cmd.767536774
Short name T647
Test name
Test status
Simulation time 2348720714 ps
CPU time 12.54 seconds
Started Aug 17 06:36:38 PM PDT 24
Finished Aug 17 06:36:50 PM PDT 24
Peak memory 233732 kb
Host smart-ff418b62-ac46-4bfe-95da-127ab0583e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767536774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.767536774
Directory /workspace/36.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/36.spi_device_csb_read.3712060064
Short name T513
Test name
Test status
Simulation time 34402181 ps
CPU time 0.74 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 206376 kb
Host smart-5ebd06e5-5958-4f83-a618-bd99110ba943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712060064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3712060064
Directory /workspace/36.spi_device_csb_read/latest


Test location /workspace/coverage/default/36.spi_device_flash_all.827800646
Short name T689
Test name
Test status
Simulation time 51826880998 ps
CPU time 89.69 seconds
Started Aug 17 06:36:31 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 253112 kb
Host smart-c4a21171-acbc-41a4-abb5-fabe58afef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827800646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.827800646
Directory /workspace/36.spi_device_flash_all/latest


Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3914331281
Short name T807
Test name
Test status
Simulation time 15671795843 ps
CPU time 98.1 seconds
Started Aug 17 06:36:28 PM PDT 24
Finished Aug 17 06:38:06 PM PDT 24
Peak memory 258404 kb
Host smart-49e40bb2-e555-4cc5-8c86-8731b9a02116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914331281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3914331281
Directory /workspace/36.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.112704618
Short name T221
Test name
Test status
Simulation time 110118931756 ps
CPU time 122.51 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:38:33 PM PDT 24
Peak memory 250164 kb
Host smart-1da822e0-fd4e-4961-9a0f-8abf17628948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112704618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.112704618
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/36.spi_device_flash_mode.1111247944
Short name T894
Test name
Test status
Simulation time 229687062 ps
CPU time 4.51 seconds
Started Aug 17 06:36:38 PM PDT 24
Finished Aug 17 06:36:43 PM PDT 24
Peak memory 225400 kb
Host smart-8ea4e321-671e-417b-9c07-a05d26176f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111247944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1111247944
Directory /workspace/36.spi_device_flash_mode/latest


Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1387783687
Short name T794
Test name
Test status
Simulation time 5004971050 ps
CPU time 33.16 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 250032 kb
Host smart-d2784e18-f339-4fa9-988d-df85df9e329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387783687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1387783687
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/36.spi_device_intercept.1709952535
Short name T230
Test name
Test status
Simulation time 2889254500 ps
CPU time 13.82 seconds
Started Aug 17 06:36:38 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 233692 kb
Host smart-d2ec1192-9634-4db4-95fb-ecca2b28e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709952535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1709952535
Directory /workspace/36.spi_device_intercept/latest


Test location /workspace/coverage/default/36.spi_device_mailbox.3488208202
Short name T130
Test name
Test status
Simulation time 7345793171 ps
CPU time 14.75 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 233708 kb
Host smart-7f6e0d60-f330-469a-8e12-b2967267d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488208202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3488208202
Directory /workspace/36.spi_device_mailbox/latest


Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.312151193
Short name T450
Test name
Test status
Simulation time 51485961 ps
CPU time 2.15 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:36:42 PM PDT 24
Peak memory 224676 kb
Host smart-d5133dbb-adae-49e7-aff2-f0e75507260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312151193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.312151193
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1340782303
Short name T932
Test name
Test status
Simulation time 3684449416 ps
CPU time 19.35 seconds
Started Aug 17 06:36:25 PM PDT 24
Finished Aug 17 06:36:45 PM PDT 24
Peak memory 234900 kb
Host smart-566ad59d-a8e4-4565-b7c3-845842f86727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340782303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1340782303
Directory /workspace/36.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2795210062
Short name T468
Test name
Test status
Simulation time 779874187 ps
CPU time 4.28 seconds
Started Aug 17 06:36:27 PM PDT 24
Finished Aug 17 06:36:32 PM PDT 24
Peak memory 224104 kb
Host smart-e113d948-b3da-48b5-8945-cdd400f9fee2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2795210062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2795210062
Directory /workspace/36.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/36.spi_device_tpm_all.1837954731
Short name T430
Test name
Test status
Simulation time 18777128875 ps
CPU time 28.9 seconds
Started Aug 17 06:36:30 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 217372 kb
Host smart-0f003bdf-5499-4c81-b004-f4da67b16a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837954731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1837954731
Directory /workspace/36.spi_device_tpm_all/latest


Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3282244523
Short name T800
Test name
Test status
Simulation time 2352498975 ps
CPU time 5.26 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:36:42 PM PDT 24
Peak memory 217328 kb
Host smart-30e9f3f9-925f-4933-b90b-6aedbde122d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282244523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3282244523
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/36.spi_device_tpm_rw.488170491
Short name T338
Test name
Test status
Simulation time 265448576 ps
CPU time 1.32 seconds
Started Aug 17 06:36:29 PM PDT 24
Finished Aug 17 06:36:30 PM PDT 24
Peak memory 217192 kb
Host smart-37e86c97-cc03-446d-87a4-f2411b184fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488170491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.488170491
Directory /workspace/36.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1338940114
Short name T12
Test name
Test status
Simulation time 120526392 ps
CPU time 0.85 seconds
Started Aug 17 06:36:35 PM PDT 24
Finished Aug 17 06:36:36 PM PDT 24
Peak memory 206872 kb
Host smart-78db7f3f-b27f-4402-88fb-0e137d21be4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338940114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1338940114
Directory /workspace/36.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/36.spi_device_upload.266436179
Short name T262
Test name
Test status
Simulation time 256497470 ps
CPU time 3.18 seconds
Started Aug 17 06:36:29 PM PDT 24
Finished Aug 17 06:36:33 PM PDT 24
Peak memory 225336 kb
Host smart-ee908a0c-5001-4705-9513-a8461bad51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266436179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.266436179
Directory /workspace/36.spi_device_upload/latest


Test location /workspace/coverage/default/37.spi_device_alert_test.4055529328
Short name T373
Test name
Test status
Simulation time 25703292 ps
CPU time 0.75 seconds
Started Aug 17 06:36:41 PM PDT 24
Finished Aug 17 06:36:42 PM PDT 24
Peak memory 205684 kb
Host smart-b1078cec-bbda-4e1e-8153-a2e79910f148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055529328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4055529328
Directory /workspace/37.spi_device_alert_test/latest


Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3641845643
Short name T255
Test name
Test status
Simulation time 893094005 ps
CPU time 3.49 seconds
Started Aug 17 06:36:35 PM PDT 24
Finished Aug 17 06:36:38 PM PDT 24
Peak memory 225368 kb
Host smart-4ebf7d4a-cd2b-466f-ab9a-32c4cac155cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641845643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3641845643
Directory /workspace/37.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/37.spi_device_csb_read.2490627766
Short name T744
Test name
Test status
Simulation time 89056775 ps
CPU time 0.78 seconds
Started Aug 17 06:36:37 PM PDT 24
Finished Aug 17 06:36:38 PM PDT 24
Peak memory 206392 kb
Host smart-b2931ecd-9886-46dd-906b-78c959a39b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490627766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2490627766
Directory /workspace/37.spi_device_csb_read/latest


Test location /workspace/coverage/default/37.spi_device_flash_all.4258516691
Short name T295
Test name
Test status
Simulation time 48463892401 ps
CPU time 97.54 seconds
Started Aug 17 06:36:33 PM PDT 24
Finished Aug 17 06:38:10 PM PDT 24
Peak memory 240124 kb
Host smart-f6d0af54-a584-4612-a117-8fd055192b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258516691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4258516691
Directory /workspace/37.spi_device_flash_all/latest


Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2253171084
Short name T823
Test name
Test status
Simulation time 114207143089 ps
CPU time 276.76 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:41:19 PM PDT 24
Peak memory 252596 kb
Host smart-193119e7-b5c2-477f-be7d-1f3b3c4a375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253171084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2253171084
Directory /workspace/37.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1332084966
Short name T662
Test name
Test status
Simulation time 12547572768 ps
CPU time 88.79 seconds
Started Aug 17 06:36:48 PM PDT 24
Finished Aug 17 06:38:17 PM PDT 24
Peak memory 254376 kb
Host smart-115b14b4-1ec0-4f45-a4ed-3ed687917662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332084966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1332084966
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/37.spi_device_flash_mode.1250838646
Short name T916
Test name
Test status
Simulation time 3655224680 ps
CPU time 56.57 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 234680 kb
Host smart-53a551ab-0b7a-4720-9340-a261a17281d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250838646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1250838646
Directory /workspace/37.spi_device_flash_mode/latest


Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4016409460
Short name T630
Test name
Test status
Simulation time 128698317771 ps
CPU time 156.2 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:39:16 PM PDT 24
Peak memory 251416 kb
Host smart-4a7eb48d-24a7-4c98-b3c4-e396dc695603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016409460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4016409460
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/37.spi_device_intercept.157375431
Short name T257
Test name
Test status
Simulation time 382154319 ps
CPU time 2.92 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:36:43 PM PDT 24
Peak memory 225292 kb
Host smart-65bfc719-fe40-4add-aa3e-1b7bf02c4fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157375431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.157375431
Directory /workspace/37.spi_device_intercept/latest


Test location /workspace/coverage/default/37.spi_device_mailbox.3119542814
Short name T286
Test name
Test status
Simulation time 627762936 ps
CPU time 3.41 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:36:40 PM PDT 24
Peak memory 225404 kb
Host smart-b16e3f8b-3931-43e4-9c9e-26771bad1dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119542814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3119542814
Directory /workspace/37.spi_device_mailbox/latest


Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3210873821
Short name T638
Test name
Test status
Simulation time 508356785 ps
CPU time 3.01 seconds
Started Aug 17 06:36:39 PM PDT 24
Finished Aug 17 06:36:42 PM PDT 24
Peak memory 233444 kb
Host smart-6789d8b3-0736-42f6-a045-44b2ededaf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210873821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3210873821
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2080356395
Short name T841
Test name
Test status
Simulation time 228327999 ps
CPU time 2.75 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 225244 kb
Host smart-4bb5454d-d3f2-4a99-948b-6d12f83d994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080356395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2080356395
Directory /workspace/37.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3910475360
Short name T562
Test name
Test status
Simulation time 1139350741 ps
CPU time 10.6 seconds
Started Aug 17 06:36:37 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 222560 kb
Host smart-cf26816b-f865-44eb-9823-bf07ca0e0a10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3910475360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3910475360
Directory /workspace/37.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/37.spi_device_stress_all.344190776
Short name T18
Test name
Test status
Simulation time 114515383 ps
CPU time 1.13 seconds
Started Aug 17 06:36:47 PM PDT 24
Finished Aug 17 06:36:48 PM PDT 24
Peak memory 207908 kb
Host smart-b885b25c-43cb-4f55-9f53-999588631646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344190776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.344190776
Directory /workspace/37.spi_device_stress_all/latest


Test location /workspace/coverage/default/37.spi_device_tpm_all.3110071282
Short name T5
Test name
Test status
Simulation time 8289222661 ps
CPU time 41.19 seconds
Started Aug 17 06:36:36 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 217336 kb
Host smart-f406365c-4fb9-4f2b-989e-e1a081c88bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110071282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3110071282
Directory /workspace/37.spi_device_tpm_all/latest


Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3220821750
Short name T355
Test name
Test status
Simulation time 5541425351 ps
CPU time 16.78 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 217276 kb
Host smart-caf7a430-1103-4c22-8237-bff0ce762076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220821750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3220821750
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/37.spi_device_tpm_rw.1728154902
Short name T389
Test name
Test status
Simulation time 232674773 ps
CPU time 5.52 seconds
Started Aug 17 06:36:39 PM PDT 24
Finished Aug 17 06:36:45 PM PDT 24
Peak memory 217132 kb
Host smart-60cf04d9-ae12-4a3d-8ca9-3e61ca6c1e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728154902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1728154902
Directory /workspace/37.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.704712059
Short name T399
Test name
Test status
Simulation time 56949536 ps
CPU time 0.71 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 206848 kb
Host smart-bde15f64-04c2-49e7-80ae-929812eb2415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704712059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.704712059
Directory /workspace/37.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/37.spi_device_upload.3335785228
Short name T834
Test name
Test status
Simulation time 1429692969 ps
CPU time 3.09 seconds
Started Aug 17 06:36:48 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 225312 kb
Host smart-3fdb1281-4be1-4588-92c2-0914faa1af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335785228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3335785228
Directory /workspace/37.spi_device_upload/latest


Test location /workspace/coverage/default/38.spi_device_alert_test.2323316194
Short name T547
Test name
Test status
Simulation time 110161840 ps
CPU time 0.71 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 205672 kb
Host smart-bad38f72-fb95-46a2-914d-ca953e87e4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323316194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2323316194
Directory /workspace/38.spi_device_alert_test/latest


Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2854715378
Short name T193
Test name
Test status
Simulation time 408380592 ps
CPU time 4.11 seconds
Started Aug 17 06:36:41 PM PDT 24
Finished Aug 17 06:36:45 PM PDT 24
Peak memory 225356 kb
Host smart-451fa369-278a-4088-aae9-939207dc5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854715378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2854715378
Directory /workspace/38.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/38.spi_device_csb_read.3795664798
Short name T526
Test name
Test status
Simulation time 49413171 ps
CPU time 0.84 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:36:41 PM PDT 24
Peak memory 207348 kb
Host smart-685473bf-ef12-4f44-bb86-0f2343fab3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795664798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3795664798
Directory /workspace/38.spi_device_csb_read/latest


Test location /workspace/coverage/default/38.spi_device_flash_all.1472690206
Short name T873
Test name
Test status
Simulation time 73519645520 ps
CPU time 78.24 seconds
Started Aug 17 06:36:39 PM PDT 24
Finished Aug 17 06:37:57 PM PDT 24
Peak memory 236048 kb
Host smart-d32978b8-d2b8-4b24-888c-9903f8db953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472690206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1472690206
Directory /workspace/38.spi_device_flash_all/latest


Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4051143973
Short name T170
Test name
Test status
Simulation time 48095766544 ps
CPU time 102.02 seconds
Started Aug 17 06:36:45 PM PDT 24
Finished Aug 17 06:38:27 PM PDT 24
Peak memory 241084 kb
Host smart-5d87d632-6f93-412e-915a-9f040a453d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051143973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4051143973
Directory /workspace/38.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2329621208
Short name T972
Test name
Test status
Simulation time 105106950439 ps
CPU time 244.81 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:40:56 PM PDT 24
Peak memory 257612 kb
Host smart-6a6bd9ec-44af-4803-b1c3-f036489d3ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329621208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2329621208
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/38.spi_device_flash_mode.2051596172
Short name T637
Test name
Test status
Simulation time 178598202 ps
CPU time 4.11 seconds
Started Aug 17 06:36:41 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 225288 kb
Host smart-65962188-d715-4ce3-8b46-ff19beed0fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051596172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2051596172
Directory /workspace/38.spi_device_flash_mode/latest


Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2638171660
Short name T44
Test name
Test status
Simulation time 14299358247 ps
CPU time 92.55 seconds
Started Aug 17 06:36:39 PM PDT 24
Finished Aug 17 06:38:12 PM PDT 24
Peak memory 254716 kb
Host smart-cb849ec8-11f5-42d9-838f-96458fec13bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638171660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2638171660
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/38.spi_device_intercept.2040927345
Short name T690
Test name
Test status
Simulation time 407053715 ps
CPU time 3.63 seconds
Started Aug 17 06:36:43 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 233612 kb
Host smart-e5029f87-090b-4442-b828-4f461a1de957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040927345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2040927345
Directory /workspace/38.spi_device_intercept/latest


Test location /workspace/coverage/default/38.spi_device_mailbox.1909851208
Short name T961
Test name
Test status
Simulation time 12558500227 ps
CPU time 46.1 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:37:32 PM PDT 24
Peak memory 240760 kb
Host smart-d5b2c614-8108-419f-9b2b-909b496840af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909851208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1909851208
Directory /workspace/38.spi_device_mailbox/latest


Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4257425094
Short name T277
Test name
Test status
Simulation time 305975563 ps
CPU time 2.88 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:36:43 PM PDT 24
Peak memory 233616 kb
Host smart-cff423e5-56a5-44f5-9b94-a2eb08b6fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257425094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4257425094
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1600326212
Short name T768
Test name
Test status
Simulation time 7344056973 ps
CPU time 14.16 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 233700 kb
Host smart-5f1fffa1-a0a6-4052-9e5b-67686b4f75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600326212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1600326212
Directory /workspace/38.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3500921841
Short name T867
Test name
Test status
Simulation time 597260988 ps
CPU time 5.46 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 224204 kb
Host smart-a9fc6aa2-35bc-4324-873a-bf66a52b215d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3500921841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3500921841
Directory /workspace/38.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/38.spi_device_stress_all.245258351
Short name T242
Test name
Test status
Simulation time 6253396064 ps
CPU time 85.69 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:38:16 PM PDT 24
Peak memory 264124 kb
Host smart-7452d6f5-2ebb-44ef-8963-bdc6fa9d8c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245258351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.245258351
Directory /workspace/38.spi_device_stress_all/latest


Test location /workspace/coverage/default/38.spi_device_tpm_all.3341139436
Short name T469
Test name
Test status
Simulation time 11798489239 ps
CPU time 22.15 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 217320 kb
Host smart-e9762aff-d2b1-4574-8868-f249556a2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341139436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3341139436
Directory /workspace/38.spi_device_tpm_all/latest


Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.579388244
Short name T406
Test name
Test status
Simulation time 34505205864 ps
CPU time 16.41 seconds
Started Aug 17 06:36:37 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 217368 kb
Host smart-f1d6506b-3629-436c-b41a-4c64f5d139ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579388244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.579388244
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/38.spi_device_tpm_rw.3079616185
Short name T138
Test name
Test status
Simulation time 56735420 ps
CPU time 0.85 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 206836 kb
Host smart-83a9f887-e0db-4bce-ac2d-d2dd336fc4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079616185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3079616185
Directory /workspace/38.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.229395411
Short name T906
Test name
Test status
Simulation time 58447194 ps
CPU time 0.76 seconds
Started Aug 17 06:36:45 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 206860 kb
Host smart-0c324154-669b-475c-bbc6-eee0a4296d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229395411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.229395411
Directory /workspace/38.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/38.spi_device_upload.1430132983
Short name T667
Test name
Test status
Simulation time 93818613 ps
CPU time 2.61 seconds
Started Aug 17 06:36:34 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 233528 kb
Host smart-72ea1d77-e323-45af-8c05-cbeb83e6d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430132983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1430132983
Directory /workspace/38.spi_device_upload/latest


Test location /workspace/coverage/default/39.spi_device_alert_test.3419309903
Short name T165
Test name
Test status
Simulation time 58873389 ps
CPU time 0.72 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 206244 kb
Host smart-79edf271-7992-46c5-9573-987a3664934a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419309903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3419309903
Directory /workspace/39.spi_device_alert_test/latest


Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4184755596
Short name T590
Test name
Test status
Simulation time 155952992 ps
CPU time 3.24 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 233508 kb
Host smart-1191ce9f-080e-4bf8-a19e-b0c89c944251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184755596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4184755596
Directory /workspace/39.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/39.spi_device_csb_read.1110907383
Short name T507
Test name
Test status
Simulation time 63267102 ps
CPU time 0.78 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 207400 kb
Host smart-8d435141-433e-499d-84c5-a235b6c9aa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110907383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1110907383
Directory /workspace/39.spi_device_csb_read/latest


Test location /workspace/coverage/default/39.spi_device_flash_all.3586984508
Short name T641
Test name
Test status
Simulation time 18449866044 ps
CPU time 82.39 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 238868 kb
Host smart-a476e54b-99a5-4130-b2d8-5873c98ad413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586984508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3586984508
Directory /workspace/39.spi_device_flash_all/latest


Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3203540276
Short name T164
Test name
Test status
Simulation time 2774201376 ps
CPU time 67.41 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 254016 kb
Host smart-dfac12e2-deb6-44d8-b6b2-06bd71650de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203540276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3203540276
Directory /workspace/39.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1466676118
Short name T701
Test name
Test status
Simulation time 18343622050 ps
CPU time 23.17 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 218788 kb
Host smart-2bc29edc-556c-4c55-9fb3-d824d985bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466676118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1466676118
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1748455058
Short name T945
Test name
Test status
Simulation time 4364710062 ps
CPU time 83.41 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 264504 kb
Host smart-bb99bbd7-fdc9-41ab-8e59-69d61552ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748455058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1748455058
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/39.spi_device_intercept.2416634708
Short name T196
Test name
Test status
Simulation time 5913696618 ps
CPU time 12.35 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 233700 kb
Host smart-d643ab3f-9e4e-47c6-93a3-fda4f21d7152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416634708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2416634708
Directory /workspace/39.spi_device_intercept/latest


Test location /workspace/coverage/default/39.spi_device_mailbox.243681903
Short name T497
Test name
Test status
Simulation time 9183002881 ps
CPU time 20.54 seconds
Started Aug 17 06:36:47 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 233756 kb
Host smart-64dd22b6-94ed-4855-9392-d9df5a1a0bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243681903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.243681903
Directory /workspace/39.spi_device_mailbox/latest


Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3589555855
Short name T290
Test name
Test status
Simulation time 6356345859 ps
CPU time 19.69 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:13 PM PDT 24
Peak memory 233688 kb
Host smart-9c3e82b6-f56f-4597-88dc-d64e9235d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589555855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3589555855
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2338718248
Short name T975
Test name
Test status
Simulation time 6101512003 ps
CPU time 7.67 seconds
Started Aug 17 06:36:44 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 233716 kb
Host smart-b721ba33-05df-4a03-bf58-e77aadc8d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338718248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2338718248
Directory /workspace/39.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1466001758
Short name T45
Test name
Test status
Simulation time 837031054 ps
CPU time 7.08 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 221612 kb
Host smart-423e61f0-b53f-4303-bfea-ee745a0763b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1466001758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1466001758
Directory /workspace/39.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/39.spi_device_stress_all.4048269072
Short name T969
Test name
Test status
Simulation time 77733484 ps
CPU time 1.14 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 207852 kb
Host smart-3672e1da-e632-48e6-8182-2b89ecd8b740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048269072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4048269072
Directory /workspace/39.spi_device_stress_all/latest


Test location /workspace/coverage/default/39.spi_device_tpm_all.2590940536
Short name T671
Test name
Test status
Simulation time 30525324478 ps
CPU time 38.4 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 217240 kb
Host smart-2254c386-9af6-4a23-a81a-cf7b2d423c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590940536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2590940536
Directory /workspace/39.spi_device_tpm_all/latest


Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.832144010
Short name T648
Test name
Test status
Simulation time 1287362521 ps
CPU time 7.69 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 217228 kb
Host smart-a44c4574-b41e-4ca8-b7d5-0355fa173339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832144010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.832144010
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/39.spi_device_tpm_rw.2792171473
Short name T788
Test name
Test status
Simulation time 733537778 ps
CPU time 2.64 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 217228 kb
Host smart-9f8287ce-18f5-4e14-99e4-8bbfff72f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792171473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2792171473
Directory /workspace/39.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3041686410
Short name T472
Test name
Test status
Simulation time 24292355 ps
CPU time 0.78 seconds
Started Aug 17 06:36:38 PM PDT 24
Finished Aug 17 06:36:39 PM PDT 24
Peak memory 206840 kb
Host smart-c83f791b-2dc9-47a7-86a3-3677b02ad7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041686410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3041686410
Directory /workspace/39.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/39.spi_device_upload.1045029960
Short name T966
Test name
Test status
Simulation time 1966393320 ps
CPU time 8.34 seconds
Started Aug 17 06:36:44 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 225376 kb
Host smart-272d8177-6260-4238-b4f3-b3afbccdf59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045029960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1045029960
Directory /workspace/39.spi_device_upload/latest


Test location /workspace/coverage/default/4.spi_device_alert_test.850597084
Short name T477
Test name
Test status
Simulation time 11337192 ps
CPU time 0.72 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 205672 kb
Host smart-d74a1642-87c2-4a3b-bb24-2d58a564e2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850597084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.850597084
Directory /workspace/4.spi_device_alert_test/latest


Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3262499158
Short name T292
Test name
Test status
Simulation time 2440855347 ps
CPU time 23.75 seconds
Started Aug 17 06:35:26 PM PDT 24
Finished Aug 17 06:35:50 PM PDT 24
Peak memory 225472 kb
Host smart-5c8d2c9b-a3bc-4b09-914c-952aad3c87f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262499158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3262499158
Directory /workspace/4.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/4.spi_device_csb_read.717679946
Short name T679
Test name
Test status
Simulation time 92972494 ps
CPU time 0.75 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 206712 kb
Host smart-87ae1628-833f-4351-a7d2-a2c1811f34b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717679946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.717679946
Directory /workspace/4.spi_device_csb_read/latest


Test location /workspace/coverage/default/4.spi_device_flash_all.3312778588
Short name T234
Test name
Test status
Simulation time 9735157782 ps
CPU time 41.1 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:42 PM PDT 24
Peak memory 250060 kb
Host smart-795c255a-c561-43c1-a359-9ce5c74a63e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312778588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3312778588
Directory /workspace/4.spi_device_flash_all/latest


Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2042472932
Short name T600
Test name
Test status
Simulation time 21803502548 ps
CPU time 95.69 seconds
Started Aug 17 06:35:11 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 241772 kb
Host smart-dd17ab96-7cc7-4d96-9a74-d5a45ad4c7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042472932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2042472932
Directory /workspace/4.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/4.spi_device_flash_mode.769083373
Short name T785
Test name
Test status
Simulation time 997361642 ps
CPU time 4.64 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 233568 kb
Host smart-c7e62577-c1ba-4bf4-b1f0-afbf14f48121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769083373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.769083373
Directory /workspace/4.spi_device_flash_mode/latest


Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1259469510
Short name T135
Test name
Test status
Simulation time 2579169060 ps
CPU time 48.6 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:51 PM PDT 24
Peak memory 250036 kb
Host smart-56bab6a5-5176-42e5-a66d-9fc257b57679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259469510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1259469510
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/4.spi_device_intercept.220522839
Short name T531
Test name
Test status
Simulation time 1083849699 ps
CPU time 3.82 seconds
Started Aug 17 06:35:20 PM PDT 24
Finished Aug 17 06:35:24 PM PDT 24
Peak memory 233624 kb
Host smart-5ddcc1ca-de8b-4f65-96af-ad0eb4ae0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220522839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.220522839
Directory /workspace/4.spi_device_intercept/latest


Test location /workspace/coverage/default/4.spi_device_mailbox.2079380060
Short name T908
Test name
Test status
Simulation time 24718193613 ps
CPU time 74.97 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 233604 kb
Host smart-c59c7a52-a758-4b4b-bbb8-afa91d371758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079380060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2079380060
Directory /workspace/4.spi_device_mailbox/latest


Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2719870200
Short name T653
Test name
Test status
Simulation time 87943576 ps
CPU time 2.07 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 224988 kb
Host smart-6beeaf63-a94b-47e7-8e1e-0bf2ad2a65f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719870200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2719870200
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2629494474
Short name T240
Test name
Test status
Simulation time 2230223288 ps
CPU time 9.57 seconds
Started Aug 17 06:34:56 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 233704 kb
Host smart-0a2fc38b-7535-405b-b269-1460b2ae620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629494474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2629494474
Directory /workspace/4.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/4.spi_device_sec_cm.3063712061
Short name T72
Test name
Test status
Simulation time 206463510 ps
CPU time 1.02 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 237180 kb
Host smart-ec05a50d-d343-4b71-9d6e-fb4de4df1114
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063712061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3063712061
Directory /workspace/4.spi_device_sec_cm/latest


Test location /workspace/coverage/default/4.spi_device_stress_all.168700044
Short name T480
Test name
Test status
Simulation time 84617983 ps
CPU time 0.94 seconds
Started Aug 17 06:35:00 PM PDT 24
Finished Aug 17 06:35:01 PM PDT 24
Peak memory 208380 kb
Host smart-f603bf52-6760-4678-a1aa-e1b33cb6e826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168700044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.168700044
Directory /workspace/4.spi_device_stress_all/latest


Test location /workspace/coverage/default/4.spi_device_tpm_all.4095612927
Short name T337
Test name
Test status
Simulation time 3839639544 ps
CPU time 20.1 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:29 PM PDT 24
Peak memory 217640 kb
Host smart-68ebaee3-7843-475b-996e-61b36de8366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095612927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4095612927
Directory /workspace/4.spi_device_tpm_all/latest


Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3066033647
Short name T871
Test name
Test status
Simulation time 11648676239 ps
CPU time 9.46 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 217180 kb
Host smart-7a0e2b3f-c7fb-414a-8c4d-65de4ba1916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066033647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3066033647
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/4.spi_device_tpm_rw.2318599332
Short name T952
Test name
Test status
Simulation time 433698042 ps
CPU time 2.38 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 217220 kb
Host smart-b4892487-4148-4f1e-9a69-316fae4cd355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318599332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2318599332
Directory /workspace/4.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3417655417
Short name T551
Test name
Test status
Simulation time 49072100 ps
CPU time 0.76 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 206864 kb
Host smart-60879843-87b1-4e9e-ba8e-d522384ec7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417655417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3417655417
Directory /workspace/4.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/4.spi_device_upload.2504209839
Short name T42
Test name
Test status
Simulation time 1966704703 ps
CPU time 4.64 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 225336 kb
Host smart-232c1254-1c4d-4f65-a909-da3e96838c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504209839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2504209839
Directory /workspace/4.spi_device_upload/latest


Test location /workspace/coverage/default/40.spi_device_alert_test.4142920801
Short name T414
Test name
Test status
Simulation time 13186051 ps
CPU time 0.7 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:50 PM PDT 24
Peak memory 206620 kb
Host smart-658240ea-a629-4dc1-a452-128380530a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142920801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4142920801
Directory /workspace/40.spi_device_alert_test/latest


Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2740743631
Short name T40
Test name
Test status
Simulation time 4387841180 ps
CPU time 10.88 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 233684 kb
Host smart-1a8330e8-d602-4d3b-afe1-337ac04cc3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740743631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2740743631
Directory /workspace/40.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/40.spi_device_csb_read.1047559952
Short name T876
Test name
Test status
Simulation time 34873195 ps
CPU time 0.75 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 207732 kb
Host smart-17eb090b-f135-4a60-ba5d-abd7495c39c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047559952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1047559952
Directory /workspace/40.spi_device_csb_read/latest


Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2431282387
Short name T421
Test name
Test status
Simulation time 21277620031 ps
CPU time 176.13 seconds
Started Aug 17 06:36:47 PM PDT 24
Finished Aug 17 06:39:43 PM PDT 24
Peak memory 250272 kb
Host smart-7e930ff1-0b30-4010-988f-3110dd2fd4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431282387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2431282387
Directory /workspace/40.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2344708957
Short name T944
Test name
Test status
Simulation time 90210627451 ps
CPU time 197.23 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:40:11 PM PDT 24
Peak memory 250104 kb
Host smart-c92466dc-8747-4c36-9f08-c9b1995a2922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344708957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2344708957
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/40.spi_device_flash_mode.3351253107
Short name T848
Test name
Test status
Simulation time 5877778104 ps
CPU time 37.12 seconds
Started Aug 17 06:36:45 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 225516 kb
Host smart-043414d1-acff-41ea-9682-39ef8eb3d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351253107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3351253107
Directory /workspace/40.spi_device_flash_mode/latest


Test location /workspace/coverage/default/40.spi_device_intercept.2408809087
Short name T806
Test name
Test status
Simulation time 2020245226 ps
CPU time 11.9 seconds
Started Aug 17 06:36:43 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 225308 kb
Host smart-1515453b-889c-40b1-8b98-070adb655b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408809087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2408809087
Directory /workspace/40.spi_device_intercept/latest


Test location /workspace/coverage/default/40.spi_device_mailbox.3423242104
Short name T25
Test name
Test status
Simulation time 57816337085 ps
CPU time 40.74 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:31 PM PDT 24
Peak memory 233736 kb
Host smart-a53e37cd-f5c7-4eae-8781-a4f2ebc547b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423242104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3423242104
Directory /workspace/40.spi_device_mailbox/latest


Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3173511517
Short name T274
Test name
Test status
Simulation time 1725728693 ps
CPU time 7.77 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 225384 kb
Host smart-8304e909-120f-4227-bcff-dd6a86b0057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173511517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3173511517
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3003059743
Short name T8
Test name
Test status
Simulation time 4546651630 ps
CPU time 12.57 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 225372 kb
Host smart-49bcd0d2-c8d4-4070-9a2b-07e18668763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003059743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3003059743
Directory /workspace/40.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1395387710
Short name T870
Test name
Test status
Simulation time 2874060849 ps
CPU time 5.11 seconds
Started Aug 17 06:36:43 PM PDT 24
Finished Aug 17 06:36:48 PM PDT 24
Peak memory 219840 kb
Host smart-18354c6a-c812-4322-831f-e8a5f8141e74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1395387710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1395387710
Directory /workspace/40.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/40.spi_device_tpm_all.2256576406
Short name T332
Test name
Test status
Simulation time 10824288779 ps
CPU time 4.19 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 217284 kb
Host smart-c23886dd-caa0-4fc5-992f-7c1186c738cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256576406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2256576406
Directory /workspace/40.spi_device_tpm_all/latest


Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4186345882
Short name T719
Test name
Test status
Simulation time 465292844 ps
CPU time 2.76 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 217176 kb
Host smart-72c69a58-e0e0-4aa9-8b61-8ba2421edbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186345882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4186345882
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/40.spi_device_tpm_rw.4175893818
Short name T925
Test name
Test status
Simulation time 31424348 ps
CPU time 0.67 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 206328 kb
Host smart-ddb7e950-e112-41f0-b213-d92a364647ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175893818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4175893818
Directory /workspace/40.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3119495152
Short name T563
Test name
Test status
Simulation time 17416506 ps
CPU time 0.72 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 206852 kb
Host smart-5a7103f9-49d4-4a07-9d01-872ee4605ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119495152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3119495152
Directory /workspace/40.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/40.spi_device_upload.1375449870
Short name T530
Test name
Test status
Simulation time 12992398096 ps
CPU time 9.51 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 225456 kb
Host smart-09358fb8-59c0-4b8c-b48f-87afa5d6cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375449870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1375449870
Directory /workspace/40.spi_device_upload/latest


Test location /workspace/coverage/default/41.spi_device_alert_test.651784665
Short name T571
Test name
Test status
Simulation time 15664068 ps
CPU time 0.78 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 206264 kb
Host smart-23183fc5-f9cc-40a3-89e5-3e75c0bdc88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651784665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.651784665
Directory /workspace/41.spi_device_alert_test/latest


Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3388821271
Short name T38
Test name
Test status
Simulation time 146786151 ps
CPU time 3.75 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 233584 kb
Host smart-0107380d-31ad-43f2-9ca8-d9dbe8bac4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388821271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3388821271
Directory /workspace/41.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/41.spi_device_csb_read.2927450263
Short name T929
Test name
Test status
Simulation time 57751653 ps
CPU time 0.83 seconds
Started Aug 17 06:36:38 PM PDT 24
Finished Aug 17 06:36:39 PM PDT 24
Peak memory 207408 kb
Host smart-3932c624-6da5-4e98-92c8-f07403b39252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927450263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2927450263
Directory /workspace/41.spi_device_csb_read/latest


Test location /workspace/coverage/default/41.spi_device_flash_all.2078062487
Short name T569
Test name
Test status
Simulation time 2303168638 ps
CPU time 47.29 seconds
Started Aug 17 06:36:48 PM PDT 24
Finished Aug 17 06:37:36 PM PDT 24
Peak memory 250052 kb
Host smart-778cc941-1c9e-4b87-8461-b31e4a78dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078062487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2078062487
Directory /workspace/41.spi_device_flash_all/latest


Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.651733839
Short name T923
Test name
Test status
Simulation time 45312767270 ps
CPU time 42.97 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:37:34 PM PDT 24
Peak memory 218712 kb
Host smart-37d73053-c863-4a5e-bd85-9577772acecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651733839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.651733839
Directory /workspace/41.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3014106934
Short name T341
Test name
Test status
Simulation time 35995581260 ps
CPU time 56.87 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 223780 kb
Host smart-d8bc8f80-2219-4cc5-bf03-b80ed89f3e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014106934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3014106934
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/41.spi_device_flash_mode.4045097193
Short name T633
Test name
Test status
Simulation time 327376003 ps
CPU time 3.53 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 225360 kb
Host smart-4a947eeb-cadf-4e80-b0ce-f0376751d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045097193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4045097193
Directory /workspace/41.spi_device_flash_mode/latest


Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3981199862
Short name T942
Test name
Test status
Simulation time 34699076729 ps
CPU time 54.92 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 240452 kb
Host smart-2a1a473c-199d-401a-bf56-9beff377940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981199862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3981199862
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/41.spi_device_intercept.2567640860
Short name T636
Test name
Test status
Simulation time 54939723 ps
CPU time 2.01 seconds
Started Aug 17 06:36:42 PM PDT 24
Finished Aug 17 06:36:44 PM PDT 24
Peak memory 223856 kb
Host smart-87d1d8ff-b5a2-4a9d-9378-a6c616fa1e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567640860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2567640860
Directory /workspace/41.spi_device_intercept/latest


Test location /workspace/coverage/default/41.spi_device_mailbox.2241965063
Short name T207
Test name
Test status
Simulation time 2883388445 ps
CPU time 37.61 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:31 PM PDT 24
Peak memory 233952 kb
Host smart-b19a840c-a73d-4918-b42c-fe7aa3df203d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241965063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2241965063
Directory /workspace/41.spi_device_mailbox/latest


Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1384217473
Short name T478
Test name
Test status
Simulation time 2925672190 ps
CPU time 5.19 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 233692 kb
Host smart-571b9ee7-21c2-4cc7-874b-8e81ed499b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384217473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1384217473
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2706780750
Short name T499
Test name
Test status
Simulation time 862345087 ps
CPU time 7 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 233564 kb
Host smart-b594a54a-e3a7-4dcf-bb20-183874f9772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706780750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2706780750
Directory /workspace/41.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.485746711
Short name T930
Test name
Test status
Simulation time 8624327811 ps
CPU time 19.49 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:14 PM PDT 24
Peak memory 223092 kb
Host smart-046507de-5e83-4e82-a844-7b85862e827d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=485746711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.485746711
Directory /workspace/41.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/41.spi_device_tpm_all.1385348782
Short name T661
Test name
Test status
Simulation time 2425001516 ps
CPU time 18.79 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 217416 kb
Host smart-9ad96efe-8a0d-4d1b-a53b-6cdc9410e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385348782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1385348782
Directory /workspace/41.spi_device_tpm_all/latest


Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3599828413
Short name T973
Test name
Test status
Simulation time 22668737860 ps
CPU time 17.56 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 217284 kb
Host smart-836e006d-1964-439c-95c0-1c3cf6febe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599828413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3599828413
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/41.spi_device_tpm_rw.1354054599
Short name T427
Test name
Test status
Simulation time 192044634 ps
CPU time 3.58 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 217236 kb
Host smart-e15d6f2f-1762-4697-95c5-60b66c0621ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354054599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1354054599
Directory /workspace/41.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3688043974
Short name T810
Test name
Test status
Simulation time 27624265 ps
CPU time 0.84 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 206856 kb
Host smart-57f9b278-5b32-48a7-9c25-a5c1ca13cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688043974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3688043974
Directory /workspace/41.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/41.spi_device_upload.1683869791
Short name T369
Test name
Test status
Simulation time 1146465827 ps
CPU time 3.59 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 233532 kb
Host smart-4306b244-7fcf-4d79-8b12-5f6fda1a615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683869791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1683869791
Directory /workspace/41.spi_device_upload/latest


Test location /workspace/coverage/default/42.spi_device_alert_test.2282689126
Short name T362
Test name
Test status
Simulation time 11946012 ps
CPU time 0.72 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 206256 kb
Host smart-61d1003d-f053-46e3-bbd7-423d3ebe011b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282689126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2282689126
Directory /workspace/42.spi_device_alert_test/latest


Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3596762090
Short name T802
Test name
Test status
Simulation time 476464545 ps
CPU time 4.76 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 233736 kb
Host smart-28e852eb-f002-4ee1-a209-cfabd244615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596762090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3596762090
Directory /workspace/42.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/42.spi_device_csb_read.3948230922
Short name T508
Test name
Test status
Simulation time 27584310 ps
CPU time 0.73 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 206640 kb
Host smart-354971a9-7d97-4057-99e7-c8bf6158c305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948230922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3948230922
Directory /workspace/42.spi_device_csb_read/latest


Test location /workspace/coverage/default/42.spi_device_flash_all.2276033787
Short name T683
Test name
Test status
Simulation time 44350647358 ps
CPU time 33.39 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:29 PM PDT 24
Peak memory 235736 kb
Host smart-ef60638c-4e76-4f36-bf99-cb153c0f08f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276033787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2276033787
Directory /workspace/42.spi_device_flash_all/latest


Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.483779019
Short name T331
Test name
Test status
Simulation time 59547821660 ps
CPU time 28.55 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:25 PM PDT 24
Peak memory 218572 kb
Host smart-a811f8b3-6e6c-40e7-be2d-04ff60aa823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483779019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.483779019
Directory /workspace/42.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4193792905
Short name T176
Test name
Test status
Simulation time 3569646442 ps
CPU time 38.42 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 240552 kb
Host smart-a2418ebd-a775-4008-9484-48b261ac9574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193792905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4193792905
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/42.spi_device_flash_mode.285465558
Short name T816
Test name
Test status
Simulation time 3182645014 ps
CPU time 40.42 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:31 PM PDT 24
Peak memory 250024 kb
Host smart-ad2dc786-efc4-4a3b-916a-7ea40063845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285465558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.285465558
Directory /workspace/42.spi_device_flash_mode/latest


Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1437355311
Short name T527
Test name
Test status
Simulation time 40691481308 ps
CPU time 97.59 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:38:24 PM PDT 24
Peak memory 256964 kb
Host smart-cd786c58-ef39-4334-a23d-a44613c08474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437355311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1437355311
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/42.spi_device_intercept.1640003603
Short name T845
Test name
Test status
Simulation time 32729687 ps
CPU time 2.08 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 233260 kb
Host smart-7cf01167-05fe-406b-ae29-48f033559ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640003603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1640003603
Directory /workspace/42.spi_device_intercept/latest


Test location /workspace/coverage/default/42.spi_device_mailbox.4055505394
Short name T775
Test name
Test status
Simulation time 538305748 ps
CPU time 12.89 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 225068 kb
Host smart-d8de665f-c3ba-4cc8-95e5-a32092348717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055505394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4055505394
Directory /workspace/42.spi_device_mailbox/latest


Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1549226301
Short name T289
Test name
Test status
Simulation time 231794146 ps
CPU time 2.56 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 233612 kb
Host smart-452f8442-fbae-4a1c-925a-d49c47ba509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549226301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1549226301
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2333723062
Short name T602
Test name
Test status
Simulation time 1386439159 ps
CPU time 4.34 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 233560 kb
Host smart-be1b1af5-de50-4d9c-aac9-ee9d8b39f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333723062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2333723062
Directory /workspace/42.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.653810901
Short name T607
Test name
Test status
Simulation time 402542552 ps
CPU time 5.91 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 223392 kb
Host smart-b82c44fa-702b-4120-89bb-913bee87b12f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=653810901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.653810901
Directory /workspace/42.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/42.spi_device_tpm_all.2512749050
Short name T333
Test name
Test status
Simulation time 1596131852 ps
CPU time 22.27 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 217324 kb
Host smart-1ead4966-6883-482b-b271-85d9ef620aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512749050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2512749050
Directory /workspace/42.spi_device_tpm_all/latest


Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1002407875
Short name T746
Test name
Test status
Simulation time 29528814656 ps
CPU time 19.78 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 217368 kb
Host smart-4b6f1c64-5b0c-4c65-8eb0-e281d6bdb962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002407875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1002407875
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/42.spi_device_tpm_rw.1034015714
Short name T855
Test name
Test status
Simulation time 232363972 ps
CPU time 1.06 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 208764 kb
Host smart-2838082f-f013-44bf-9aa8-5de4163d1d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034015714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1034015714
Directory /workspace/42.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1780709901
Short name T431
Test name
Test status
Simulation time 18191258 ps
CPU time 0.75 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 206740 kb
Host smart-0427c2b3-3bf0-46ac-bc1f-18478391839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780709901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1780709901
Directory /workspace/42.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/42.spi_device_upload.4209374013
Short name T429
Test name
Test status
Simulation time 256933350 ps
CPU time 7.04 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 233592 kb
Host smart-42b379aa-78fa-419d-b48d-884f14206eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209374013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.4209374013
Directory /workspace/42.spi_device_upload/latest


Test location /workspace/coverage/default/43.spi_device_alert_test.1535520303
Short name T735
Test name
Test status
Simulation time 35019447 ps
CPU time 0.68 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 206256 kb
Host smart-c73d3f33-fdb1-421e-8f5d-dada3f724144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535520303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1535520303
Directory /workspace/43.spi_device_alert_test/latest


Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1950293723
Short name T190
Test name
Test status
Simulation time 305302744 ps
CPU time 2.76 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 233420 kb
Host smart-d6da10ec-0246-4d1a-9fcc-73bdcbdaf6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950293723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1950293723
Directory /workspace/43.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/43.spi_device_csb_read.3792847363
Short name T835
Test name
Test status
Simulation time 46283456 ps
CPU time 0.85 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 207164 kb
Host smart-0ee864a0-a127-4774-b54c-d3aed9411a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792847363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3792847363
Directory /workspace/43.spi_device_csb_read/latest


Test location /workspace/coverage/default/43.spi_device_flash_all.1232477674
Short name T502
Test name
Test status
Simulation time 236773422478 ps
CPU time 210.52 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:40:28 PM PDT 24
Peak memory 258244 kb
Host smart-9b597077-fe7f-4c17-849b-ba6fd4843d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232477674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1232477674
Directory /workspace/43.spi_device_flash_all/latest


Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2626609094
Short name T32
Test name
Test status
Simulation time 6352426346 ps
CPU time 32.54 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:28 PM PDT 24
Peak memory 258408 kb
Host smart-3de9c338-07cd-4b11-b3f8-d0313723f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626609094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2626609094
Directory /workspace/43.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2769781387
Short name T210
Test name
Test status
Simulation time 19620225077 ps
CPU time 233.18 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:40:49 PM PDT 24
Peak memory 253728 kb
Host smart-eff6ca35-354d-46b9-9167-40881f5c185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769781387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2769781387
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/43.spi_device_flash_mode.3430555875
Short name T319
Test name
Test status
Simulation time 1621610232 ps
CPU time 23.79 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:19 PM PDT 24
Peak memory 241820 kb
Host smart-03a4ff2e-176f-4cfd-aeb1-ad8768f5a799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430555875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3430555875
Directory /workspace/43.spi_device_flash_mode/latest


Test location /workspace/coverage/default/43.spi_device_intercept.258983668
Short name T223
Test name
Test status
Simulation time 5938266310 ps
CPU time 26.9 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:37:24 PM PDT 24
Peak memory 225448 kb
Host smart-0e0c1c01-cbc7-4e8f-a6e7-7bc0cc9f2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258983668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.258983668
Directory /workspace/43.spi_device_intercept/latest


Test location /workspace/coverage/default/43.spi_device_mailbox.1503406095
Short name T388
Test name
Test status
Simulation time 31114602 ps
CPU time 1.97 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 223780 kb
Host smart-ce6db24a-0a9c-4629-9f62-8f360748b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503406095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1503406095
Directory /workspace/43.spi_device_mailbox/latest


Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3803139604
Short name T758
Test name
Test status
Simulation time 298817459 ps
CPU time 2.62 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 233584 kb
Host smart-67f95c9b-9374-45f9-aea4-55f584d89f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803139604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3803139604
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3609147016
Short name T213
Test name
Test status
Simulation time 3962538639 ps
CPU time 11.74 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 233652 kb
Host smart-e79edcfe-0f9c-488a-807b-abf7bdee0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609147016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3609147016
Directory /workspace/43.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1241505691
Short name T403
Test name
Test status
Simulation time 1222133033 ps
CPU time 9.95 seconds
Started Aug 17 06:36:45 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 221132 kb
Host smart-65d238c6-8a3b-4c1d-80c9-fd67b50ebde0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1241505691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1241505691
Directory /workspace/43.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/43.spi_device_stress_all.1698699896
Short name T192
Test name
Test status
Simulation time 21564063053 ps
CPU time 42.48 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:36 PM PDT 24
Peak memory 225612 kb
Host smart-d472f822-bbe6-4dbc-a9c6-3f76892a1ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698699896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1698699896
Directory /workspace/43.spi_device_stress_all/latest


Test location /workspace/coverage/default/43.spi_device_tpm_all.2344072994
Short name T954
Test name
Test status
Simulation time 17761467342 ps
CPU time 21.94 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:37:13 PM PDT 24
Peak memory 217400 kb
Host smart-fbfcba40-8629-4822-b236-135489acaf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344072994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2344072994
Directory /workspace/43.spi_device_tpm_all/latest


Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2032492810
Short name T592
Test name
Test status
Simulation time 6509481196 ps
CPU time 9.3 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 217372 kb
Host smart-61305c5e-d15a-4498-a664-114f8f0e7856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032492810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2032492810
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/43.spi_device_tpm_rw.4094255312
Short name T889
Test name
Test status
Simulation time 78079357 ps
CPU time 1.01 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 208000 kb
Host smart-62b11ec7-2c8c-42d2-960e-58e19a0c65fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094255312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4094255312
Directory /workspace/43.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3000558224
Short name T756
Test name
Test status
Simulation time 111881735 ps
CPU time 1.01 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 207848 kb
Host smart-d4794e45-6b6f-4c5e-add3-274e62be1339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000558224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3000558224
Directory /workspace/43.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/43.spi_device_upload.2490039534
Short name T464
Test name
Test status
Simulation time 537730133 ps
CPU time 3.99 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 233612 kb
Host smart-aed94e2b-6901-42b8-a08f-e781136f4075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490039534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2490039534
Directory /workspace/43.spi_device_upload/latest


Test location /workspace/coverage/default/44.spi_device_alert_test.795541556
Short name T902
Test name
Test status
Simulation time 10841942 ps
CPU time 0.74 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:54 PM PDT 24
Peak memory 206444 kb
Host smart-37c2f118-ccd9-43cb-9590-ec148e2406c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795541556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.795541556
Directory /workspace/44.spi_device_alert_test/latest


Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3268274925
Short name T591
Test name
Test status
Simulation time 277936905 ps
CPU time 3.03 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 225440 kb
Host smart-a9b59b03-9496-4420-97bd-a9aacb12f255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268274925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3268274925
Directory /workspace/44.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/44.spi_device_csb_read.982023692
Short name T928
Test name
Test status
Simulation time 21523117 ps
CPU time 0.77 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 207648 kb
Host smart-7667dd9a-3f12-47d2-abc8-87b469dedbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982023692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.982023692
Directory /workspace/44.spi_device_csb_read/latest


Test location /workspace/coverage/default/44.spi_device_flash_all.3769225481
Short name T85
Test name
Test status
Simulation time 24467151443 ps
CPU time 61.36 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 250160 kb
Host smart-390adfe1-bc3b-4d23-95e1-5b8fad55b5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769225481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3769225481
Directory /workspace/44.spi_device_flash_all/latest


Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1290666924
Short name T168
Test name
Test status
Simulation time 11081849021 ps
CPU time 64.53 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 238764 kb
Host smart-7e8a8b67-1f9d-462f-a953-684f11bcf4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290666924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1290666924
Directory /workspace/44.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1019705788
Short name T611
Test name
Test status
Simulation time 8641898262 ps
CPU time 58.72 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 239436 kb
Host smart-7a012fc1-8090-43b2-84c6-fc09892ab2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019705788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1019705788
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/44.spi_device_flash_mode.3580849135
Short name T460
Test name
Test status
Simulation time 732021347 ps
CPU time 11.88 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 237980 kb
Host smart-cdcd3c97-72cc-4d11-9293-1e4df359a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580849135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3580849135
Directory /workspace/44.spi_device_flash_mode/latest


Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1193938537
Short name T979
Test name
Test status
Simulation time 52437771401 ps
CPU time 182.91 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:40:00 PM PDT 24
Peak memory 250188 kb
Host smart-2f1490ba-23e2-40b6-8194-15dbd1ca56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193938537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1193938537
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/44.spi_device_intercept.884719013
Short name T557
Test name
Test status
Simulation time 998769768 ps
CPU time 13.07 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 233856 kb
Host smart-e8956d72-dc8f-41f3-8902-bdd3dfe22a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884719013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.884719013
Directory /workspace/44.spi_device_intercept/latest


Test location /workspace/coverage/default/44.spi_device_mailbox.2164333136
Short name T939
Test name
Test status
Simulation time 28974652988 ps
CPU time 71.2 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 241680 kb
Host smart-03b33129-b8c2-414e-a19f-cd182a121b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164333136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2164333136
Directory /workspace/44.spi_device_mailbox/latest


Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4029028215
Short name T280
Test name
Test status
Simulation time 12065901344 ps
CPU time 19.45 seconds
Started Aug 17 06:36:48 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 233716 kb
Host smart-549a3c0a-a517-40b5-8c1b-d3206237b493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029028215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4029028215
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.727791300
Short name T439
Test name
Test status
Simulation time 641122770 ps
CPU time 6.51 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 225064 kb
Host smart-c1a7f8db-8fdd-4e41-81e6-ba3010f29c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727791300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.727791300
Directory /workspace/44.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1252668643
Short name T488
Test name
Test status
Simulation time 526567083 ps
CPU time 3.61 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 219756 kb
Host smart-92116611-ad20-4b01-8a67-5505d0056b6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1252668643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1252668643
Directory /workspace/44.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/44.spi_device_stress_all.1361747483
Short name T157
Test name
Test status
Simulation time 46529061797 ps
CPU time 184.67 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:39:55 PM PDT 24
Peak memory 258352 kb
Host smart-3612582c-fe26-4a78-9c9d-81cfcfb332dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361747483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1361747483
Directory /workspace/44.spi_device_stress_all/latest


Test location /workspace/coverage/default/44.spi_device_tpm_all.4085458465
Short name T27
Test name
Test status
Simulation time 4755577982 ps
CPU time 14.35 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 217436 kb
Host smart-e7c31ab2-c562-437b-a641-7f3f58108f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085458465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4085458465
Directory /workspace/44.spi_device_tpm_all/latest


Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3508566357
Short name T372
Test name
Test status
Simulation time 1428447543 ps
CPU time 4.21 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 217152 kb
Host smart-5972c881-a5fe-4816-a894-14e07adba574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508566357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3508566357
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/44.spi_device_tpm_rw.2756802175
Short name T444
Test name
Test status
Simulation time 283225313 ps
CPU time 1.34 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 217092 kb
Host smart-8e3664a0-f126-4e1d-9572-6972dbfc4640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756802175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2756802175
Directory /workspace/44.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.403784389
Short name T384
Test name
Test status
Simulation time 287193200 ps
CPU time 0.89 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:36:47 PM PDT 24
Peak memory 206876 kb
Host smart-9306d990-7700-4504-b70d-f2906b7fd302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403784389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.403784389
Directory /workspace/44.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/44.spi_device_upload.1697858114
Short name T790
Test name
Test status
Simulation time 35765271646 ps
CPU time 29.47 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 252012 kb
Host smart-3caf5388-956d-4163-b12a-a419b0ce2871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697858114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1697858114
Directory /workspace/44.spi_device_upload/latest


Test location /workspace/coverage/default/45.spi_device_alert_test.2140244653
Short name T833
Test name
Test status
Simulation time 22226357 ps
CPU time 0.73 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 205724 kb
Host smart-79272e12-a2ed-4ccc-bc99-48516b1cc3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140244653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2140244653
Directory /workspace/45.spi_device_alert_test/latest


Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1819711100
Short name T926
Test name
Test status
Simulation time 207733578 ps
CPU time 4.02 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 233620 kb
Host smart-07ce2204-b535-49a9-83fe-f308801fd1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819711100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1819711100
Directory /workspace/45.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/45.spi_device_csb_read.176704547
Short name T76
Test name
Test status
Simulation time 27088081 ps
CPU time 0.75 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 206392 kb
Host smart-2195f3e4-8612-4a16-bc61-07b1d46d7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176704547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.176704547
Directory /workspace/45.spi_device_csb_read/latest


Test location /workspace/coverage/default/45.spi_device_flash_all.4111522410
Short name T199
Test name
Test status
Simulation time 421110566139 ps
CPU time 412.68 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:43:51 PM PDT 24
Peak memory 265256 kb
Host smart-2765a4c7-0bc9-4d65-b533-e7ea3ba3b0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111522410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4111522410
Directory /workspace/45.spi_device_flash_all/latest


Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3687405393
Short name T781
Test name
Test status
Simulation time 11000130042 ps
CPU time 96.59 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:38:29 PM PDT 24
Peak memory 233856 kb
Host smart-45aaa6b4-7b9c-4ccf-9a4a-8db15af585fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687405393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3687405393
Directory /workspace/45.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4044364803
Short name T509
Test name
Test status
Simulation time 21736950 ps
CPU time 0.83 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 217624 kb
Host smart-0b720c40-1947-4a2d-a57b-67d8aedb5e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044364803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4044364803
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/45.spi_device_flash_mode.1862358711
Short name T669
Test name
Test status
Simulation time 13362960888 ps
CPU time 15.92 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 250104 kb
Host smart-3486309b-83dc-472c-8abe-62c4571f830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862358711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1862358711
Directory /workspace/45.spi_device_flash_mode/latest


Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.903628335
Short name T808
Test name
Test status
Simulation time 63301795726 ps
CPU time 110.47 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:38:44 PM PDT 24
Peak memory 251920 kb
Host smart-1c80ac5f-3fd4-447c-8243-72db1b7f33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903628335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.903628335
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/45.spi_device_intercept.3450214813
Short name T60
Test name
Test status
Simulation time 167485729 ps
CPU time 3.69 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 233636 kb
Host smart-216c17e6-1b6c-48f0-9f06-f77d2d71e43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450214813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3450214813
Directory /workspace/45.spi_device_intercept/latest


Test location /workspace/coverage/default/45.spi_device_mailbox.1390418802
Short name T433
Test name
Test status
Simulation time 1395662715 ps
CPU time 23.12 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 249948 kb
Host smart-62abb644-fa7a-4d9a-af4c-821865943068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390418802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1390418802
Directory /workspace/45.spi_device_mailbox/latest


Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2697364889
Short name T387
Test name
Test status
Simulation time 1889774059 ps
CPU time 4.83 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 225320 kb
Host smart-7a8a2ddd-dce2-429c-b87c-fa45872cda3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697364889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2697364889
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3841532093
Short name T917
Test name
Test status
Simulation time 113500874 ps
CPU time 2.26 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 224352 kb
Host smart-f822c7ae-4400-4282-928e-082b44ec5342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841532093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3841532093
Directory /workspace/45.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.732600275
Short name T2
Test name
Test status
Simulation time 79581977 ps
CPU time 3.56 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 223624 kb
Host smart-d3a616af-02ee-475d-b57a-7e964c763e30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=732600275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.732600275
Directory /workspace/45.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/45.spi_device_stress_all.2575082523
Short name T947
Test name
Test status
Simulation time 34265488150 ps
CPU time 103.58 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:38:37 PM PDT 24
Peak memory 250180 kb
Host smart-81e731e3-3879-4d44-b2a1-367465c8cbf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575082523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2575082523
Directory /workspace/45.spi_device_stress_all/latest


Test location /workspace/coverage/default/45.spi_device_tpm_all.1675037702
Short name T852
Test name
Test status
Simulation time 301498385 ps
CPU time 4.31 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 217460 kb
Host smart-a6d39319-df5b-46f2-8e1b-a48d78fd0ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675037702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1675037702
Directory /workspace/45.spi_device_tpm_all/latest


Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3013809796
Short name T914
Test name
Test status
Simulation time 971864131 ps
CPU time 6.57 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 217216 kb
Host smart-c3f73751-5d76-470e-b53f-dbb7ddd844c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013809796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3013809796
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/45.spi_device_tpm_rw.1081776728
Short name T461
Test name
Test status
Simulation time 12846249 ps
CPU time 0.67 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 206428 kb
Host smart-b8b4566b-79f8-4887-846b-9e836491e156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081776728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1081776728
Directory /workspace/45.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2701545621
Short name T760
Test name
Test status
Simulation time 338372412 ps
CPU time 0.96 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 207824 kb
Host smart-a3a2b811-3986-41a8-bc23-b474bd85973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701545621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2701545621
Directory /workspace/45.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/45.spi_device_upload.3227812409
Short name T392
Test name
Test status
Simulation time 449209999 ps
CPU time 2.41 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 233296 kb
Host smart-16725098-13e4-4887-8027-dd5bf504852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227812409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3227812409
Directory /workspace/45.spi_device_upload/latest


Test location /workspace/coverage/default/46.spi_device_alert_test.1317786998
Short name T840
Test name
Test status
Simulation time 30781712 ps
CPU time 0.69 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:52 PM PDT 24
Peak memory 206244 kb
Host smart-e88f8ac3-af00-4185-9416-9b7ffd02dc95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317786998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1317786998
Directory /workspace/46.spi_device_alert_test/latest


Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4041478718
Short name T625
Test name
Test status
Simulation time 1748914826 ps
CPU time 10.18 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 233584 kb
Host smart-3a112f03-71c3-4342-99eb-7a04c2c9f482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041478718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4041478718
Directory /workspace/46.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/46.spi_device_csb_read.381152270
Short name T465
Test name
Test status
Simulation time 19678809 ps
CPU time 0.79 seconds
Started Aug 17 06:36:40 PM PDT 24
Finished Aug 17 06:36:41 PM PDT 24
Peak memory 206496 kb
Host smart-f20f0e66-6b7f-4cc0-8964-581be8dd32bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381152270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.381152270
Directory /workspace/46.spi_device_csb_read/latest


Test location /workspace/coverage/default/46.spi_device_flash_all.2161428363
Short name T974
Test name
Test status
Simulation time 7397599862 ps
CPU time 82.93 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 273552 kb
Host smart-dc355673-6bcf-4ff6-9c63-e032a3afa48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161428363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2161428363
Directory /workspace/46.spi_device_flash_all/latest


Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2454526550
Short name T339
Test name
Test status
Simulation time 3118749718 ps
CPU time 14.57 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 250216 kb
Host smart-82eacad4-fc79-447d-93db-4af6aa44cf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454526550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2454526550
Directory /workspace/46.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.75508437
Short name T713
Test name
Test status
Simulation time 33926263205 ps
CPU time 162.88 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:39:35 PM PDT 24
Peak memory 256812 kb
Host smart-14ef00df-ead8-4f30-b7ab-9a67769a546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75508437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.75508437
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/46.spi_device_flash_mode.520628236
Short name T941
Test name
Test status
Simulation time 758384313 ps
CPU time 11.79 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 241796 kb
Host smart-38cc0d55-5185-40ab-ba40-c11c00d60ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520628236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.520628236
Directory /workspace/46.spi_device_flash_mode/latest


Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.835456571
Short name T206
Test name
Test status
Simulation time 3414730938 ps
CPU time 74.53 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:38:16 PM PDT 24
Peak memory 255796 kb
Host smart-54d49626-8397-4b60-b689-71e1d9551ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835456571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.835456571
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/46.spi_device_intercept.3755237977
Short name T402
Test name
Test status
Simulation time 424665055 ps
CPU time 5.65 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 225320 kb
Host smart-9b287559-3642-4802-9a5c-3790cb0614f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755237977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3755237977
Directory /workspace/46.spi_device_intercept/latest


Test location /workspace/coverage/default/46.spi_device_mailbox.2964494650
Short name T843
Test name
Test status
Simulation time 24772886136 ps
CPU time 47.98 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 233708 kb
Host smart-2fc492a8-0760-489f-b97f-92c7d0d3d400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964494650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2964494650
Directory /workspace/46.spi_device_mailbox/latest


Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2833755212
Short name T279
Test name
Test status
Simulation time 248429520 ps
CPU time 2.84 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 225288 kb
Host smart-7522f990-e1a9-485e-a8d8-48f06c3c1323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833755212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2833755212
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4003305058
Short name T724
Test name
Test status
Simulation time 3788873190 ps
CPU time 9.6 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 233592 kb
Host smart-c8c99950-8c0b-424c-bbfa-a52da6131dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003305058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4003305058
Directory /workspace/46.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.364326791
Short name T911
Test name
Test status
Simulation time 946553862 ps
CPU time 7.31 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 223636 kb
Host smart-9d2ca198-ddf7-459e-bc50-ea29e9e2b282
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=364326791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.364326791
Directory /workspace/46.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/46.spi_device_stress_all.607355129
Short name T301
Test name
Test status
Simulation time 45219875859 ps
CPU time 217.03 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:40:33 PM PDT 24
Peak memory 253512 kb
Host smart-311480b5-e1e2-4310-874b-61781af66f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607355129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.607355129
Directory /workspace/46.spi_device_stress_all/latest


Test location /workspace/coverage/default/46.spi_device_tpm_all.1203466087
Short name T646
Test name
Test status
Simulation time 8709262129 ps
CPU time 14.5 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 220636 kb
Host smart-ccc2de2d-c6f5-4f68-926f-6139da7931e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203466087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1203466087
Directory /workspace/46.spi_device_tpm_all/latest


Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2241229665
Short name T666
Test name
Test status
Simulation time 179172375 ps
CPU time 1.38 seconds
Started Aug 17 06:36:48 PM PDT 24
Finished Aug 17 06:36:49 PM PDT 24
Peak memory 208612 kb
Host smart-2794d752-e109-4dde-b5f3-afc9691c7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241229665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2241229665
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/46.spi_device_tpm_rw.2789664034
Short name T28
Test name
Test status
Simulation time 111063056 ps
CPU time 2.18 seconds
Started Aug 17 06:36:49 PM PDT 24
Finished Aug 17 06:36:51 PM PDT 24
Peak memory 217224 kb
Host smart-8013b465-2ad4-4541-81df-ba7dd7013c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789664034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2789664034
Directory /workspace/46.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1038414660
Short name T885
Test name
Test status
Simulation time 62588795 ps
CPU time 0.74 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 206880 kb
Host smart-4177ad18-6381-4117-b229-a758c14b00ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038414660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1038414660
Directory /workspace/46.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/46.spi_device_upload.2177538392
Short name T293
Test name
Test status
Simulation time 6525060648 ps
CPU time 10.02 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 225552 kb
Host smart-cbae1c84-8e5d-4966-b23c-fd3722b8cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177538392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2177538392
Directory /workspace/46.spi_device_upload/latest


Test location /workspace/coverage/default/47.spi_device_alert_test.235752955
Short name T83
Test name
Test status
Simulation time 37568671 ps
CPU time 0.73 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 206580 kb
Host smart-b6f07c33-ba2b-433f-bce1-88353883988f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235752955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.235752955
Directory /workspace/47.spi_device_alert_test/latest


Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3896649279
Short name T698
Test name
Test status
Simulation time 690800736 ps
CPU time 5.52 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 233380 kb
Host smart-6ee12eb9-f434-403e-b95a-30f1db2abf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896649279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3896649279
Directory /workspace/47.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/47.spi_device_csb_read.1100108871
Short name T818
Test name
Test status
Simulation time 29999227 ps
CPU time 0.81 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:50 PM PDT 24
Peak memory 207356 kb
Host smart-f282485d-cd92-4f42-9ae1-1b21cea1c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100108871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1100108871
Directory /workspace/47.spi_device_csb_read/latest


Test location /workspace/coverage/default/47.spi_device_flash_all.241658830
Short name T804
Test name
Test status
Simulation time 65486551939 ps
CPU time 243.77 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:40:55 PM PDT 24
Peak memory 254712 kb
Host smart-6127d9ae-fabb-40d4-9775-4c41b83d8877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241658830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.241658830
Directory /workspace/47.spi_device_flash_all/latest


Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2314267790
Short name T549
Test name
Test status
Simulation time 31787046994 ps
CPU time 164.25 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:39:40 PM PDT 24
Peak memory 255396 kb
Host smart-11092337-d6ad-4c4e-acdb-edb7dcc1350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314267790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2314267790
Directory /workspace/47.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2611783918
Short name T299
Test name
Test status
Simulation time 18785089961 ps
CPU time 85.03 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:38:19 PM PDT 24
Peak memory 252504 kb
Host smart-f1dc290f-2a15-490a-94d4-0ea59c27d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611783918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2611783918
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/47.spi_device_flash_mode.1829827936
Short name T136
Test name
Test status
Simulation time 1419666407 ps
CPU time 21.88 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 235932 kb
Host smart-ff32cf38-20c3-47c2-9f6f-aed21da8b17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829827936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1829827936
Directory /workspace/47.spi_device_flash_mode/latest


Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.4134203737
Short name T357
Test name
Test status
Simulation time 11376508 ps
CPU time 0.82 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 216524 kb
Host smart-3a53cb15-6af7-41e6-89be-27dd7a68821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134203737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.4134203737
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/47.spi_device_intercept.3961324238
Short name T708
Test name
Test status
Simulation time 442499689 ps
CPU time 3.47 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 233504 kb
Host smart-9704fbca-abfa-4200-a298-bf1aa47786d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961324238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3961324238
Directory /workspace/47.spi_device_intercept/latest


Test location /workspace/coverage/default/47.spi_device_mailbox.246717363
Short name T742
Test name
Test status
Simulation time 2227098701 ps
CPU time 15.08 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 233676 kb
Host smart-b257b948-7853-487a-a827-6096819d8278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246717363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.246717363
Directory /workspace/47.spi_device_mailbox/latest


Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1058379350
Short name T275
Test name
Test status
Simulation time 37342680503 ps
CPU time 36.93 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 233640 kb
Host smart-8b9f6cf1-9316-4c2b-a176-902fc0b1a9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058379350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1058379350
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3493987421
Short name T368
Test name
Test status
Simulation time 6968832915 ps
CPU time 6.77 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 225420 kb
Host smart-abbbf80a-9023-476f-83a4-e50de31fe767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493987421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3493987421
Directory /workspace/47.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1417238613
Short name T356
Test name
Test status
Simulation time 1057227726 ps
CPU time 4.2 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 224056 kb
Host smart-087daa4c-84d4-4ec3-a0d9-2c91a6d75ca6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1417238613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1417238613
Directory /workspace/47.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/47.spi_device_tpm_all.1215038708
Short name T395
Test name
Test status
Simulation time 42461527 ps
CPU time 0.72 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 206440 kb
Host smart-0fcecabf-f4d4-494f-804e-812613537dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215038708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1215038708
Directory /workspace/47.spi_device_tpm_all/latest


Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2609130420
Short name T570
Test name
Test status
Simulation time 1267506962 ps
CPU time 5.7 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 217124 kb
Host smart-57fe0f04-de66-4ef8-a2fe-708d8040d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609130420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2609130420
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/47.spi_device_tpm_rw.1492502480
Short name T616
Test name
Test status
Simulation time 129367962 ps
CPU time 1.57 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:53 PM PDT 24
Peak memory 217168 kb
Host smart-c98f625e-dd62-4e2e-9a43-fa89ec66db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492502480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1492502480
Directory /workspace/47.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1662041617
Short name T377
Test name
Test status
Simulation time 181024436 ps
CPU time 0.85 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 206892 kb
Host smart-13e94161-b06b-4052-bb11-1b71d3be8f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662041617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1662041617
Directory /workspace/47.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/47.spi_device_upload.4139867463
Short name T587
Test name
Test status
Simulation time 2759473562 ps
CPU time 8.44 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 241820 kb
Host smart-f3e35ef5-42c1-48b8-8be9-1891c9d19b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139867463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4139867463
Directory /workspace/47.spi_device_upload/latest


Test location /workspace/coverage/default/48.spi_device_alert_test.4283825753
Short name T4
Test name
Test status
Simulation time 71755592 ps
CPU time 0.74 seconds
Started Aug 17 06:36:47 PM PDT 24
Finished Aug 17 06:36:48 PM PDT 24
Peak memory 205696 kb
Host smart-e97f4253-2444-4943-9443-ce10f59a4db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283825753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4283825753
Directory /workspace/48.spi_device_alert_test/latest


Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2380251687
Short name T651
Test name
Test status
Simulation time 749924298 ps
CPU time 7.04 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 225324 kb
Host smart-b40a63d1-ea3c-4536-a671-ab4736657d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380251687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2380251687
Directory /workspace/48.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/48.spi_device_csb_read.255867264
Short name T169
Test name
Test status
Simulation time 45014585 ps
CPU time 0.76 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 206384 kb
Host smart-dc69e1c9-f9df-46cf-be15-451fa4cb6992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255867264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.255867264
Directory /workspace/48.spi_device_csb_read/latest


Test location /workspace/coverage/default/48.spi_device_flash_all.2646888083
Short name T53
Test name
Test status
Simulation time 3844929034 ps
CPU time 30.18 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:37:21 PM PDT 24
Peak memory 250108 kb
Host smart-efa53269-9b6c-4d39-ab0c-691e59bbd58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646888083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2646888083
Directory /workspace/48.spi_device_flash_all/latest


Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.985960032
Short name T218
Test name
Test status
Simulation time 9985170439 ps
CPU time 48.74 seconds
Started Aug 17 06:36:52 PM PDT 24
Finished Aug 17 06:37:41 PM PDT 24
Peak memory 234888 kb
Host smart-0a0bebce-3bdc-4f7a-872f-074ed84040a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985960032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.985960032
Directory /workspace/48.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3662422079
Short name T139
Test name
Test status
Simulation time 3195925310 ps
CPU time 48.05 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 250236 kb
Host smart-940f38c4-e061-4c90-a533-532cf0c4fe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662422079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3662422079
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/48.spi_device_flash_mode.1050513882
Short name T318
Test name
Test status
Simulation time 1909503035 ps
CPU time 18.25 seconds
Started Aug 17 06:36:46 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 233572 kb
Host smart-13ef218c-7f4e-44f3-9234-c7dacb0313ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050513882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1050513882
Directory /workspace/48.spi_device_flash_mode/latest


Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3932385752
Short name T177
Test name
Test status
Simulation time 26444473604 ps
CPU time 108.9 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:38:52 PM PDT 24
Peak memory 255524 kb
Host smart-c9963734-0a8a-4bd1-bfdb-b8d8d272fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932385752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3932385752
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/48.spi_device_intercept.2832036104
Short name T828
Test name
Test status
Simulation time 1087435475 ps
CPU time 2.74 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 225360 kb
Host smart-24fb73b7-8943-4bfe-94d0-fedb8c648d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832036104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2832036104
Directory /workspace/48.spi_device_intercept/latest


Test location /workspace/coverage/default/48.spi_device_mailbox.131663449
Short name T540
Test name
Test status
Simulation time 4498930684 ps
CPU time 15.07 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 233712 kb
Host smart-b9e2c118-6b4e-49a7-b085-c897724f22f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131663449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.131663449
Directory /workspace/48.spi_device_mailbox/latest


Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2371766664
Short name T728
Test name
Test status
Simulation time 5936334438 ps
CPU time 18.5 seconds
Started Aug 17 06:36:47 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 233688 kb
Host smart-7f28a9ad-3a38-4bb5-9029-ec295eee3bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371766664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2371766664
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2652903228
Short name T752
Test name
Test status
Simulation time 536841592 ps
CPU time 10.02 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 250936 kb
Host smart-9dd6d971-bc86-4413-9403-988008c5a2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652903228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2652903228
Directory /workspace/48.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.31359906
Short name T694
Test name
Test status
Simulation time 3802694940 ps
CPU time 9.16 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 220204 kb
Host smart-837d5108-2a2c-4cef-8ec4-39348df8721e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31359906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direc
t.31359906
Directory /workspace/48.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/48.spi_device_stress_all.2824472390
Short name T55
Test name
Test status
Simulation time 222748420683 ps
CPU time 402.97 seconds
Started Aug 17 06:37:05 PM PDT 24
Finished Aug 17 06:43:48 PM PDT 24
Peak memory 267244 kb
Host smart-b5d23243-b406-43ab-b2d3-33545a2d59fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824472390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2824472390
Directory /workspace/48.spi_device_stress_all/latest


Test location /workspace/coverage/default/48.spi_device_tpm_all.2675437130
Short name T933
Test name
Test status
Simulation time 408047061 ps
CPU time 6.44 seconds
Started Aug 17 06:36:51 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 217396 kb
Host smart-bccf63ec-174c-4667-8688-0879f58c61d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675437130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2675437130
Directory /workspace/48.spi_device_tpm_all/latest


Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1932274180
Short name T62
Test name
Test status
Simulation time 9290707737 ps
CPU time 8.65 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 217208 kb
Host smart-29d2a5c8-7862-43a8-87db-072e3e1c809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932274180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1932274180
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/48.spi_device_tpm_rw.1447923988
Short name T993
Test name
Test status
Simulation time 400145323 ps
CPU time 2.18 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 217204 kb
Host smart-3e172067-a97f-4365-8dd4-fcaa4748f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447923988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1447923988
Directory /workspace/48.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3444398211
Short name T93
Test name
Test status
Simulation time 54492463 ps
CPU time 0.73 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 206808 kb
Host smart-aa8ff01c-907a-4f75-a370-239990daa5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444398211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3444398211
Directory /workspace/48.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/48.spi_device_upload.1863092145
Short name T291
Test name
Test status
Simulation time 2263651410 ps
CPU time 4.29 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 225544 kb
Host smart-e756bfe6-6fa5-4ce0-8307-804466920695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863092145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1863092145
Directory /workspace/48.spi_device_upload/latest


Test location /workspace/coverage/default/49.spi_device_alert_test.417581440
Short name T789
Test name
Test status
Simulation time 13710280 ps
CPU time 0.87 seconds
Started Aug 17 06:37:17 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 205732 kb
Host smart-32857642-5e23-41be-b419-934e1122e85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417581440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.417581440
Directory /workspace/49.spi_device_alert_test/latest


Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3724338475
Short name T895
Test name
Test status
Simulation time 322602963 ps
CPU time 4.01 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 233512 kb
Host smart-56c711ff-4832-46d3-bb7e-3899b79bab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724338475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3724338475
Directory /workspace/49.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/49.spi_device_csb_read.2447524247
Short name T891
Test name
Test status
Simulation time 15174162 ps
CPU time 0.76 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 207440 kb
Host smart-08476ed4-44f3-4484-ad6e-926d2cec1a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447524247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2447524247
Directory /workspace/49.spi_device_csb_read/latest


Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.700179343
Short name T16
Test name
Test status
Simulation time 7526385771 ps
CPU time 76.45 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 250308 kb
Host smart-42aad1e7-422b-404d-abf9-87d99469ea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700179343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.700179343
Directory /workspace/49.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2720004637
Short name T837
Test name
Test status
Simulation time 29713784495 ps
CPU time 292.35 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:41:47 PM PDT 24
Peak memory 258416 kb
Host smart-0456239f-91e6-43b2-8fa4-c3720b8ee600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720004637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2720004637
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/49.spi_device_flash_mode.687188775
Short name T763
Test name
Test status
Simulation time 483004504 ps
CPU time 4.82 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 239608 kb
Host smart-211a0b0b-3af0-4fe9-9fcf-e07f9f4a7913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687188775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.687188775
Directory /workspace/49.spi_device_flash_mode/latest


Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1639501087
Short name T498
Test name
Test status
Simulation time 15439798891 ps
CPU time 139.53 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:39:10 PM PDT 24
Peak memory 254512 kb
Host smart-44912683-aa01-46aa-a906-25adf9fda846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639501087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1639501087
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/49.spi_device_intercept.1425754698
Short name T924
Test name
Test status
Simulation time 2440057081 ps
CPU time 16.82 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:13 PM PDT 24
Peak memory 233684 kb
Host smart-86e49cb7-d2ed-4f18-936a-da70a432191d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425754698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1425754698
Directory /workspace/49.spi_device_intercept/latest


Test location /workspace/coverage/default/49.spi_device_mailbox.539013201
Short name T216
Test name
Test status
Simulation time 2559561602 ps
CPU time 12.3 seconds
Started Aug 17 06:36:53 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 233348 kb
Host smart-13ea0cfb-4eaf-4040-ad1b-93d3f27113af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539013201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.539013201
Directory /workspace/49.spi_device_mailbox/latest


Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4192026419
Short name T769
Test name
Test status
Simulation time 418338616 ps
CPU time 2.95 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 233600 kb
Host smart-4b543539-ea3f-4778-aa2d-cf2e4fc62dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192026419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4192026419
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3414271862
Short name T441
Test name
Test status
Simulation time 552512941 ps
CPU time 7.56 seconds
Started Aug 17 06:36:50 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 233576 kb
Host smart-2acf7ee0-baac-4b28-b1cc-8be67477d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414271862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3414271862
Directory /workspace/49.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1513448566
Short name T545
Test name
Test status
Simulation time 1681435942 ps
CPU time 15.59 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:19 PM PDT 24
Peak memory 222984 kb
Host smart-21444009-b75b-4df2-ab55-0d1baabc91ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1513448566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1513448566
Directory /workspace/49.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/49.spi_device_stress_all.3664516964
Short name T205
Test name
Test status
Simulation time 69454608278 ps
CPU time 448.5 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:44:27 PM PDT 24
Peak memory 261568 kb
Host smart-d03195b4-57ec-49f6-88a5-34383119d066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664516964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3664516964
Directory /workspace/49.spi_device_stress_all/latest


Test location /workspace/coverage/default/49.spi_device_tpm_all.2245509002
Short name T998
Test name
Test status
Simulation time 2836103724 ps
CPU time 10.83 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 217560 kb
Host smart-4b275ef4-d87a-4d00-935c-69d0f90d2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245509002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2245509002
Directory /workspace/49.spi_device_tpm_all/latest


Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3476530065
Short name T959
Test name
Test status
Simulation time 1414614457 ps
CPU time 8.16 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 217136 kb
Host smart-9651a1f6-2441-4bbe-b348-988ea1160df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476530065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3476530065
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/49.spi_device_tpm_rw.1387009282
Short name T359
Test name
Test status
Simulation time 60064239 ps
CPU time 1.2 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 209000 kb
Host smart-6e35d800-94f7-4e4a-ac4e-7806e23cca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387009282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1387009282
Directory /workspace/49.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3707704370
Short name T501
Test name
Test status
Simulation time 32510464 ps
CPU time 0.75 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 206888 kb
Host smart-b41394c9-09fe-4e7e-b046-6a50ee886b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707704370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3707704370
Directory /workspace/49.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/49.spi_device_upload.1376917438
Short name T214
Test name
Test status
Simulation time 183861710 ps
CPU time 3.7 seconds
Started Aug 17 06:36:55 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 233636 kb
Host smart-6373d9fa-e2fb-4945-bb0c-1b5ce611bc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376917438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1376917438
Directory /workspace/49.spi_device_upload/latest


Test location /workspace/coverage/default/5.spi_device_alert_test.314586544
Short name T903
Test name
Test status
Simulation time 36467209 ps
CPU time 0.71 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 206604 kb
Host smart-5951747e-2105-447d-916e-69e87cc086ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314586544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.314586544
Directory /workspace/5.spi_device_alert_test/latest


Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1388598906
Short name T879
Test name
Test status
Simulation time 1473823556 ps
CPU time 20.72 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:33 PM PDT 24
Peak memory 225376 kb
Host smart-8461009f-e74c-4eca-a29a-4bf926c90dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388598906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1388598906
Directory /workspace/5.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/5.spi_device_csb_read.1101440065
Short name T740
Test name
Test status
Simulation time 21482918 ps
CPU time 0.8 seconds
Started Aug 17 06:35:11 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 207456 kb
Host smart-4b6415f4-6abf-4e09-97d2-0c80763e4561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101440065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1101440065
Directory /workspace/5.spi_device_csb_read/latest


Test location /workspace/coverage/default/5.spi_device_flash_all.3228208251
Short name T856
Test name
Test status
Simulation time 7603171371 ps
CPU time 63.94 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:36:16 PM PDT 24
Peak memory 258316 kb
Host smart-f7ac05dc-a2d5-4bb3-b19c-f2dc1edd621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228208251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3228208251
Directory /workspace/5.spi_device_flash_all/latest


Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3048366826
Short name T225
Test name
Test status
Simulation time 34016208768 ps
CPU time 176.4 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 250236 kb
Host smart-2283f9d7-e3e2-43a9-a744-b57c2d58f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048366826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3048366826
Directory /workspace/5.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3937967385
Short name T396
Test name
Test status
Simulation time 18902344044 ps
CPU time 132.17 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 242032 kb
Host smart-c85d1d5b-0f96-4ed3-a47c-5c0822d66763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937967385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3937967385
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/5.spi_device_flash_mode.2765560266
Short name T668
Test name
Test status
Simulation time 753045508 ps
CPU time 6.11 seconds
Started Aug 17 06:35:04 PM PDT 24
Finished Aug 17 06:35:10 PM PDT 24
Peak memory 239036 kb
Host smart-9015539b-3e21-4af3-b3f9-2713bd95bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765560266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2765560266
Directory /workspace/5.spi_device_flash_mode/latest


Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3054190182
Short name T795
Test name
Test status
Simulation time 10266917623 ps
CPU time 43.5 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:53 PM PDT 24
Peak memory 225536 kb
Host smart-67097bde-6a60-43ad-b784-ede2d364ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054190182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3054190182
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/5.spi_device_intercept.3899310949
Short name T762
Test name
Test status
Simulation time 29113595 ps
CPU time 2.09 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 225016 kb
Host smart-d8a9c73c-0790-42e4-a5c2-3dfba23c8b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899310949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3899310949
Directory /workspace/5.spi_device_intercept/latest


Test location /workspace/coverage/default/5.spi_device_mailbox.3813276810
Short name T978
Test name
Test status
Simulation time 29910974 ps
CPU time 2.22 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 225240 kb
Host smart-bab11dc9-b251-459d-88d4-afdd8b393f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813276810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3813276810
Directory /workspace/5.spi_device_mailbox/latest


Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1256956255
Short name T936
Test name
Test status
Simulation time 3478815415 ps
CPU time 7.42 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 241892 kb
Host smart-d2dd2872-be2b-471f-b737-bc098079b208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256956255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1256956255
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4223564605
Short name T211
Test name
Test status
Simulation time 2391196375 ps
CPU time 8.55 seconds
Started Aug 17 06:35:28 PM PDT 24
Finished Aug 17 06:35:37 PM PDT 24
Peak memory 236552 kb
Host smart-be898c4e-5b64-427b-aa22-0f813ab3722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223564605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4223564605
Directory /workspace/5.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.467647725
Short name T417
Test name
Test status
Simulation time 311298768 ps
CPU time 4.19 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 223952 kb
Host smart-245e948a-f245-40c2-ba6e-58dccb63c463
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=467647725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.467647725
Directory /workspace/5.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/5.spi_device_stress_all.3522411858
Short name T463
Test name
Test status
Simulation time 3294783436 ps
CPU time 22.8 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:26 PM PDT 24
Peak memory 220780 kb
Host smart-017a0918-c70e-40c3-96d7-790a567026c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522411858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3522411858
Directory /workspace/5.spi_device_stress_all/latest


Test location /workspace/coverage/default/5.spi_device_tpm_all.2591340105
Short name T566
Test name
Test status
Simulation time 19775657002 ps
CPU time 28.7 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:39 PM PDT 24
Peak memory 217336 kb
Host smart-294cf461-015f-4bac-a5d9-61e4780f5786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591340105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2591340105
Directory /workspace/5.spi_device_tpm_all/latest


Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1207161288
Short name T927
Test name
Test status
Simulation time 9250573665 ps
CPU time 2.44 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 209008 kb
Host smart-cd62fc3d-6776-4445-82df-1bdffc2da08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207161288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1207161288
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/5.spi_device_tpm_rw.2349914349
Short name T446
Test name
Test status
Simulation time 772118332 ps
CPU time 2.07 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 217064 kb
Host smart-51c48f1d-11c4-40c1-9d6d-c2c1aeb75abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349914349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2349914349
Directory /workspace/5.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2408966979
Short name T686
Test name
Test status
Simulation time 14225536 ps
CPU time 0.71 seconds
Started Aug 17 06:35:21 PM PDT 24
Finished Aug 17 06:35:21 PM PDT 24
Peak memory 206444 kb
Host smart-539128af-ed3c-4adb-ac8f-a921bb7f03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408966979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2408966979
Directory /workspace/5.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/5.spi_device_upload.4077089261
Short name T252
Test name
Test status
Simulation time 1481762671 ps
CPU time 12.14 seconds
Started Aug 17 06:35:22 PM PDT 24
Finished Aug 17 06:35:34 PM PDT 24
Peak memory 233564 kb
Host smart-4742902f-bb3a-4823-b853-a18b76901ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077089261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4077089261
Directory /workspace/5.spi_device_upload/latest


Test location /workspace/coverage/default/6.spi_device_alert_test.3726153037
Short name T9
Test name
Test status
Simulation time 14864516 ps
CPU time 0.73 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 206588 kb
Host smart-cdae4a5f-d34f-4892-8f8f-35a83f1e569f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726153037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
726153037
Directory /workspace/6.spi_device_alert_test/latest


Test location /workspace/coverage/default/6.spi_device_cfg_cmd.76307844
Short name T10
Test name
Test status
Simulation time 361971297 ps
CPU time 5.68 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:18 PM PDT 24
Peak memory 225448 kb
Host smart-adaa743d-171c-45d2-ae33-ed705b8b3a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76307844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.76307844
Directory /workspace/6.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/6.spi_device_csb_read.1072195835
Short name T658
Test name
Test status
Simulation time 64642491 ps
CPU time 0.79 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 207420 kb
Host smart-20b54333-4cad-4826-a3b0-14828773ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072195835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1072195835
Directory /workspace/6.spi_device_csb_read/latest


Test location /workspace/coverage/default/6.spi_device_flash_all.2479513232
Short name T194
Test name
Test status
Simulation time 17624481256 ps
CPU time 66.36 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:36:37 PM PDT 24
Peak memory 251112 kb
Host smart-81bd19ea-4c25-4dc2-b558-d8b68a2856ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479513232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2479513232
Directory /workspace/6.spi_device_flash_all/latest


Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3470298683
Short name T56
Test name
Test status
Simulation time 3748422065 ps
CPU time 39.44 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:45 PM PDT 24
Peak memory 250188 kb
Host smart-77cb544c-5adb-41c6-93f8-0674948cb48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470298683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3470298683
Directory /workspace/6.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1879287336
Short name T440
Test name
Test status
Simulation time 16884526808 ps
CPU time 25.45 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:34 PM PDT 24
Peak memory 225568 kb
Host smart-3b957207-659b-4cb4-b549-b6269d98af23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879287336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1879287336
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/6.spi_device_flash_mode.3877441482
Short name T322
Test name
Test status
Simulation time 3075571392 ps
CPU time 11.16 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 250264 kb
Host smart-105a3ff5-c20a-4819-898b-5838d037725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877441482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3877441482
Directory /workspace/6.spi_device_flash_mode/latest


Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1577314812
Short name T882
Test name
Test status
Simulation time 12355272775 ps
CPU time 84.97 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:36:35 PM PDT 24
Peak memory 257080 kb
Host smart-5480d8e4-7230-440d-9b7e-abd101e42b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577314812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1577314812
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/6.spi_device_intercept.3786350672
Short name T247
Test name
Test status
Simulation time 1372945890 ps
CPU time 9.91 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:16 PM PDT 24
Peak memory 233576 kb
Host smart-0c458ae2-bf9b-424a-a02a-139327a26564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786350672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3786350672
Directory /workspace/6.spi_device_intercept/latest


Test location /workspace/coverage/default/6.spi_device_mailbox.3819202407
Short name T259
Test name
Test status
Simulation time 6358336091 ps
CPU time 14.72 seconds
Started Aug 17 06:35:33 PM PDT 24
Finished Aug 17 06:35:48 PM PDT 24
Peak memory 241732 kb
Host smart-a63cbf97-c6c7-481b-8306-74580a80ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819202407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3819202407
Directory /workspace/6.spi_device_mailbox/latest


Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2299231864
Short name T827
Test name
Test status
Simulation time 697780442 ps
CPU time 2.9 seconds
Started Aug 17 06:35:13 PM PDT 24
Finished Aug 17 06:35:16 PM PDT 24
Peak memory 225348 kb
Host smart-4ccbd1f9-f661-4730-ace3-9204d0172da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299231864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2299231864
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1745045251
Short name T63
Test name
Test status
Simulation time 386762217 ps
CPU time 2.61 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 225432 kb
Host smart-5e45dcc2-f52b-4e21-aa3b-6588942dd623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745045251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1745045251
Directory /workspace/6.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.878036514
Short name T149
Test name
Test status
Simulation time 671582375 ps
CPU time 5.99 seconds
Started Aug 17 06:35:22 PM PDT 24
Finished Aug 17 06:35:28 PM PDT 24
Peak memory 224148 kb
Host smart-d8d001e0-de12-4904-8558-dc3bb8ee6b12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878036514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.878036514
Directory /workspace/6.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/6.spi_device_stress_all.3455911016
Short name T58
Test name
Test status
Simulation time 228397516307 ps
CPU time 507.06 seconds
Started Aug 17 06:35:25 PM PDT 24
Finished Aug 17 06:43:52 PM PDT 24
Peak memory 274716 kb
Host smart-8ce8de48-ec14-4042-bfef-81a7821774be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455911016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3455911016
Directory /workspace/6.spi_device_stress_all/latest


Test location /workspace/coverage/default/6.spi_device_tpm_all.2295985565
Short name T594
Test name
Test status
Simulation time 5228503005 ps
CPU time 16.42 seconds
Started Aug 17 06:35:19 PM PDT 24
Finished Aug 17 06:35:36 PM PDT 24
Peak memory 217312 kb
Host smart-242809d0-e722-4e24-b624-7e26bb9f3ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295985565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2295985565
Directory /workspace/6.spi_device_tpm_all/latest


Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.617489672
Short name T741
Test name
Test status
Simulation time 2657420099 ps
CPU time 7.45 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:11 PM PDT 24
Peak memory 217296 kb
Host smart-667608b5-8294-4d57-9c2c-ae15cb0a80d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617489672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.617489672
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/6.spi_device_tpm_rw.4103319320
Short name T564
Test name
Test status
Simulation time 13748109 ps
CPU time 0.82 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 207740 kb
Host smart-6c84fb13-8ec7-474b-bb1f-549b157e4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103319320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.4103319320
Directory /workspace/6.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.625543221
Short name T696
Test name
Test status
Simulation time 12242562 ps
CPU time 0.67 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 206408 kb
Host smart-be689c0c-0d45-42d7-b69d-b35cfad5be7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625543221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.625543221
Directory /workspace/6.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/6.spi_device_upload.2221875470
Short name T980
Test name
Test status
Simulation time 48478215769 ps
CPU time 40.79 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:53 PM PDT 24
Peak memory 233752 kb
Host smart-64654ff4-a0eb-4e51-822b-6d989f76733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221875470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2221875470
Directory /workspace/6.spi_device_upload/latest


Test location /workspace/coverage/default/7.spi_device_alert_test.2088542364
Short name T892
Test name
Test status
Simulation time 22128811 ps
CPU time 0.73 seconds
Started Aug 17 06:35:16 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 205676 kb
Host smart-e29f0532-35ef-4a6f-83be-da1f2e74de19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088542364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
088542364
Directory /workspace/7.spi_device_alert_test/latest


Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1236365989
Short name T36
Test name
Test status
Simulation time 93967195 ps
CPU time 3.48 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 233540 kb
Host smart-d528b9ed-9375-410d-8992-ee4e6872c609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236365989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1236365989
Directory /workspace/7.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/7.spi_device_csb_read.2680841013
Short name T365
Test name
Test status
Simulation time 31912859 ps
CPU time 0.81 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 207452 kb
Host smart-31c33936-e84f-42e6-9d90-8364b4fa19a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680841013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2680841013
Directory /workspace/7.spi_device_csb_read/latest


Test location /workspace/coverage/default/7.spi_device_flash_all.2207423674
Short name T426
Test name
Test status
Simulation time 130546261547 ps
CPU time 96.26 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:36:46 PM PDT 24
Peak memory 236196 kb
Host smart-43fa2c84-a346-4c53-8631-a88163bdecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207423674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2207423674
Directory /workspace/7.spi_device_flash_all/latest


Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.529146112
Short name T691
Test name
Test status
Simulation time 54097510003 ps
CPU time 124.75 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 252032 kb
Host smart-45a42243-e5c1-4cce-9616-439c0aa60a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529146112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.529146112
Directory /workspace/7.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.80853319
Short name T412
Test name
Test status
Simulation time 2169517985 ps
CPU time 10.9 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 236332 kb
Host smart-9caf2c50-5238-45e6-89be-408aa1da5944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80853319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.80853319
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/7.spi_device_flash_mode.896068380
Short name T486
Test name
Test status
Simulation time 171478198 ps
CPU time 2.62 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 225372 kb
Host smart-5215271a-9bd6-4c3a-bc1f-66d57a7a883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896068380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.896068380
Directory /workspace/7.spi_device_flash_mode/latest


Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3903953760
Short name T272
Test name
Test status
Simulation time 271498012828 ps
CPU time 448.21 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:42:35 PM PDT 24
Peak memory 257160 kb
Host smart-e8dbd4c1-6991-4d29-bad9-640f6cf26115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903953760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3903953760
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/7.spi_device_intercept.2316811386
Short name T826
Test name
Test status
Simulation time 1174966512 ps
CPU time 14.41 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:20 PM PDT 24
Peak memory 225344 kb
Host smart-bd0550bb-ab9b-41dc-ada1-7dd3ff49e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316811386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2316811386
Directory /workspace/7.spi_device_intercept/latest


Test location /workspace/coverage/default/7.spi_device_mailbox.1199976638
Short name T774
Test name
Test status
Simulation time 2474780740 ps
CPU time 13.71 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:35:44 PM PDT 24
Peak memory 225536 kb
Host smart-7d5b3ad1-38db-409e-a668-396862b688ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199976638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1199976638
Directory /workspace/7.spi_device_mailbox/latest


Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3384540288
Short name T380
Test name
Test status
Simulation time 973982400 ps
CPU time 4.86 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:07 PM PDT 24
Peak memory 233628 kb
Host smart-7c45fc7b-442c-48e5-87a9-36e13623f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384540288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3384540288
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3449383693
Short name T659
Test name
Test status
Simulation time 34214208 ps
CPU time 2.73 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:15 PM PDT 24
Peak memory 232800 kb
Host smart-7493844e-7b05-4c9b-8174-fd0daedc09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449383693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3449383693
Directory /workspace/7.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3127240706
Short name T75
Test name
Test status
Simulation time 237448210 ps
CPU time 5.23 seconds
Started Aug 17 06:35:22 PM PDT 24
Finished Aug 17 06:35:27 PM PDT 24
Peak memory 224080 kb
Host smart-f694a90f-dccf-411e-aa69-3c9d30a4614d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3127240706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3127240706
Directory /workspace/7.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/7.spi_device_tpm_all.2924081763
Short name T718
Test name
Test status
Simulation time 12553905 ps
CPU time 0.73 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:06 PM PDT 24
Peak memory 206488 kb
Host smart-d582049c-72b3-481a-8968-f0fe76dc75fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924081763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2924081763
Directory /workspace/7.spi_device_tpm_all/latest


Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3084461112
Short name T772
Test name
Test status
Simulation time 1661403793 ps
CPU time 9.39 seconds
Started Aug 17 06:35:14 PM PDT 24
Finished Aug 17 06:35:24 PM PDT 24
Peak memory 217160 kb
Host smart-8fa07b13-ac5c-4dda-b003-30c764ea3eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084461112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3084461112
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/7.spi_device_tpm_rw.1250180275
Short name T937
Test name
Test status
Simulation time 670191034 ps
CPU time 2.04 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 217180 kb
Host smart-1a275a79-f241-4d7f-ace2-a315a9428fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250180275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1250180275
Directory /workspace/7.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3633448936
Short name T133
Test name
Test status
Simulation time 680403518 ps
CPU time 1 seconds
Started Aug 17 06:35:26 PM PDT 24
Finished Aug 17 06:35:27 PM PDT 24
Peak memory 207824 kb
Host smart-324e6b46-40af-498d-8ca8-00c02d9f02bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633448936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3633448936
Directory /workspace/7.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/7.spi_device_upload.1567818136
Short name T605
Test name
Test status
Simulation time 4517204378 ps
CPU time 8.99 seconds
Started Aug 17 06:35:11 PM PDT 24
Finished Aug 17 06:35:20 PM PDT 24
Peak memory 233708 kb
Host smart-8b05e197-57c8-44fb-8a3b-ce631814f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567818136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1567818136
Directory /workspace/7.spi_device_upload/latest


Test location /workspace/coverage/default/8.spi_device_alert_test.3935955322
Short name T1002
Test name
Test status
Simulation time 13457287 ps
CPU time 0.69 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 205916 kb
Host smart-27f2d698-b039-4f4c-b958-099d6bbd26b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935955322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
935955322
Directory /workspace/8.spi_device_alert_test/latest


Test location /workspace/coverage/default/8.spi_device_cfg_cmd.416778665
Short name T814
Test name
Test status
Simulation time 139744113 ps
CPU time 3.01 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 225304 kb
Host smart-1b91aedf-f982-4a27-94ab-53595e0fe6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416778665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.416778665
Directory /workspace/8.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/8.spi_device_csb_read.2115572868
Short name T451
Test name
Test status
Simulation time 56133312 ps
CPU time 0.77 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 206440 kb
Host smart-f841de80-cb00-4d3c-b28c-9a6937b39516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115572868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2115572868
Directory /workspace/8.spi_device_csb_read/latest


Test location /workspace/coverage/default/8.spi_device_flash_all.3213878328
Short name T304
Test name
Test status
Simulation time 10170404670 ps
CPU time 102.32 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 274184 kb
Host smart-c7c5608b-f2a7-4421-a366-3071a5b9c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213878328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3213878328
Directory /workspace/8.spi_device_flash_all/latest


Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1739669113
Short name T554
Test name
Test status
Simulation time 4837879347 ps
CPU time 83.98 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:36:55 PM PDT 24
Peak memory 258328 kb
Host smart-68a7d577-6c9f-4271-907e-29c836646fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739669113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1739669113
Directory /workspace/8.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1434002139
Short name T273
Test name
Test status
Simulation time 38337888376 ps
CPU time 131.61 seconds
Started Aug 17 06:35:15 PM PDT 24
Finished Aug 17 06:37:27 PM PDT 24
Peak memory 274756 kb
Host smart-b9879a52-5440-497c-ab1d-9e4e2e2b140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434002139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1434002139
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/8.spi_device_flash_mode.1441777711
Short name T860
Test name
Test status
Simulation time 4964448840 ps
CPU time 78.72 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:36:25 PM PDT 24
Peak memory 233616 kb
Host smart-49d78e1a-9ec2-4ea7-a3db-1faabf2de0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441777711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1441777711
Directory /workspace/8.spi_device_flash_mode/latest


Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2923424117
Short name T379
Test name
Test status
Simulation time 56820629 ps
CPU time 0.93 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 216904 kb
Host smart-aa3b37a1-6a66-4e32-bc0e-b0c4465e627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923424117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2923424117
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/8.spi_device_intercept.1341634226
Short name T489
Test name
Test status
Simulation time 95234755 ps
CPU time 3.19 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 233632 kb
Host smart-4bcc5ac5-a73b-4c9e-8944-d12ff457ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341634226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1341634226
Directory /workspace/8.spi_device_intercept/latest


Test location /workspace/coverage/default/8.spi_device_mailbox.467394157
Short name T175
Test name
Test status
Simulation time 2405609768 ps
CPU time 28.26 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:38 PM PDT 24
Peak memory 241732 kb
Host smart-e09b8f55-0992-470d-8d64-b1544789e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467394157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.467394157
Directory /workspace/8.spi_device_mailbox/latest


Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.202358279
Short name T52
Test name
Test status
Simulation time 4948932393 ps
CPU time 16.52 seconds
Started Aug 17 06:34:57 PM PDT 24
Finished Aug 17 06:35:14 PM PDT 24
Peak memory 241768 kb
Host smart-501cde71-5c17-4b72-9d5f-317a6b97d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202358279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
202358279
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4124096437
Short name T617
Test name
Test status
Simulation time 420000921 ps
CPU time 3.28 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 225328 kb
Host smart-f0b0f412-335d-4c76-bfc0-1f99e1cb9387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124096437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4124096437
Directory /workspace/8.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3269936285
Short name T681
Test name
Test status
Simulation time 1183338647 ps
CPU time 4.21 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:16 PM PDT 24
Peak memory 223616 kb
Host smart-1388d5c5-a346-46eb-acf3-1902e55235b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3269936285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3269936285
Directory /workspace/8.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/8.spi_device_stress_all.882409765
Short name T449
Test name
Test status
Simulation time 73278657542 ps
CPU time 351.77 seconds
Started Aug 17 06:35:14 PM PDT 24
Finished Aug 17 06:41:05 PM PDT 24
Peak memory 274336 kb
Host smart-d947e0f5-db47-4fab-8be5-e70b917378d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882409765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.882409765
Directory /workspace/8.spi_device_stress_all/latest


Test location /workspace/coverage/default/8.spi_device_tpm_all.2176907770
Short name T336
Test name
Test status
Simulation time 88469871 ps
CPU time 2.06 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 217268 kb
Host smart-7afeee6b-c8ec-4341-bb3a-e3a6649d6957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176907770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2176907770
Directory /workspace/8.spi_device_tpm_all/latest


Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3031329105
Short name T803
Test name
Test status
Simulation time 13375310071 ps
CPU time 18.2 seconds
Started Aug 17 06:34:59 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 217304 kb
Host smart-a808a8db-3800-4dbe-a79c-2ec76e932d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031329105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3031329105
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/8.spi_device_tpm_rw.3907829098
Short name T918
Test name
Test status
Simulation time 105284570 ps
CPU time 4.34 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:05 PM PDT 24
Peak memory 217144 kb
Host smart-b8a1da0b-b583-4902-a622-e46c2d119048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907829098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3907829098
Directory /workspace/8.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1507456256
Short name T533
Test name
Test status
Simulation time 44414953 ps
CPU time 0.74 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:13 PM PDT 24
Peak memory 206812 kb
Host smart-eb62311f-2ddf-41e9-a7ff-1b166fc5e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507456256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1507456256
Directory /workspace/8.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/8.spi_device_upload.3638103835
Short name T1004
Test name
Test status
Simulation time 8913227333 ps
CPU time 32.37 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:34 PM PDT 24
Peak memory 233616 kb
Host smart-96bd60d1-60af-4a03-baa1-b8ccf37fae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638103835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3638103835
Directory /workspace/8.spi_device_upload/latest


Test location /workspace/coverage/default/9.spi_device_alert_test.644468682
Short name T765
Test name
Test status
Simulation time 16008607 ps
CPU time 0.73 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:02 PM PDT 24
Peak memory 205692 kb
Host smart-8b89bf9d-58dd-4e4f-9f99-c4fa624eaff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644468682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.644468682
Directory /workspace/9.spi_device_alert_test/latest


Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1779544067
Short name T996
Test name
Test status
Simulation time 1116630419 ps
CPU time 2.89 seconds
Started Aug 17 06:35:29 PM PDT 24
Finished Aug 17 06:35:32 PM PDT 24
Peak memory 225384 kb
Host smart-408b22e0-f56c-426f-8bdb-8ef304c5d6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779544067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1779544067
Directory /workspace/9.spi_device_cfg_cmd/latest


Test location /workspace/coverage/default/9.spi_device_csb_read.460879118
Short name T482
Test name
Test status
Simulation time 15742753 ps
CPU time 0.76 seconds
Started Aug 17 06:35:02 PM PDT 24
Finished Aug 17 06:35:03 PM PDT 24
Peak memory 207360 kb
Host smart-b8eac4f9-6270-4ce5-ad3c-9af92690afbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460879118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.460879118
Directory /workspace/9.spi_device_csb_read/latest


Test location /workspace/coverage/default/9.spi_device_flash_all.19066681
Short name T749
Test name
Test status
Simulation time 10896628111 ps
CPU time 44.54 seconds
Started Aug 17 06:35:07 PM PDT 24
Finished Aug 17 06:35:57 PM PDT 24
Peak memory 238180 kb
Host smart-94525b30-b7bc-4b60-9c94-27da54c78410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19066681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.19066681
Directory /workspace/9.spi_device_flash_all/latest


Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1890008922
Short name T300
Test name
Test status
Simulation time 4222805564 ps
CPU time 87.74 seconds
Started Aug 17 06:35:31 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 262912 kb
Host smart-6f37271d-4df4-42f3-ae38-58df0e6eb622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890008922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1890008922
Directory /workspace/9.spi_device_flash_and_tpm/latest


Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2924017822
Short name T542
Test name
Test status
Simulation time 23901406690 ps
CPU time 64.21 seconds
Started Aug 17 06:35:05 PM PDT 24
Finished Aug 17 06:36:09 PM PDT 24
Peak memory 254948 kb
Host smart-f37215df-2208-44d0-821c-9647e3d25b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924017822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2924017822
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest


Test location /workspace/coverage/default/9.spi_device_flash_mode.578641877
Short name T59
Test name
Test status
Simulation time 2035021197 ps
CPU time 11.56 seconds
Started Aug 17 06:35:10 PM PDT 24
Finished Aug 17 06:35:22 PM PDT 24
Peak memory 233576 kb
Host smart-5870843a-ad1c-4f43-8c99-3deb40d5d8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578641877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.578641877
Directory /workspace/9.spi_device_flash_mode/latest


Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2113998125
Short name T626
Test name
Test status
Simulation time 179247497927 ps
CPU time 315.49 seconds
Started Aug 17 06:35:34 PM PDT 24
Finished Aug 17 06:40:50 PM PDT 24
Peak memory 261336 kb
Host smart-66adc6b6-d798-4ae0-921a-94033edd8e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113998125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2113998125
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest


Test location /workspace/coverage/default/9.spi_device_intercept.2991806796
Short name T678
Test name
Test status
Simulation time 31518714 ps
CPU time 2.29 seconds
Started Aug 17 06:35:42 PM PDT 24
Finished Aug 17 06:35:44 PM PDT 24
Peak memory 233288 kb
Host smart-6f2557ab-3bd3-4c96-8386-a7a2487bddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991806796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2991806796
Directory /workspace/9.spi_device_intercept/latest


Test location /workspace/coverage/default/9.spi_device_mailbox.1837249239
Short name T726
Test name
Test status
Simulation time 3243441170 ps
CPU time 12.71 seconds
Started Aug 17 06:35:12 PM PDT 24
Finished Aug 17 06:35:25 PM PDT 24
Peak memory 233744 kb
Host smart-6a894d85-ad01-4047-b462-30bfb86a1a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837249239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1837249239
Directory /workspace/9.spi_device_mailbox/latest


Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3754377622
Short name T552
Test name
Test status
Simulation time 2471603366 ps
CPU time 11.59 seconds
Started Aug 17 06:35:30 PM PDT 24
Finished Aug 17 06:35:42 PM PDT 24
Peak memory 240208 kb
Host smart-c00c43e0-7dad-477e-9608-df6d6d8e5853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754377622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3754377622
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest


Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.297590399
Short name T759
Test name
Test status
Simulation time 120030038 ps
CPU time 2.45 seconds
Started Aug 17 06:35:01 PM PDT 24
Finished Aug 17 06:35:04 PM PDT 24
Peak memory 233532 kb
Host smart-f95b465c-3ee6-4b9d-ad25-292f8f20cb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297590399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.297590399
Directory /workspace/9.spi_device_pass_cmd_filtering/latest


Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1964242632
Short name T404
Test name
Test status
Simulation time 546064763 ps
CPU time 3.78 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:12 PM PDT 24
Peak memory 220904 kb
Host smart-79108f98-142f-468b-a503-6307b2ed6f66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964242632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1964242632
Directory /workspace/9.spi_device_read_buffer_direct/latest


Test location /workspace/coverage/default/9.spi_device_stress_all.3373475209
Short name T19
Test name
Test status
Simulation time 95209620836 ps
CPU time 287.71 seconds
Started Aug 17 06:35:21 PM PDT 24
Finished Aug 17 06:40:09 PM PDT 24
Peak memory 274448 kb
Host smart-0a1ef0e0-7690-4ae0-b26f-c1e533733d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373475209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3373475209
Directory /workspace/9.spi_device_stress_all/latest


Test location /workspace/coverage/default/9.spi_device_tpm_all.4141297712
Short name T575
Test name
Test status
Simulation time 7392814528 ps
CPU time 34.81 seconds
Started Aug 17 06:35:09 PM PDT 24
Finished Aug 17 06:35:44 PM PDT 24
Peak memory 217344 kb
Host smart-a33a8b98-549f-4fdb-a543-ede72a11806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141297712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4141297712
Directory /workspace/9.spi_device_tpm_all/latest


Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.66439992
Short name T574
Test name
Test status
Simulation time 6263401394 ps
CPU time 14.06 seconds
Started Aug 17 06:35:03 PM PDT 24
Finished Aug 17 06:35:17 PM PDT 24
Peak memory 217268 kb
Host smart-c8090c22-95ea-4420-9008-0daa8262ea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66439992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.66439992
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest


Test location /workspace/coverage/default/9.spi_device_tpm_rw.2402873038
Short name T796
Test name
Test status
Simulation time 197857176 ps
CPU time 1.06 seconds
Started Aug 17 06:35:06 PM PDT 24
Finished Aug 17 06:35:08 PM PDT 24
Peak memory 208712 kb
Host smart-04f387b1-9dd1-49a3-b5c2-df4bac28f561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402873038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2402873038
Directory /workspace/9.spi_device_tpm_rw/latest


Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1845735895
Short name T832
Test name
Test status
Simulation time 26742738 ps
CPU time 0.71 seconds
Started Aug 17 06:35:08 PM PDT 24
Finished Aug 17 06:35:09 PM PDT 24
Peak memory 206844 kb
Host smart-c16cbb3c-4435-4acb-928c-35097b4bd0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845735895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1845735895
Directory /workspace/9.spi_device_tpm_sts_read/latest


Test location /workspace/coverage/default/9.spi_device_upload.2554103042
Short name T360
Test name
Test status
Simulation time 2654915010 ps
CPU time 8.94 seconds
Started Aug 17 06:35:26 PM PDT 24
Finished Aug 17 06:35:35 PM PDT 24
Peak memory 225540 kb
Host smart-d6f9dfc3-007f-436f-8aac-ec7631ffa68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554103042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2554103042
Directory /workspace/9.spi_device_upload/latest
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