Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2827480	1			T2	1		T3	21		T4	1
all_values[1]	2827480	1			T2	1		T3	21		T4	1
all_values[2]	2827480	1			T2	1		T3	21		T4	1
all_values[3]	2827480	1			T2	1		T3	21		T4	1
all_values[4]	2827480	1			T2	1		T3	21		T4	1
all_values[5]	2827480	1			T2	1		T3	21		T4	1
all_values[6]	2827480	1			T2	1		T3	21		T4	1
all_values[7]	2827480	1			T2	1		T3	21		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22551975

1

T2

8

T3

168

T4

8

auto[1]

67865

1

T16

6831

T17

50

T18

89

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22593824

1

T2

8

T3

168

T4

8

auto[1]

26016

1

T31

177

T16

264

T59

295

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2807739	1			T2	1		T3	21		T4	1
all_values[0]	auto[0]	auto[1]	12518	1			T31	86		T16	1		T59	166
all_values[0]	auto[1]	auto[0]	6911	1			T16	1023		T17	4		T18	5
all_values[0]	auto[1]	auto[1]	312	1			T16	115		T17	2		T18	2
all_values[1]	auto[0]	auto[0]	2804378	1			T2	1		T3	21		T4	1
all_values[1]	auto[0]	auto[1]	7861	1			T31	71		T59	129		T18	66
all_values[1]	auto[1]	auto[0]	14928	1			T16	1031		T17	4		T18	8
all_values[1]	auto[1]	auto[1]	313	1			T16	107		T17	4		T18	7
all_values[2]	auto[0]	auto[0]	2815950	1			T2	1		T3	21		T4	1
all_values[2]	auto[0]	auto[1]	2941	1			T31	20		T17	3		T18	8
all_values[2]	auto[1]	auto[0]	8377	1			T16	1099		T17	2		T18	5
all_values[2]	auto[1]	auto[1]	212	1			T16	39		T17	5		T18	4
all_values[3]	auto[0]	auto[0]	2817552	1			T2	1		T3	21		T4	1
all_values[3]	auto[0]	auto[1]	194	1			T18	2		T20	2		T33	3
all_values[3]	auto[1]	auto[0]	9532	1			T16	1136		T17	5		T18	9
all_values[3]	auto[1]	auto[1]	202	1			T16	2		T17	2		T18	4
all_values[4]	auto[0]	auto[0]	2820773	1			T2	1		T3	21		T4	1
all_values[4]	auto[0]	auto[1]	213	1			T18	3		T20	8		T33	5
all_values[4]	auto[1]	auto[0]	6316	1			T16	2		T17	4		T18	3
all_values[4]	auto[1]	auto[1]	178	1			T17	2		T18	4		T20	2
all_values[5]	auto[0]	auto[0]	2817796	1			T2	1		T3	21		T4	1
all_values[5]	auto[0]	auto[1]	165	1			T17	3		T18	2		T20	3
all_values[5]	auto[1]	auto[0]	9355	1			T16	1139		T17	3		T18	7
all_values[5]	auto[1]	auto[1]	164	1			T17	1		T18	5		T20	1
all_values[6]	auto[0]	auto[0]	2826320	1			T2	1		T3	21		T4	1
all_values[6]	auto[0]	auto[1]	204	1			T17	2		T18	4		T20	3
all_values[6]	auto[1]	auto[0]	787	1			T17	4		T18	8		T20	3
all_values[6]	auto[1]	auto[1]	169	1			T17	2		T18	4		T34	3
all_values[7]	auto[0]	auto[0]	2817183	1			T2	1		T3	21		T4	1
all_values[7]	auto[0]	auto[1]	188	1			T20	7		T33	1		T34	2
all_values[7]	auto[1]	auto[0]	9927	1			T16	1138		T17	6		T18	9
all_values[7]	auto[1]	auto[1]	182	1			T18	5		T20	4		T33	5