Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34559	1			T4	4		T5	12		T10	5
auto[SpiFlashAddrCfg]	7754	1			T3	8		T4	2		T9	2
auto[SpiFlashAddr3b]	9306	1			T4	4		T9	2		T10	8
auto[SpiFlashAddr4b]	7424	1			T4	4		T10	3		T11	16

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33081

1

T3

8

T5

12

T9

4

auto[1]

25962

1

T4

14

T10

12

T11

128

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31466

1

T3

8

T4

8

T5

12

auto[1]

27577

1

T4

6

T9

2

T10

13

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39380	1			T4	8		T5	12		T10	6
values[1]	1087	1			T11	6		T14	3		T15	1
values[2]	1530	1			T10	1		T11	3		T14	3
values[3]	1408	1			T11	1		T14	3		T15	2
values[4]	1442	1			T3	6		T4	2		T10	1
values[5]	1488	1			T3	2		T9	2		T10	4
values[6]	1460	1			T10	1		T11	1		T14	4
values[7]	1431	1			T4	2		T10	1		T11	5
values[8]	9817	1			T4	2		T9	2		T10	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30901

1

T3

8

T4

14

T5

12

auto[1]

28142

1

T14

659

T31

216

T44

257

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55776

1

T3

8

T4

14

T5

12

write

3267

1

T10

1

T11

12

T14

9

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19196

1

T3

8

T4

4

T5

12

valids[0x1]

39847

1

T4

10

T9

2

T10

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1557	1			T4	4		T10	2		T11	3
internal_process_ops[0x5a]	1621	1			T11	5		T14	15		T15	2
internal_process_ops[0x05]	20510	1			T11	127		T14	487		T15	3
internal_process_ops[0x35]	1700	1			T11	1		T14	6		T31	7
internal_process_ops[0x15]	1510	1			T10	2		T11	5		T14	7
internal_process_ops[0x03]	1099	1			T9	2		T10	1		T11	5
internal_process_ops[0x0b]	1091	1			T4	4		T11	5		T15	2
internal_process_ops[0x3b]	1074	1			T9	2		T10	3		T11	8
internal_process_ops[0x6b]	1022	1			T4	2		T10	1		T11	3
internal_process_ops[0xbb]	1000	1			T3	6		T10	1		T11	4
internal_process_ops[0xeb]	985	1			T3	2		T10	1		T11	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57354

1

T3

8

T4

14

T5

12

auto[1]

1689

1

T11

8

T14

5

T15

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56685

1

T3

8

T4

14

T5

12

auto[1]

2358

1

T11

4

T14

16

T15

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10390

1

T5

12

T10

3

T11

59

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6408

1

T4

4

T10

2

T11

91

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2096

1

T3

8

T9

2

T10

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1848

1

T4

2

T11

19

T15

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2487

1

T9

2

T10

2

T11

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2162

1

T4

4

T10

6

T11

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2075

1

T11

4

T13

4

T15

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1843

1

T4

4

T10

3

T11

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T15

2

T105

2

T53

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

108

1

T51

2

T53

2

T46

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

79

1

T11

2

T15

1

T46

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

110

1

T11

1

T15

1

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T15

1

T54

10

T20

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

119

1

T15

1

T46

1

T20

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T10

1

T11

1

T46

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

124

1

T51

2

T46

3

T56

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

105

1

T37

4

T53

1

T20

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T53

1

T46

1

T55

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T50

2

T46

2

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T46

1

T55

1

T57

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T37

2

T106

2

T54

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

71

1

T11

7

T46

2

T55

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

83

1

T11

1

T53

3

T46

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T46

1

T20

3

T73

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9533

1

T14

401

T31

63

T44

131

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7403

1

T14

147

T31

37

T44

46

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1544

1

T14

22

T31

14

T44

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1408

1

T14

19

T31

14

T44

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1906

1

T14

12

T31

23

T44

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1900

1

T14

28

T31

16

T44

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1375

1

T14

10

T31

13

T44

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1398

1

T14

11

T31

20

T44

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T14

1

T44

2

T18

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T16

5

T59

6

T18

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T44

2

T16

3

T61

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

88

1

T14

2

T16

1

T102

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

92

1

T61

2

T18

3

T99

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

124

1

T14

1

T16

2

T59

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T31

1

T44

2

T61

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T44

2

T59

1

T167

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

80

1

T14

1

T31

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

125

1

T31

4

T59

4

T165

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

117

1

T31

1

T44

4

T16

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

147

1

T31

2

T59

3

T61

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T31

2

T44

1

T59

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

107

1

T14

2

T31

3

T59

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

117

1

T14

2

T16

3

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

69

1

T31

1

T59

1

T61

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3930	1			T5	12		T10	1		T11	13
auto[0]	values[0]	valids[0x1]	15825	1			T4	8		T10	5		T11	156
auto[0]	values[1]	valids[0x1]	572	1			T11	6		T15	1		T50	1
auto[0]	values[2]	valids[0x0]	536	1			T10	1		T11	1		T15	3
auto[0]	values[2]	valids[0x1]	337	1			T11	2		T51	2		T53	2
auto[0]	values[3]	valids[0x0]	571	1			T11	1		T15	1		T50	8
auto[0]	values[3]	valids[0x1]	318	1			T15	1		T106	2		T53	3
auto[0]	values[4]	valids[0x0]	496	1			T3	6		T4	2		T10	1
auto[0]	values[4]	valids[0x1]	285	1			T11	1		T15	2		T50	1
auto[0]	values[5]	valids[0x0]	569	1			T3	2		T10	3		T11	2
auto[0]	values[5]	valids[0x1]	302	1			T9	2		T10	1		T11	1
auto[0]	values[6]	valids[0x0]	547	1			T10	1		T15	2		T53	1
auto[0]	values[6]	valids[0x1]	269	1			T11	1		T168	2		T53	1
auto[0]	values[7]	valids[0x0]	530	1			T4	2		T10	1		T11	5
auto[0]	values[7]	valids[0x1]	282	1			T15	1		T50	2		T52	2
auto[0]	values[8]	valids[0x0]	3396	1			T9	2		T10	4		T11	19
auto[0]	values[8]	valids[0x1]	2136	1			T4	2		T10	2		T11	13
auto[1]	values[0]	valids[0x0]	3894	1			T14	45		T31	42		T44	24
auto[1]	values[0]	valids[0x1]	15731	1			T14	528		T31	75		T44	173
auto[1]	values[1]	valids[0x1]	515	1			T14	3		T31	6		T44	2
auto[1]	values[2]	valids[0x0]	398	1			T14	1		T31	9		T44	4
auto[1]	values[2]	valids[0x1]	259	1			T14	2		T31	3		T44	4
auto[1]	values[3]	valids[0x0]	305	1			T14	3		T31	5		T44	2
auto[1]	values[3]	valids[0x1]	214	1			T31	1		T16	4		T61	2
auto[1]	values[4]	valids[0x0]	386	1			T14	5		T31	3		T44	2
auto[1]	values[4]	valids[0x1]	275	1			T14	5		T44	1		T16	2
auto[1]	values[5]	valids[0x0]	371	1			T14	4		T31	6		T44	3
auto[1]	values[5]	valids[0x1]	246	1			T14	1		T31	1		T44	2
auto[1]	values[6]	valids[0x0]	387	1			T14	4		T31	2		T44	4
auto[1]	values[6]	valids[0x1]	257	1			T31	6		T44	2		T16	1
auto[1]	values[7]	valids[0x0]	380	1			T14	3		T31	3		T44	3
auto[1]	values[7]	valids[0x1]	239	1			T14	4		T31	5		T44	5
auto[1]	values[8]	valids[0x0]	2500	1			T14	30		T31	22		T44	15
auto[1]	values[8]	valids[0x1]	1785	1			T14	21		T31	27		T44	11