Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3216298

1

T3

1

T4

1

T5

5787

auto[1]

31704

1

T11

123

T14

479

T15

5

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

829731

1

T3

1

T4

1

T5

5787

auto[1]

2418271

1

T10

2196

T11

8408

T14

8752

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	624376	1			T3	1		T4	1		T5	966
auto[524288:1048575]	404450	1			T5	881		T10	7		T11	1
auto[1048576:1572863]	340418	1			T11	1790		T14	64		T15	9
auto[1572864:2097151]	313950	1			T5	1203		T9	20		T11	1617
auto[2097152:2621439]	386089	1			T5	1		T9	47		T10	9
auto[2621440:3145727]	370868	1			T5	1709		T10	258		T11	772
auto[3145728:3670015]	418640	1			T5	5		T10	1		T11	3063
auto[3670016:4194303]	389211	1			T5	1022		T10	1964		T11	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2451157

1

T3

1

T4

1

T5

23

auto[1]

796845

1

T5

5764

T9

67

T11

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2826867

1

T3

1

T4

1

T5

4359

auto[1]

421135

1

T5

1428

T11

4725

T14

57

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	185910	1			T3	1		T4	1		T5	964
auto[0]	auto[0]	auto[0:524287]	auto[1]	383076	1			T11	667		T14	2		T31	2990
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	91759	1			T10	7		T11	1		T14	22
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	255798	1			T14	3402		T15	512		T31	3126
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	84640	1			T11	1		T14	2		T15	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	202828	1			T11	128		T14	6		T15	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	75700	1			T5	986		T9	20		T11	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	199899	1			T11	1600		T14	1153		T15	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	74986	1			T5	1		T9	47		T10	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	256376	1			T11	517		T14	514		T44	254
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	113991	1			T5	1381		T10	2		T11	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	204598	1			T10	256		T11	763		T14	516
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	86943	1			T5	5		T10	1		T14	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	260045	1			T14	2624		T15	2162		T31	4696
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	101577	1			T5	1022		T10	24		T11	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	222046	1			T10	1940		T14	68		T31	58
auto[0]	auto[1]	auto[0:524287]	auto[0]	1829	1			T5	2		T11	1		T16	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	49845	1			T16	1		T59	683		T236	518
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1494	1			T5	881		T14	1		T15	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	50458	1			T59	104		T61	256		T53	2047
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	859	1			T11	4		T14	2		T31	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48279	1			T11	1657		T14	1		T31	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1063	1			T5	217		T14	3		T15	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	33608	1			T14	2		T44	256		T16	1140
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	589	1			T31	1		T16	6		T59	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51351	1			T31	128		T16	2		T59	507
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	888	1			T5	328		T16	1		T59	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	46992	1			T59	1		T18	259		T46	512
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1513	1			T11	4		T31	3		T58	911
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	65101	1			T11	2957		T31	768		T59	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2173	1			T14	2		T16	3		T18	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	60084	1			T14	1		T16	2		T18	133
auto[1]	auto[0]	auto[0:524287]	auto[0]	453	1			T31	1		T44	1		T59	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2845	1			T31	2		T59	1		T18	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	486	1			T14	8		T59	5		T61	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4052	1			T14	182		T59	2		T61	132
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	373	1			T14	1		T31	1		T44	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2726	1			T14	7		T44	41		T16	66
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	374	1			T11	1		T14	1		T31	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3009	1			T11	13		T14	44		T31	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	378	1			T14	2		T44	2		T16	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1872	1			T14	80		T44	37		T16	12
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	352	1			T11	1		T14	1		T15	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3095	1			T11	6		T14	57		T31	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	423	1			T14	1		T31	3		T44	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3450	1			T14	45		T31	1		T44	18
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	335	1			T14	1		T44	1		T59	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2472	1			T14	4		T44	32		T59	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	74	1			T16	1		T236	1		T53	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	344	1			T16	8		T236	1		T53	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	94	1			T53	1		T93	1		T36	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	309	1			T53	4		T93	29		T36	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	53	1			T14	1		T93	3		T100	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	660	1			T14	44		T93	126		T183	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	88	1			T55	1		T166	1		T187	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	209	1			T55	1		T187	5		T41	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	79	1			T16	2		T59	2		T18	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	458	1			T16	6		T59	1		T18	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	100	1			T59	1		T18	3		T103	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	852	1			T59	21		T18	26		T210	12
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	86	1			T11	2		T59	1		T51	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1079	1			T11	100		T59	17		T51	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	69	1			T16	2		T102	3		T236	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	455	1			T16	83		T236	1		T233	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2009850	1			T3	1		T4	1		T5	12
auto[0]	auto[0]	auto[1]	790322	1			T5	4347		T9	67		T14	8
auto[0]	auto[1]	auto[0]	410293	1			T5	11		T11	4621		T14	11
auto[0]	auto[1]	auto[1]	5833	1			T5	1417		T11	2		T14	1
auto[1]	auto[0]	auto[0]	26117	1			T11	21		T14	429		T15	5
auto[1]	auto[0]	auto[1]	578	1			T14	5		T44	4		T59	3
auto[1]	auto[1]	auto[0]	4897	1			T11	101		T14	44		T16	102
auto[1]	auto[1]	auto[1]	112	1			T11	1		T14	1		T59	1