Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	0	8	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_write	2	0	2	100.00	100	1	1	0
cp_payload_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	8	0	8	100.00	100	1	1	0

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

809

1

T11

2

T14

11

T31

3

write

1483

1

T11

2

T14

5

T15

1

---

Summary for Variable cp_payload_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_payload_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
excess_fifo	477	1			T15	1		T31	2		T44	2
frequent_use_values[0]	853	1			T11	2		T14	11		T31	4
frequent_use_values[1]	56	1			T44	1		T59	1		T100	1
frequent_use_values[2]	60	1			T16	2		T59	1		T61	1
frequent_use_values[3]	74	1			T14	3		T16	1		T18	1
frequent_use_values[4]	49	1			T18	1		T165	1		T53	1
frequent_use_values[256]	371	1			T11	2		T31	1		T44	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_payload_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_payload_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read	frequent_use_values[0]	809	1			T11	2		T14	11		T31	3
write	excess_fifo	477	1			T15	1		T31	2		T44	2
write	frequent_use_values[0]	44	1			T31	1		T18	1		T51	1
write	frequent_use_values[1]	56	1			T44	1		T59	1		T100	1
write	frequent_use_values[2]	60	1			T16	2		T59	1		T61	1
write	frequent_use_values[3]	74	1			T14	3		T16	1		T18	1
write	frequent_use_values[4]	49	1			T18	1		T165	1		T53	1
write	frequent_use_values[256]	371	1			T11	2		T31	1		T44	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
read_w_nonzero_payload	0	Illegal