Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2827480	1			T2	1		T3	21		T4	1
all_pins[1]	2827480	1			T2	1		T3	21		T4	1
all_pins[2]	2827480	1			T2	1		T3	21		T4	1
all_pins[3]	2827480	1			T2	1		T3	21		T4	1
all_pins[4]	2827480	1			T2	1		T3	21		T4	1
all_pins[5]	2827480	1			T2	1		T3	21		T4	1
all_pins[6]	2827480	1			T2	1		T3	21		T4	1
all_pins[7]	2827480	1			T2	1		T3	21		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22616912	1			T2	8		T3	168		T4	8
values[0x1]	2928	1			T16	408		T17	18		T18	35
transitions[0x0=>0x1]	2381	1			T16	249		T17	12		T18	23
transitions[0x1=>0x0]	2393	1			T16	249		T17	12		T18	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2827140	1			T2	1		T3	21		T4	1
all_pins[0]	values[0x1]	340	1			T16	130		T17	2		T18	2
all_pins[0]	transitions[0x0=>0x1]	170	1			T16	12		T17	2		T18	1
all_pins[0]	transitions[0x1=>0x0]	165	1			T16	1		T17	4		T18	6
all_pins[1]	values[0x0]	2827145	1			T2	1		T3	21		T4	1
all_pins[1]	values[0x1]	335	1			T16	119		T17	4		T18	7
all_pins[1]	transitions[0x0=>0x1]	244	1			T16	78		T17	1		T18	3
all_pins[1]	transitions[0x1=>0x0]	124	1			T17	2		T166	2		T169	5
all_pins[2]	values[0x0]	2827265	1			T2	1		T3	21		T4	1
all_pins[2]	values[0x1]	215	1			T16	41		T17	5		T18	4
all_pins[2]	transitions[0x0=>0x1]	173	1			T16	41		T17	3		T18	2
all_pins[2]	transitions[0x1=>0x0]	160	1			T16	2		T18	2		T20	1
all_pins[3]	values[0x0]	2827278	1			T2	1		T3	21		T4	1
all_pins[3]	values[0x1]	202	1			T16	2		T17	2		T18	4
all_pins[3]	transitions[0x0=>0x1]	158	1			T16	2		T17	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	134	1			T17	2		T18	2		T20	2
all_pins[4]	values[0x0]	2827302	1			T2	1		T3	21		T4	1
all_pins[4]	values[0x1]	178	1			T17	2		T18	4		T20	2
all_pins[4]	transitions[0x0=>0x1]	147	1			T17	2		T18	4		T20	1
all_pins[4]	transitions[0x1=>0x0]	786	1			T16	116		T17	1		T18	5
all_pins[5]	values[0x0]	2826663	1			T2	1		T3	21		T4	1
all_pins[5]	values[0x1]	817	1			T16	116		T17	1		T18	5
all_pins[5]	transitions[0x0=>0x1]	725	1			T16	116		T18	4		T20	1
all_pins[5]	transitions[0x1=>0x0]	567	1			T17	1		T18	3		T34	2
all_pins[6]	values[0x0]	2826821	1			T2	1		T3	21		T4	1
all_pins[6]	values[0x1]	659	1			T17	2		T18	4		T34	3
all_pins[6]	transitions[0x0=>0x1]	620	1			T17	2		T18	2		T34	2
all_pins[6]	transitions[0x1=>0x0]	143	1			T18	3		T20	4		T33	5
all_pins[7]	values[0x0]	2827298	1			T2	1		T3	21		T4	1
all_pins[7]	values[0x1]	182	1			T18	5		T20	4		T33	5
all_pins[7]	transitions[0x0=>0x1]	144	1			T18	5		T20	4		T33	5
all_pins[7]	transitions[0x1=>0x0]	314	1			T16	130		T17	2		T18	2