Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17884

1

T3

8

T5

12

T9

4

auto[1]

13017

1

T4

14

T10

12

T11

128

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4159	1			T5	12		T11	62		T163	6
values[1]	3474	1			T11	34		T26	6		T50	20
values[2]	3446	1			T3	8		T11	20		T15	40
values[3]	3631	1			T4	14		T9	4		T104	2
values[4]	4171	1			T13	12		T37	14		T122	12
values[5]	3390	1			T10	20		T50	20		T168	12
values[6]	4309	1			T15	20		T58	4		T38	16
values[7]	4321	1			T11	107		T51	41		T237	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3783	1			T15	20		T53	28		T86	18
values[1]	3043	1			T4	14		T26	6		T38	16
values[2]	4037	1			T11	82		T50	20		T163	6
values[3]	3562	1			T9	4		T11	121		T15	20
values[4]	3737	1			T5	12		T10	20		T15	20
values[5]	4845	1			T3	8		T13	12		T105	20
values[6]	3758	1			T50	20		T51	92		T238	2
values[7]	4136	1			T11	20		T58	4		T237	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	237	1			T73	15		T185	10		T187	19
auto[0]	values[0]	values[1]	275	1			T46	9		T210	12		T213	49
auto[0]	values[0]	values[2]	434	1			T11	53		T166	13		T213	9
auto[0]	values[0]	values[3]	151	1			T88	4		T232	10		T190	13
auto[0]	values[0]	values[4]	372	1			T5	12		T239	20		T166	15
auto[0]	values[0]	values[5]	407	1			T106	18		T92	113		T57	12
auto[0]	values[0]	values[6]	401	1			T238	2		T73	11		T41	9
auto[0]	values[0]	values[7]	255	1			T53	28		T46	15		T240	4
auto[0]	values[1]	values[0]	385	1			T53	18		T86	18		T55	12
auto[0]	values[1]	values[1]	168	1			T26	6		T187	9		T195	21
auto[0]	values[1]	values[2]	88	1			T53	16		T210	10		T241	20
auto[0]	values[1]	values[3]	200	1			T11	5		T189	12		T242	2
auto[0]	values[1]	values[4]	250	1			T67	10		T73	86		T166	12
auto[0]	values[1]	values[5]	284	1			T243	4		T244	22		T210	10
auto[0]	values[1]	values[6]	226	1			T50	12		T51	13		T179	8
auto[0]	values[1]	values[7]	352	1			T166	10		T94	29		T186	18
auto[0]	values[2]	values[0]	198	1			T226	11		T184	12		T193	9
auto[0]	values[2]	values[1]	182	1			T55	13		T228	22		T245	8
auto[0]	values[2]	values[2]	276	1			T50	9		T166	14		T213	13
auto[0]	values[2]	values[3]	196	1			T15	16		T46	16		T73	41
auto[0]	values[2]	values[4]	223	1			T15	15		T210	12		T94	93
auto[0]	values[2]	values[5]	359	1			T3	8		T246	12		T71	14
auto[0]	values[2]	values[6]	344	1			T247	14		T71	14		T166	14
auto[0]	values[2]	values[7]	283	1			T11	10		T248	7		T200	43
auto[0]	values[3]	values[0]	168	1			T195	13		T41	10		T249	14
auto[0]	values[3]	values[1]	125	1			T104	2		T223	4		T138	9
auto[0]	values[3]	values[2]	493	1			T87	18		T250	8		T208	61
auto[0]	values[3]	values[3]	431	1			T9	4		T251	8		T55	12
auto[0]	values[3]	values[4]	531	1			T53	25		T213	14		T225	12
auto[0]	values[3]	values[5]	150	1			T46	10		T187	10		T41	16
auto[0]	values[3]	values[6]	169	1			T20	14		T187	11		T195	10
auto[0]	values[3]	values[7]	168	1			T55	19		T252	8		T209	24
auto[0]	values[4]	values[0]	352	1			T46	11		T20	22		T72	8
auto[0]	values[4]	values[1]	191	1			T184	10		T138	15		T41	8
auto[0]	values[4]	values[2]	281	1			T213	13		T232	10		T188	12
auto[0]	values[4]	values[3]	358	1			T37	14		T20	24		T213	10
auto[0]	values[4]	values[4]	185	1			T122	12		T94	23		T41	10
auto[0]	values[4]	values[5]	206	1			T13	12		T76	2		T20	13
auto[0]	values[4]	values[6]	202	1			T253	10		T73	32		T213	9
auto[0]	values[4]	values[7]	277	1			T185	12		T184	22		T138	8
auto[0]	values[5]	values[0]	181	1			T46	11		T20	23		T57	8
auto[0]	values[5]	values[1]	87	1			T52	16		T20	17		T179	13
auto[0]	values[5]	values[2]	273	1			T46	26		T73	16		T207	29
auto[0]	values[5]	values[3]	176	1			T71	14		T215	20		T210	9
auto[0]	values[5]	values[4]	181	1			T10	8		T168	12		T55	12
auto[0]	values[5]	values[5]	389	1			T50	8		T20	10		T232	8
auto[0]	values[5]	values[6]	331	1			T190	47		T205	14		T193	28
auto[0]	values[5]	values[7]	351	1			T53	22		T54	28		T73	9
auto[0]	values[6]	values[0]	333	1			T15	15		T20	11		T57	10
auto[0]	values[6]	values[1]	342	1			T38	16		T229	2		T254	18
auto[0]	values[6]	values[2]	231	1			T46	12		T185	30		T217	9
auto[0]	values[6]	values[3]	223	1			T222	13		T187	12		T41	17
auto[0]	values[6]	values[4]	320	1			T50	12		T55	15		T213	12
auto[0]	values[6]	values[5]	374	1			T105	20		T53	18		T255	2
auto[0]	values[6]	values[6]	190	1			T73	14		T256	2		T207	10
auto[0]	values[6]	values[7]	578	1			T58	4		T257	10		T232	16
auto[0]	values[7]	values[0]	239	1			T55	15		T20	9		T195	20
auto[0]	values[7]	values[1]	275	1			T46	15		T187	15		T179	10
auto[0]	values[7]	values[2]	253	1			T11	16		T20	13		T71	10
auto[0]	values[7]	values[3]	359	1			T11	11		T51	28		T227	16
auto[0]	values[7]	values[4]	214	1			T20	51		T187	24		T232	15
auto[0]	values[7]	values[5]	513	1			T71	28		T185	29		T187	74
auto[0]	values[7]	values[6]	316	1			T46	16		T73	13		T258	18
auto[0]	values[7]	values[7]	322	1			T237	2		T55	13		T71	116
auto[1]	values[0]	values[0]	294	1			T73	5		T185	10		T187	10
auto[1]	values[0]	values[1]	261	1			T46	11		T210	63		T213	8
auto[1]	values[0]	values[2]	209	1			T11	9		T163	6		T166	9
auto[1]	values[0]	values[3]	118	1			T232	10		T190	7		T259	14
auto[1]	values[0]	values[4]	115	1			T166	9		T94	6		T184	11
auto[1]	values[0]	values[5]	182	1			T57	8		T94	12		T213	39
auto[1]	values[0]	values[6]	275	1			T56	16		T73	9		T41	12
auto[1]	values[0]	values[7]	173	1			T53	4		T46	5		T190	7
auto[1]	values[1]	values[0]	136	1			T53	10		T55	8		T20	10
auto[1]	values[1]	values[1]	124	1			T187	12		T195	19		T221	8
auto[1]	values[1]	values[2]	58	1			T53	4		T210	16		T190	13
auto[1]	values[1]	values[3]	275	1			T11	29		T179	7		T188	35
auto[1]	values[1]	values[4]	194	1			T73	6		T166	12		T220	12
auto[1]	values[1]	values[5]	364	1			T210	17		T138	9		T188	44
auto[1]	values[1]	values[6]	246	1			T50	8		T51	79		T179	12
auto[1]	values[1]	values[7]	124	1			T166	10		T94	11		T205	12
auto[1]	values[2]	values[0]	207	1			T226	9		T184	8		T193	66
auto[1]	values[2]	values[1]	115	1			T55	7		T41	11		T221	5
auto[1]	values[2]	values[2]	147	1			T50	11		T166	7		T213	8
auto[1]	values[2]	values[3]	128	1			T15	4		T46	4		T73	10
auto[1]	values[2]	values[4]	89	1			T15	5		T210	8		T94	13
auto[1]	values[2]	values[5]	250	1			T71	93		T73	10		T187	7
auto[1]	values[2]	values[6]	318	1			T71	44		T166	6		T185	9
auto[1]	values[2]	values[7]	131	1			T11	10		T248	13		T221	9
auto[1]	values[3]	values[0]	128	1			T195	10		T41	11		T196	33
auto[1]	values[3]	values[1]	208	1			T4	14		T138	11		T208	10
auto[1]	values[3]	values[2]	198	1			T260	16		T208	9		T261	11
auto[1]	values[3]	values[3]	182	1			T55	8		T210	9		T262	18
auto[1]	values[3]	values[4]	265	1			T53	60		T213	11		T179	6
auto[1]	values[3]	values[5]	150	1			T46	10		T187	14		T41	4
auto[1]	values[3]	values[6]	138	1			T20	6		T187	9		T195	10
auto[1]	values[3]	values[7]	127	1			T55	9		T263	20		T208	8
auto[1]	values[4]	values[0]	383	1			T46	9		T20	5		T193	55
auto[1]	values[4]	values[1]	182	1			T184	10		T138	13		T41	12
auto[1]	values[4]	values[2]	444	1			T213	126		T232	98		T188	20
auto[1]	values[4]	values[3]	141	1			T20	1		T213	10		T205	8
auto[1]	values[4]	values[4]	190	1			T94	25		T41	10		T264	22
auto[1]	values[4]	values[5]	384	1			T20	64		T210	29		T184	13
auto[1]	values[4]	values[6]	137	1			T73	4		T213	22		T190	10
auto[1]	values[4]	values[7]	258	1			T185	8		T184	20		T138	14
auto[1]	values[5]	values[0]	97	1			T46	9		T20	5		T57	12
auto[1]	values[5]	values[1]	148	1			T20	44		T179	7		T188	28
auto[1]	values[5]	values[2]	237	1			T46	14		T73	4		T207	15
auto[1]	values[5]	values[3]	93	1			T71	6		T210	11		T187	13
auto[1]	values[5]	values[4]	87	1			T10	12		T55	8		T184	11
auto[1]	values[5]	values[5]	293	1			T50	12		T20	14		T232	12
auto[1]	values[5]	values[6]	187	1			T190	17		T205	40		T193	4
auto[1]	values[5]	values[7]	279	1			T53	32		T73	11		T166	6
auto[1]	values[6]	values[0]	266	1			T15	5		T20	9		T57	10
auto[1]	values[6]	values[1]	101	1			T221	8		T265	4		T266	5
auto[1]	values[6]	values[2]	153	1			T46	8		T185	10		T217	21
auto[1]	values[6]	values[3]	234	1			T267	14		T222	19		T187	8
auto[1]	values[6]	values[4]	286	1			T50	8		T55	5		T213	10
auto[1]	values[6]	values[5]	288	1			T53	6		T73	6		T205	153
auto[1]	values[6]	values[6]	153	1			T73	6		T207	10		T268	9
auto[1]	values[6]	values[7]	237	1			T232	10		T41	6		T190	9
auto[1]	values[7]	values[0]	179	1			T55	7		T20	11		T195	9
auto[1]	values[7]	values[1]	259	1			T46	5		T187	5		T179	10
auto[1]	values[7]	values[2]	262	1			T11	4		T20	7		T71	21
auto[1]	values[7]	values[3]	297	1			T11	76		T51	13		T269	6
auto[1]	values[7]	values[4]	235	1			T20	6		T187	29		T232	61
auto[1]	values[7]	values[5]	252	1			T270	16		T71	5		T185	7
auto[1]	values[7]	values[6]	125	1			T46	4		T73	7		T271	16
auto[1]	values[7]	values[7]	221	1			T55	9		T272	6		T71	12