Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	376	1			T9	2		T11	4		T15	2
auto[ReadAddrCrossIntoMailbox]	299	1			T11	1		T50	1		T53	5
auto[ReadAddrCrossOutOfMailbox]	261	1			T11	2		T15	1		T50	1
auto[ReadAddrCrossAllMailbox]	201	1			T51	1		T53	2		T55	4
auto[ReadAddrOutsideMailbox]	3626	1			T3	8		T4	6		T10	7

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2293

1

T3

4

T4

3

T9

1

auto[1]

2470

1

T3

4

T4

3

T9

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	837	1			T9	2		T10	1		T11	5
read_ops[0x0b]	837	1			T4	4		T11	5		T15	2
read_ops[0x3b]	837	1			T10	3		T11	8		T15	2
read_ops[0x6b]	772	1			T4	2		T10	1		T11	3
read_ops[0xbb]	747	1			T3	6		T10	1		T11	4
read_ops[0xeb]	733	1			T3	2		T10	1		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T9	1		T46	1		T166	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T9	1		T51	1		T53	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T88	1		T55	1		T20	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T88	1		T73	1		T187	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T11	1		T20	1		T195	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T53	1		T166	1		T193	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T53	1		T195	2		T273	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T51	1		T94	1		T213	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T11	2		T13	2		T15	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	320	1			T10	1		T11	2		T13	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T53	2		T46	1		T20	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T11	1		T15	1		T55	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T53	1		T55	1		T225	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T11	1		T55	1		T71	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T53	1		T20	3		T57	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	1		T55	1		T73	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T55	1		T213	1		T217	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T55	2		T94	1		T213	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T4	2		T37	1		T50	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T4	2		T11	2		T15	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T46	1		T55	1		T166	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T11	1		T46	1		T55	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T53	1		T232	1		T138	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T166	2		T213	1		T232	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T71	1		T226	1		T138	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T53	1		T55	1		T185	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T20	1		T232	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T274	1		T194	2		T231	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T10	3		T11	5		T52	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	344	1			T11	2		T15	2		T50	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T20	1		T187	1		T213	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T11	1		T51	2		T73	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T94	1		T232	1		T138	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T73	2		T187	1		T232	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T50	1		T53	1		T73	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T190	2		T234	1		T194	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T20	1		T187	1		T179	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T53	1		T73	1		T166	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T4	1		T11	2		T50	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T4	1		T10	1		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T20	1		T223	1		T166	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T11	1		T15	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T53	1		T46	1		T73	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T53	1		T166	2		T187	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T94	1		T213	1		T205	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T15	1		T53	1		T94	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T213	1		T205	1		T234	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T94	1		T213	2		T179	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T3	3		T11	3		T105	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T3	3		T10	1		T15	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T53	1		T46	1		T73	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T55	1		T73	1		T213	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T53	1		T73	1		T166	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T50	1		T20	1		T73	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T73	1		T187	1		T184	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T187	1		T213	1		T41	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T55	1		T166	1		T213	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T41	1		T214	1		T193	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T3	1		T10	1		T11	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T3	1		T15	2		T50	1