Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3954	1			T10	20		T11	62		T104	2
values[1]	4624	1			T3	8		T105	20		T51	133
values[2]	3587	1			T11	20		T15	20		T26	6
values[3]	4253	1			T15	20		T106	18		T237	2
values[4]	4102	1			T163	6		T53	60		T55	28
values[5]	3693	1			T4	14		T11	20		T50	20
values[6]	3751	1			T9	4		T13	12		T38	16
values[7]	2937	1			T5	12		T11	121		T15	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4356	1			T13	12		T51	41		T106	18
values[1]	4213	1			T9	4		T15	20		T105	20
values[2]	4453	1			T52	16		T53	61		T88	4
values[3]	3543	1			T5	12		T10	20		T58	4
values[4]	2917	1			T3	8		T11	87		T50	40
values[5]	4267	1			T4	14		T11	20		T15	40
values[6]	3724	1			T11	34		T38	16		T104	2
values[7]	3428	1			T11	82		T26	6		T37	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30083

1

T3

8

T4

14

T5

12

auto[1]

818

1

T11

8

T15

2

T50

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	490	1			T55	20		T73	40		T187	77
auto[0]	values[0]	values[1]	552	1			T168	12		T53	48		T251	8
auto[0]	values[0]	values[2]	618	1			T53	24		T46	20		T213	47
auto[0]	values[0]	values[3]	424	1			T10	20		T46	19		T166	22
auto[0]	values[0]	values[4]	289	1			T46	16		T260	14		T275	18
auto[0]	values[0]	values[5]	494	1			T57	19		T187	26		T195	21
auto[0]	values[0]	values[6]	558	1			T104	2		T270	16		T73	49
auto[0]	values[0]	values[7]	427	1			T11	62		T46	19		T267	10
auto[0]	values[1]	values[0]	578	1			T51	39		T210	20		T41	38
auto[0]	values[1]	values[1]	672	1			T105	20		T51	90		T71	89
auto[0]	values[1]	values[2]	755	1			T210	37		T187	19		T213	22
auto[0]	values[1]	values[3]	285	1			T53	20		T184	20		T200	43
auto[0]	values[1]	values[4]	474	1			T3	8		T71	20		T72	8
auto[0]	values[1]	values[5]	370	1			T184	26		T41	20		T190	20
auto[0]	values[1]	values[6]	732	1			T53	34		T46	20		T263	18
auto[0]	values[1]	values[7]	638	1			T189	12		T92	113		T269	6
auto[0]	values[2]	values[0]	436	1			T184	26		T41	40		T264	16
auto[0]	values[2]	values[1]	401	1			T57	19		T210	26		T213	57
auto[0]	values[2]	values[2]	582	1			T20	79		T73	120		T187	19
auto[0]	values[2]	values[3]	390	1			T210	26		T222	32		T207	20
auto[0]	values[2]	values[4]	393	1			T50	20		T46	19		T55	20
auto[0]	values[2]	values[5]	595	1			T15	18		T255	2		T193	32
auto[0]	values[2]	values[6]	233	1			T242	2		T190	39		T193	51
auto[0]	values[2]	values[7]	457	1			T11	20		T26	6		T50	19
auto[0]	values[3]	values[0]	776	1			T106	18		T20	27		T187	25
auto[0]	values[3]	values[1]	635	1			T15	20		T71	33		T166	20
auto[0]	values[3]	values[2]	426	1			T46	20		T101	12		T94	103
auto[0]	values[3]	values[3]	636	1			T20	57		T56	12		T226	20
auto[0]	values[3]	values[4]	320	1			T238	2		T232	19		T196	74
auto[0]	values[3]	values[5]	410	1			T55	21		T94	28		T203	12
auto[0]	values[3]	values[6]	595	1			T187	20		T276	16		T205	23
auto[0]	values[3]	values[7]	333	1			T237	2		T239	20		T55	20
auto[0]	values[4]	values[0]	796	1			T73	20		T213	158		T195	20
auto[0]	values[4]	values[1]	494	1			T163	6		T20	20		T73	90
auto[0]	values[4]	values[2]	426	1			T41	22		T207	20		T208	20
auto[0]	values[4]	values[3]	493	1			T53	27		T138	21		T277	12
auto[0]	values[4]	values[4]	365	1			T186	18		T195	19		T179	20
auto[0]	values[4]	values[5]	621	1			T57	20		T227	16		T166	23
auto[0]	values[4]	values[6]	376	1			T53	29		T20	27		T94	20
auto[0]	values[4]	values[7]	441	1			T55	26		T213	53		T41	40
auto[0]	values[5]	values[0]	533	1			T73	36		T245	8		T188	20
auto[0]	values[5]	values[1]	469	1			T53	20		T55	22		T20	77
auto[0]	values[5]	values[2]	534	1			T53	36		T88	4		T210	147
auto[0]	values[5]	values[3]	382	1			T166	19		T278	65		T279	4
auto[0]	values[5]	values[4]	287	1			T50	20		T76	2		T55	19
auto[0]	values[5]	values[5]	614	1			T4	14		T11	13		T246	12
auto[0]	values[5]	values[6]	479	1			T67	10		T71	124		T166	20
auto[0]	values[5]	values[7]	281	1			T187	20		T220	12		T184	20
auto[0]	values[6]	values[0]	330	1			T13	12		T248	66		T280	22
auto[0]	values[6]	values[1]	517	1			T9	4		T50	20		T71	107
auto[0]	values[6]	values[2]	543	1			T55	20		T253	10		T69	12
auto[0]	values[6]	values[3]	533	1			T46	19		T57	19		T185	20
auto[0]	values[6]	values[4]	364	1			T252	8		T281	6		T224	25
auto[0]	values[6]	values[5]	562	1			T122	12		T254	18		T184	20
auto[0]	values[6]	values[6]	342	1			T38	16		T73	20		T166	23
auto[0]	values[6]	values[7]	466	1			T86	18		T247	14		T228	22
auto[0]	values[7]	values[0]	313	1			T87	18		T46	20		T243	4
auto[0]	values[7]	values[1]	367	1			T195	19		T282	16		T224	18
auto[0]	values[7]	values[2]	437	1			T52	16		T46	18		T20	18
auto[0]	values[7]	values[3]	310	1			T5	12		T58	4		T272	6
auto[0]	values[7]	values[4]	347	1			T11	87		T166	21		T185	39
auto[0]	values[7]	values[5]	478	1			T15	20		T54	28		T262	14
auto[0]	values[7]	values[6]	313	1			T11	33		T240	4		T179	18
auto[0]	values[7]	values[7]	296	1			T37	14		T210	20		T224	25
auto[1]	values[0]	values[0]	8	1			T187	1		T65	1		T283	1
auto[1]	values[0]	values[1]	10	1			T138	2		T188	2		T274	1
auto[1]	values[0]	values[2]	20	1			T213	1		T195	1		T221	2
auto[1]	values[0]	values[3]	14	1			T46	1		T94	1		T284	2
auto[1]	values[0]	values[4]	17	1			T46	4		T260	2		T235	1
auto[1]	values[0]	values[5]	10	1			T57	1		T187	2		T195	2
auto[1]	values[0]	values[6]	9	1			T73	2		T285	1		T266	1
auto[1]	values[0]	values[7]	14	1			T46	1		T267	4		T187	2
auto[1]	values[1]	values[0]	21	1			T51	2		T41	2		T190	1
auto[1]	values[1]	values[1]	11	1			T51	2		T73	1		T184	1
auto[1]	values[1]	values[2]	21	1			T187	1		T213	3		T184	3
auto[1]	values[1]	values[3]	10	1			T286	4		T287	2		T288	4
auto[1]	values[1]	values[4]	14	1			T205	3		T192	1		T197	1
auto[1]	values[1]	values[5]	15	1			T184	2		T41	1		T224	3
auto[1]	values[1]	values[6]	11	1			T263	2		T217	2		T196	2
auto[1]	values[1]	values[7]	17	1			T207	2		T265	2		T266	2
auto[1]	values[2]	values[0]	19	1			T184	1		T41	3		T264	6
auto[1]	values[2]	values[1]	12	1			T57	1		T41	1		T271	2
auto[1]	values[2]	values[2]	17	1			T20	2		T73	2		T187	5
auto[1]	values[2]	values[3]	9	1			T210	1		T191	5		T289	1
auto[1]	values[2]	values[4]	10	1			T46	1		T20	1		T274	1
auto[1]	values[2]	values[5]	14	1			T15	2		T231	1		T290	1
auto[1]	values[2]	values[6]	12	1			T190	2		T193	1		T285	1
auto[1]	values[2]	values[7]	7	1			T50	1		T291	2		T65	3
auto[1]	values[3]	values[0]	21	1			T94	1		T213	2		T285	1
auto[1]	values[3]	values[1]	19	1			T179	2		T232	3		T41	4
auto[1]	values[3]	values[2]	18	1			T94	3		T213	1		T138	2
auto[1]	values[3]	values[3]	15	1			T56	4		T187	1		T230	2
auto[1]	values[3]	values[4]	4	1			T232	1		T196	1		T141	1
auto[1]	values[3]	values[5]	17	1			T55	1		T94	2		T188	2
auto[1]	values[3]	values[6]	17	1			T187	1		T205	1		T217	1
auto[1]	values[3]	values[7]	11	1			T196	2		T292	3		T293	2
auto[1]	values[4]	values[0]	6	1			T213	1		T217	2		T208	1
auto[1]	values[4]	values[1]	11	1			T73	2		T138	1		T280	1
auto[1]	values[4]	values[2]	11	1			T201	6		T66	2		T294	3
auto[1]	values[4]	values[3]	8	1			T53	1		T138	1		T206	1
auto[1]	values[4]	values[4]	10	1			T195	3		T248	2		T230	1
auto[1]	values[4]	values[5]	18	1			T166	1		T210	1		T213	1
auto[1]	values[4]	values[6]	12	1			T53	3		T20	1		T188	4
auto[1]	values[4]	values[7]	14	1			T55	2		T213	2		T196	1
auto[1]	values[5]	values[0]	16	1			T234	2		T204	2		T295	2
auto[1]	values[5]	values[1]	12	1			T185	2		T201	3		T259	3
auto[1]	values[5]	values[2]	18	1			T53	1		T210	3		T185	1
auto[1]	values[5]	values[3]	9	1			T166	2		T296	2		T274	1
auto[1]	values[5]	values[4]	12	1			T55	1		T179	2		T204	1
auto[1]	values[5]	values[5]	17	1			T11	7		T232	1		T205	4
auto[1]	values[5]	values[6]	24	1			T71	4		T248	4		T297	2
auto[1]	values[5]	values[7]	6	1			T235	1		T231	3		T283	1
auto[1]	values[6]	values[0]	4	1			T219	3		T298	1		-	-
auto[1]	values[6]	values[1]	17	1			T138	1		T234	2		T268	1
auto[1]	values[6]	values[2]	15	1			T235	3		T194	3		T231	2
auto[1]	values[6]	values[3]	12	1			T46	1		T57	1		T187	4
auto[1]	values[6]	values[4]	5	1			T299	2		T294	1		T300	2
auto[1]	values[6]	values[5]	20	1			T138	2		T221	3		T190	2
auto[1]	values[6]	values[6]	5	1			T166	1		T198	2		T293	1
auto[1]	values[6]	values[7]	16	1			T166	2		T184	5		T235	2
auto[1]	values[7]	values[0]	9	1			T187	2		T184	2		T138	1
auto[1]	values[7]	values[1]	14	1			T195	1		T224	2		T280	2
auto[1]	values[7]	values[2]	12	1			T46	2		T20	2		T207	1
auto[1]	values[7]	values[3]	13	1			T184	2		T224	5		T289	1
auto[1]	values[7]	values[4]	6	1			T166	1		T185	1		T141	2
auto[1]	values[7]	values[5]	12	1			T262	4		T138	1		T190	1
auto[1]	values[7]	values[6]	6	1			T11	1		T179	2		T196	1
auto[1]	values[7]	values[7]	4	1			T192	2		T283	1		T301	1