Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838	1			T16	4		T17	8		T18	14
all_values[1]	838	1			T16	4		T17	8		T18	14
all_values[2]	838	1			T16	4		T17	8		T18	14
all_values[3]	838	1			T16	4		T17	8		T18	14
all_values[4]	838	1			T16	4		T17	8		T18	14
all_values[5]	838	1			T16	4		T17	8		T18	14
all_values[6]	838	1			T16	4		T17	8		T18	14
all_values[7]	838	1			T16	4		T17	8		T18	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3696

1

T16

12

T17

31

T18

42

auto[1]

3008

1

T16

20

T17

33

T18

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2750

1

T16

21

T17

32

T18

39

auto[1]

3954

1

T16

11

T17

32

T18

73

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3878

1

T16

25

T17

43

T18

58

auto[1]

2826

1

T16

7

T17

21

T18

54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	166	1			T17	1		T18	1		T20	5
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T16	1		T17	1		T18	2
all_values[0]	auto[0]	auto[1]	auto[0]	139	1			T17	2		T18	3		T20	2
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T16	1		T17	1		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	208	1			T16	1		T17	1		T18	3
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T16	1		T17	2		T18	5
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T17	3		T20	3		T33	3
all_values[1]	auto[0]	auto[0]	auto[1]	90	1			T33	1		T34	1		T166	3
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T16	1		T17	1		T18	2
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T16	1		T17	1		T18	4
all_values[1]	auto[1]	auto[0]	auto[1]	208	1			T16	1		T17	1		T18	2
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T16	1		T17	2		T18	6
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T16	2		T18	2		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	95	1			T17	3		T18	1		T20	2
all_values[2]	auto[0]	auto[1]	auto[0]	146	1			T16	1		T18	2		T20	3
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T17	2		T18	2		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	206	1			T17	2		T18	2		T20	3
all_values[2]	auto[1]	auto[1]	auto[1]	142	1			T16	1		T17	1		T18	5
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T17	3		T18	1		T20	8
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T33	1		T34	2		T166	1
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T16	2		T17	1		T18	4
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T16	1		T17	1		T18	2
all_values[3]	auto[1]	auto[0]	auto[1]	204	1			T16	1		T17	2		T18	2
all_values[3]	auto[1]	auto[1]	auto[1]	175	1			T17	1		T18	5		T20	3
all_values[4]	auto[0]	auto[0]	auto[0]	167	1			T16	1		T17	3		T18	5
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T18	1		T20	2		T33	1
all_values[4]	auto[0]	auto[1]	auto[0]	163	1			T16	3		T17	3		T18	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T18	2		T20	1		T34	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T18	1		T20	8		T33	6
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T17	2		T18	4		T20	3
all_values[5]	auto[0]	auto[0]	auto[0]	267	1			T17	2		T18	2		T20	8
all_values[5]	auto[0]	auto[1]	auto[0]	242	1			T16	4		T17	2		T18	5
all_values[5]	auto[1]	auto[0]	auto[1]	193	1			T17	3		T18	6		T20	3
all_values[5]	auto[1]	auto[1]	auto[1]	136	1			T17	1		T18	1		T20	1
all_values[6]	auto[0]	auto[0]	auto[0]	191	1			T16	4		T17	2		T18	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T17	1		T18	2		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	149	1			T17	2		T18	3		T20	2
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T17	1		T18	2		T34	2
all_values[6]	auto[1]	auto[0]	auto[1]	209	1			T18	3		T20	4		T33	6
all_values[6]	auto[1]	auto[1]	auto[1]	135	1			T17	2		T18	3		T34	3
all_values[7]	auto[0]	auto[0]	auto[0]	180	1			T17	3		T18	4		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T20	3		T33	1		T34	2
all_values[7]	auto[0]	auto[1]	auto[0]	149	1			T16	3		T17	4		T18	3
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T18	1		T20	3		T33	2
all_values[7]	auto[1]	auto[0]	auto[1]	186	1			T16	1		T18	1		T20	4
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T17	1		T18	5		T20	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal