Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1730

1

T2

5

T6

4

T8

7

auto[1]

1638

1

T2

2

T6

3

T8

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1746

1

T6

7

T27

1

T31

13

auto[1]

1622

1

T2

7

T8

10

T28

45

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2685

1

T2

7

T6

3

T8

10

auto[1]

683

1

T6

4

T31

7

T25

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	665	1			T2	2		T6	2		T8	4
valid[1]	683	1			T2	1		T6	1		T8	2
valid[2]	687	1			T2	2		T6	1		T28	7
valid[3]	674	1			T2	2		T6	1		T8	1
valid[4]	659	1			T6	2		T8	3		T28	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	113	1			T6	1		T31	2		T93	2
auto[0]	auto[0]	valid[0]	auto[1]	166	1			T2	1		T8	3		T28	5
auto[0]	auto[0]	valid[1]	auto[0]	115	1			T27	1		T99	1		T167	1
auto[0]	auto[0]	valid[1]	auto[1]	162	1			T2	1		T8	1		T28	4
auto[0]	auto[0]	valid[2]	auto[0]	106	1			T6	1		T25	1		T53	1
auto[0]	auto[0]	valid[2]	auto[1]	173	1			T2	1		T28	4		T29	3
auto[0]	auto[0]	valid[3]	auto[0]	109	1			T31	2		T25	2		T99	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T2	2		T8	1		T28	5
auto[0]	auto[0]	valid[4]	auto[0]	124	1			T6	1		T31	1		T25	2
auto[0]	auto[0]	valid[4]	auto[1]	162	1			T8	2		T28	5		T29	2
auto[0]	auto[1]	valid[0]	auto[0]	104	1			T25	2		T59	2		T75	1
auto[0]	auto[1]	valid[0]	auto[1]	157	1			T2	1		T8	1		T28	6
auto[0]	auto[1]	valid[1]	auto[0]	95	1			T59	1		T99	1		T53	1
auto[0]	auto[1]	valid[1]	auto[1]	171	1			T8	1		T29	6		T31	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T99	4		T236	1		T167	1
auto[0]	auto[1]	valid[2]	auto[1]	148	1			T2	1		T28	3		T29	2
auto[0]	auto[1]	valid[3]	auto[0]	98	1			T31	1		T59	1		T99	4
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T28	8		T30	2		T39	1
auto[0]	auto[1]	valid[4]	auto[0]	82	1			T25	1		T167	1		T55	2
auto[0]	auto[1]	valid[4]	auto[1]	161	1			T8	1		T28	5		T29	1
auto[1]	auto[0]	valid[0]	auto[0]	63	1			T6	1		T31	1		T25	1
auto[1]	auto[0]	valid[1]	auto[0]	82	1			T31	1		T25	1		T99	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T99	2		T236	1		T93	1
auto[1]	auto[0]	valid[3]	auto[0]	65	1			T167	2		T33	3		T313	1
auto[1]	auto[0]	valid[4]	auto[0]	61	1			T236	1		T167	2		T33	1
auto[1]	auto[1]	valid[0]	auto[0]	62	1			T31	1		T59	1		T99	1
auto[1]	auto[1]	valid[1]	auto[0]	58	1			T6	1		T36	1		T226	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T31	1		T25	2		T59	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T6	1		T31	3		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T6	1		T25	1		T99	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal