Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45739

1

T6

164

T7

11

T27

10

auto[1]

16237

1

T2

7

T6

33

T8

197

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45221

1

T2

7

T6

129

T7

5

auto[1]

16755

1

T6

68

T7

6

T27

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32145	1			T2	7		T6	101		T7	5
others[1]	5258	1			T6	17		T7	1		T8	15
others[2]	5135	1			T6	17		T8	6		T27	1
others[3]	5889	1			T6	15		T7	1		T8	24
interest[1]	3469	1			T6	10		T8	21		T28	32
interest[4]	21138	1			T2	7		T6	67		T7	2
interest[64]	10080	1			T6	37		T7	4		T8	32

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14919	1			T6	55		T7	2		T27	5
auto[0]	auto[0]	others[1]	2464	1			T6	4		T7	1		T31	10
auto[0]	auto[0]	others[2]	2425	1			T6	10		T27	1		T31	6
auto[0]	auto[0]	others[3]	2743	1			T6	8		T7	1		T31	8
auto[0]	auto[0]	interest[1]	1633	1			T6	1		T31	14		T16	2
auto[0]	auto[0]	interest[4]	9756	1			T6	34		T7	1		T27	5
auto[0]	auto[0]	interest[64]	4800	1			T6	18		T7	1		T27	2
auto[0]	auto[1]	others[0]	8589	1			T2	7		T6	14		T8	99
auto[0]	auto[1]	others[1]	1393	1			T6	5		T8	15		T28	43
auto[0]	auto[1]	others[2]	1325	1			T6	2		T8	6		T28	49
auto[0]	auto[1]	others[3]	1521	1			T6	2		T8	24		T28	42
auto[0]	auto[1]	interest[1]	878	1			T6	3		T8	21		T28	32
auto[0]	auto[1]	interest[4]	5728	1			T2	7		T6	10		T8	63
auto[0]	auto[1]	interest[64]	2531	1			T6	7		T8	32		T28	88
auto[1]	auto[0]	others[0]	8637	1			T6	32		T7	3		T27	1
auto[1]	auto[0]	others[1]	1401	1			T6	8		T31	12		T16	4
auto[1]	auto[0]	others[2]	1385	1			T6	5		T31	11		T16	6
auto[1]	auto[0]	others[3]	1625	1			T6	5		T31	14		T22	1
auto[1]	auto[0]	interest[1]	958	1			T6	6		T31	8		T16	3
auto[1]	auto[0]	interest[4]	5654	1			T6	23		T7	1		T27	1
auto[1]	auto[0]	interest[64]	2749	1			T6	12		T7	3		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal