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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T1026 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4216787896 Aug 18 05:09:30 PM PDT 24 Aug 18 05:09:34 PM PDT 24 119095485 ps
T1027 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2365330952 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:05 PM PDT 24 49398366 ps
T173 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4122203672 Aug 18 05:09:13 PM PDT 24 Aug 18 05:09:20 PM PDT 24 346283870 ps
T1028 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1855885695 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:31 PM PDT 24 699810900 ps
T1029 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1830406193 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:33 PM PDT 24 90572583 ps
T1030 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1135378267 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:04 PM PDT 24 25446258 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.997430323 Aug 18 05:09:01 PM PDT 24 Aug 18 05:09:23 PM PDT 24 1294769087 ps
T171 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1572106799 Aug 18 05:09:21 PM PDT 24 Aug 18 05:09:41 PM PDT 24 2433412607 ps
T177 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4024357762 Aug 18 05:08:49 PM PDT 24 Aug 18 05:09:11 PM PDT 24 615648547 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.990168773 Aug 18 05:09:01 PM PDT 24 Aug 18 05:09:03 PM PDT 24 28770302 ps
T1031 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.550173530 Aug 18 05:10:06 PM PDT 24 Aug 18 05:10:06 PM PDT 24 45761217 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3737698004 Aug 18 05:08:50 PM PDT 24 Aug 18 05:08:52 PM PDT 24 30580670 ps
T176 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3124134516 Aug 18 05:09:55 PM PDT 24 Aug 18 05:10:08 PM PDT 24 920653092 ps
T1033 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2582951783 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:31 PM PDT 24 50575904 ps
T153 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3450132413 Aug 18 05:09:55 PM PDT 24 Aug 18 05:09:57 PM PDT 24 74550521 ps
T128 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.672624611 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:43 PM PDT 24 200071523 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2676728121 Aug 18 05:08:52 PM PDT 24 Aug 18 05:08:55 PM PDT 24 429308595 ps
T1035 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2374512363 Aug 18 05:09:04 PM PDT 24 Aug 18 05:09:06 PM PDT 24 113161854 ps
T1036 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.851034695 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:31 PM PDT 24 72144117 ps
T1037 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1298670376 Aug 18 05:09:32 PM PDT 24 Aug 18 05:09:34 PM PDT 24 29828558 ps
T118 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.163415782 Aug 18 05:09:39 PM PDT 24 Aug 18 05:09:44 PM PDT 24 675440473 ps
T154 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.59070335 Aug 18 05:09:42 PM PDT 24 Aug 18 05:09:44 PM PDT 24 100988576 ps
T132 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3413830803 Aug 18 05:08:53 PM PDT 24 Aug 18 05:09:05 PM PDT 24 371666335 ps
T129 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3484003661 Aug 18 05:09:11 PM PDT 24 Aug 18 05:09:13 PM PDT 24 92488061 ps
T1038 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2818053901 Aug 18 05:09:19 PM PDT 24 Aug 18 05:09:23 PM PDT 24 122785726 ps
T1039 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4287026516 Aug 18 05:10:02 PM PDT 24 Aug 18 05:10:03 PM PDT 24 20529391 ps
T155 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1954882159 Aug 18 05:09:46 PM PDT 24 Aug 18 05:09:49 PM PDT 24 357160457 ps
T1040 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.311189600 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:34 PM PDT 24 65162788 ps
T1041 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3509667347 Aug 18 05:10:02 PM PDT 24 Aug 18 05:10:03 PM PDT 24 88748062 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.44585993 Aug 18 05:09:19 PM PDT 24 Aug 18 05:09:19 PM PDT 24 18862669 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.616613131 Aug 18 05:09:00 PM PDT 24 Aug 18 05:09:01 PM PDT 24 15029762 ps
T156 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3206446041 Aug 18 05:09:46 PM PDT 24 Aug 18 05:09:48 PM PDT 24 61720732 ps
T1044 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1808249812 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:56 PM PDT 24 136896493 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.211172165 Aug 18 05:09:04 PM PDT 24 Aug 18 05:09:06 PM PDT 24 54633545 ps
T1045 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3782109570 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:03 PM PDT 24 11204016 ps
T1046 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2031696124 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:05 PM PDT 24 16334269 ps
T115 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4133082864 Aug 18 05:09:38 PM PDT 24 Aug 18 05:09:51 PM PDT 24 449140495 ps
T131 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2014294408 Aug 18 05:09:30 PM PDT 24 Aug 18 05:09:33 PM PDT 24 327801866 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1131697424 Aug 18 05:09:53 PM PDT 24 Aug 18 05:09:56 PM PDT 24 120767239 ps
T96 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3395860452 Aug 18 05:09:10 PM PDT 24 Aug 18 05:09:11 PM PDT 24 118707185 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2583255941 Aug 18 05:09:11 PM PDT 24 Aug 18 05:09:13 PM PDT 24 209600178 ps
T178 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4244287450 Aug 18 05:09:44 PM PDT 24 Aug 18 05:10:03 PM PDT 24 1204950456 ps
T1049 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.315245403 Aug 18 05:09:41 PM PDT 24 Aug 18 05:09:44 PM PDT 24 364058035 ps
T1050 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2282786109 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:05 PM PDT 24 14551252 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.263796103 Aug 18 05:09:32 PM PDT 24 Aug 18 05:09:33 PM PDT 24 36727763 ps
T97 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3576553615 Aug 18 05:08:51 PM PDT 24 Aug 18 05:08:52 PM PDT 24 40677777 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1305628653 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:54 PM PDT 24 1121248034 ps
T1053 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3242113910 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 86754758 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1322877479 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:55 PM PDT 24 11141106214 ps
T1055 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.68552034 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:35 PM PDT 24 59740065 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3902470602 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:34 PM PDT 24 154138662 ps
T1057 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2756864480 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:35 PM PDT 24 120851813 ps
T1058 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3494920446 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:32 PM PDT 24 1499795532 ps
T133 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4254978994 Aug 18 05:09:20 PM PDT 24 Aug 18 05:09:28 PM PDT 24 1238404049 ps
T1059 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.501464670 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:55 PM PDT 24 59412542 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2275190878 Aug 18 05:08:51 PM PDT 24 Aug 18 05:08:52 PM PDT 24 14938362 ps
T1061 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1001605926 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:41 PM PDT 24 16883566 ps
T1062 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2092317086 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 70466875 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.445288500 Aug 18 05:09:00 PM PDT 24 Aug 18 05:09:09 PM PDT 24 1514204744 ps
T1064 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3816459675 Aug 18 05:09:30 PM PDT 24 Aug 18 05:09:31 PM PDT 24 36030317 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2520824064 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:56 PM PDT 24 97161918 ps
T1066 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2117913280 Aug 18 05:09:20 PM PDT 24 Aug 18 05:09:21 PM PDT 24 32096423 ps
T1067 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1131133667 Aug 18 05:10:02 PM PDT 24 Aug 18 05:10:03 PM PDT 24 56629173 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3981444314 Aug 18 05:09:41 PM PDT 24 Aug 18 05:09:42 PM PDT 24 12222160 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2273920526 Aug 18 05:09:19 PM PDT 24 Aug 18 05:09:22 PM PDT 24 161741663 ps
T98 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3271692051 Aug 18 05:08:59 PM PDT 24 Aug 18 05:09:00 PM PDT 24 32607747 ps
T1070 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.264903893 Aug 18 05:09:41 PM PDT 24 Aug 18 05:09:44 PM PDT 24 136812215 ps
T1071 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3671860009 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:05 PM PDT 24 13240305 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2036857398 Aug 18 05:09:30 PM PDT 24 Aug 18 05:09:34 PM PDT 24 150700435 ps
T134 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.189409242 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:33 PM PDT 24 27029187 ps
T135 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1242298590 Aug 18 05:09:39 PM PDT 24 Aug 18 05:09:41 PM PDT 24 88853666 ps
T1073 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3069153892 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:43 PM PDT 24 468610408 ps
T1074 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3888892589 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:31 PM PDT 24 83560410 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2557269475 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:43 PM PDT 24 230981802 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2081644495 Aug 18 05:09:19 PM PDT 24 Aug 18 05:09:21 PM PDT 24 26627623 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2895067454 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:58 PM PDT 24 109318007 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3467446570 Aug 18 05:09:30 PM PDT 24 Aug 18 05:09:33 PM PDT 24 253885019 ps
T174 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1052996473 Aug 18 05:09:29 PM PDT 24 Aug 18 05:09:43 PM PDT 24 795368975 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4272439850 Aug 18 05:09:19 PM PDT 24 Aug 18 05:09:25 PM PDT 24 315237979 ps
T1080 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2040562699 Aug 18 05:09:12 PM PDT 24 Aug 18 05:09:13 PM PDT 24 34543388 ps
T1081 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.161117454 Aug 18 05:10:02 PM PDT 24 Aug 18 05:10:03 PM PDT 24 41415633 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3763380295 Aug 18 05:08:49 PM PDT 24 Aug 18 05:08:52 PM PDT 24 28924938 ps
T1083 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3590467942 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:32 PM PDT 24 19313302 ps
T1084 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1919286720 Aug 18 05:09:32 PM PDT 24 Aug 18 05:09:50 PM PDT 24 599345606 ps
T1085 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2547845748 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:55 PM PDT 24 24558004 ps
T1086 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.343515891 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:33 PM PDT 24 26195991 ps
T1087 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4155806201 Aug 18 05:09:42 PM PDT 24 Aug 18 05:09:45 PM PDT 24 182647068 ps
T1088 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2802063446 Aug 18 05:09:53 PM PDT 24 Aug 18 05:09:56 PM PDT 24 91446350 ps
T1089 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4179111937 Aug 18 05:09:55 PM PDT 24 Aug 18 05:09:56 PM PDT 24 82458652 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.378986623 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:58 PM PDT 24 56407305 ps
T1091 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2681875843 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:32 PM PDT 24 179791941 ps
T1092 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2898464371 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:32 PM PDT 24 20849499 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2266936780 Aug 18 05:09:55 PM PDT 24 Aug 18 05:09:57 PM PDT 24 259341927 ps
T1094 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1516438281 Aug 18 05:09:09 PM PDT 24 Aug 18 05:09:18 PM PDT 24 442332936 ps
T1095 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4096237382 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 17957461 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.548603220 Aug 18 05:09:21 PM PDT 24 Aug 18 05:09:22 PM PDT 24 14468632 ps
T1097 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3223495937 Aug 18 05:09:53 PM PDT 24 Aug 18 05:09:54 PM PDT 24 12538703 ps
T1098 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.414452245 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:03 PM PDT 24 14737513 ps
T1099 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1226063290 Aug 18 05:09:42 PM PDT 24 Aug 18 05:09:46 PM PDT 24 235267852 ps
T1100 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4000156446 Aug 18 05:10:04 PM PDT 24 Aug 18 05:10:04 PM PDT 24 25732518 ps
T1101 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3860192767 Aug 18 05:09:39 PM PDT 24 Aug 18 05:09:44 PM PDT 24 155002012 ps
T1102 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1197814451 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:34 PM PDT 24 91428165 ps
T1103 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1102988154 Aug 18 05:10:02 PM PDT 24 Aug 18 05:10:03 PM PDT 24 11595866 ps
T1104 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3489460717 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:55 PM PDT 24 1879394805 ps
T1105 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4169479641 Aug 18 05:09:44 PM PDT 24 Aug 18 05:09:45 PM PDT 24 27560384 ps
T1106 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.504437154 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 23526312 ps
T1107 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1587347376 Aug 18 05:09:39 PM PDT 24 Aug 18 05:09:41 PM PDT 24 219577737 ps
T1108 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3426534319 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 15285187 ps
T1109 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1695760328 Aug 18 05:09:45 PM PDT 24 Aug 18 05:09:53 PM PDT 24 1492966944 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2859803010 Aug 18 05:09:11 PM PDT 24 Aug 18 05:09:45 PM PDT 24 2375924355 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.234939876 Aug 18 05:09:12 PM PDT 24 Aug 18 05:09:16 PM PDT 24 251851240 ps
T1112 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3096294295 Aug 18 05:08:49 PM PDT 24 Aug 18 05:09:05 PM PDT 24 7632151175 ps
T1113 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3995364671 Aug 18 05:09:39 PM PDT 24 Aug 18 05:09:47 PM PDT 24 306271246 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.201721287 Aug 18 05:09:46 PM PDT 24 Aug 18 05:09:47 PM PDT 24 38568896 ps
T1115 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2674878370 Aug 18 05:09:54 PM PDT 24 Aug 18 05:09:57 PM PDT 24 46642343 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3875611264 Aug 18 05:09:21 PM PDT 24 Aug 18 05:09:21 PM PDT 24 21322720 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4032473186 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:34 PM PDT 24 117761964 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2818818398 Aug 18 05:09:12 PM PDT 24 Aug 18 05:09:13 PM PDT 24 150155812 ps
T1119 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.561436024 Aug 18 05:10:06 PM PDT 24 Aug 18 05:10:07 PM PDT 24 47632033 ps
T1120 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2951606185 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 12508756 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2518618176 Aug 18 05:08:59 PM PDT 24 Aug 18 05:09:04 PM PDT 24 308783370 ps
T1122 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.928576730 Aug 18 05:09:41 PM PDT 24 Aug 18 05:09:43 PM PDT 24 116688646 ps
T1123 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.909367497 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:41 PM PDT 24 38572899 ps
T1124 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1880485561 Aug 18 05:09:19 PM PDT 24 Aug 18 05:09:21 PM PDT 24 235700804 ps
T1125 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3024486512 Aug 18 05:09:31 PM PDT 24 Aug 18 05:09:32 PM PDT 24 17749342 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.278113659 Aug 18 05:09:01 PM PDT 24 Aug 18 05:09:02 PM PDT 24 55077990 ps
T1127 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4081806926 Aug 18 05:09:40 PM PDT 24 Aug 18 05:09:46 PM PDT 24 1254427964 ps
T1128 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.484755133 Aug 18 05:10:01 PM PDT 24 Aug 18 05:10:02 PM PDT 24 43628144 ps
T1129 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3436796757 Aug 18 05:10:03 PM PDT 24 Aug 18 05:10:04 PM PDT 24 52952888 ps
T1130 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.271787384 Aug 18 05:09:53 PM PDT 24 Aug 18 05:09:54 PM PDT 24 17848532 ps
T1131 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.556065083 Aug 18 05:09:01 PM PDT 24 Aug 18 05:09:19 PM PDT 24 1490498462 ps

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1128434815
Short name T4
Test name
Test status
Simulation time 3351431512 ps
CPU time 10.12 seconds
Started Aug 18 04:53:23 PM PDT 24
Finished Aug 18 04:53:33 PM PDT 24
Peak memory 225428 kb
Host smart-f034e90e-0b2f-4298-9052-3cc8bf307a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128434815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1128434815
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.946807844
Short name T31
Test name
Test status
Simulation time 156652447005 ps
CPU time 349.16 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 05:01:18 PM PDT 24
Peak memory 272516 kb
Host smart-aca006f2-ef04-4f98-9974-a0003697dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946807844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.946807844
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1440945479
Short name T166
Test name
Test status
Simulation time 279823032282 ps
CPU time 713.56 seconds
Started Aug 18 04:56:41 PM PDT 24
Finished Aug 18 05:08:35 PM PDT 24
Peak memory 267296 kb
Host smart-e5784acd-2f7f-4130-b524-93e06eda1d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440945479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1440945479
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.257656936
Short name T53
Test name
Test status
Simulation time 7727330426 ps
CPU time 137.04 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:59:57 PM PDT 24
Peak memory 266804 kb
Host smart-b2745648-f4d4-490d-b7dc-52415da14055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257656936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.257656936
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1010956415
Short name T108
Test name
Test status
Simulation time 4510130337 ps
CPU time 26.1 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:57 PM PDT 24
Peak memory 215396 kb
Host smart-2d1344ad-39d3-4f4f-85bd-2564f0e87a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010956415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1010956415
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2178522995
Short name T99
Test name
Test status
Simulation time 4142766952 ps
CPU time 33.4 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:49 PM PDT 24
Peak memory 225516 kb
Host smart-aba84367-f02c-4293-b347-a47756cf1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178522995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2178522995
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2387432165
Short name T11
Test name
Test status
Simulation time 7369790226 ps
CPU time 50.13 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 250132 kb
Host smart-8119e60a-b084-44c3-bba3-30b4053ae6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387432165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2387432165
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2165927890
Short name T82
Test name
Test status
Simulation time 21458758 ps
CPU time 0.76 seconds
Started Aug 18 04:53:16 PM PDT 24
Finished Aug 18 04:53:17 PM PDT 24
Peak memory 216672 kb
Host smart-d7db75cf-e0cf-4845-94a3-0226230afd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165927890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2165927890
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.587711744
Short name T20
Test name
Test status
Simulation time 31015260802 ps
CPU time 258.97 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:59:34 PM PDT 24
Peak memory 269540 kb
Host smart-56f87907-9f39-4750-828d-f85276843504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587711744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.587711744
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2390865040
Short name T138
Test name
Test status
Simulation time 113066879214 ps
CPU time 331.9 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 05:01:00 PM PDT 24
Peak memory 274372 kb
Host smart-d1ea2c04-eca4-4fc8-ab71-0a13d77a0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390865040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2390865040
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3810338278
Short name T41
Test name
Test status
Simulation time 95578536642 ps
CPU time 889.71 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 05:11:28 PM PDT 24
Peak memory 269176 kb
Host smart-2221c4c1-0cae-4be5-90d3-4756ec6684a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810338278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3810338278
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4058256702
Short name T1
Test name
Test status
Simulation time 2768970730 ps
CPU time 6.28 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:19 PM PDT 24
Peak memory 223012 kb
Host smart-e83f6fbf-b127-4a2c-84a7-f8ee5a013303
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4058256702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4058256702
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2337579001
Short name T46
Test name
Test status
Simulation time 55899996551 ps
CPU time 408.17 seconds
Started Aug 18 04:56:43 PM PDT 24
Finished Aug 18 05:03:31 PM PDT 24
Peak memory 257400 kb
Host smart-034592f2-d86b-4958-b9aa-db15bf468670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337579001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2337579001
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.764461461
Short name T21
Test name
Test status
Simulation time 248895085 ps
CPU time 1.07 seconds
Started Aug 18 04:53:23 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 237080 kb
Host smart-2be9c6df-15b9-4e0e-8009-5786e6169b2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764461461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.764461461
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.240424362
Short name T114
Test name
Test status
Simulation time 1025664257 ps
CPU time 5.51 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:35 PM PDT 24
Peak memory 215216 kb
Host smart-9d3ded26-cbc5-4c8f-b610-79801153d5a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240424362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.240424362
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2986857857
Short name T317
Test name
Test status
Simulation time 10422711659 ps
CPU time 120.1 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:59:21 PM PDT 24
Peak memory 249988 kb
Host smart-83fbc01d-0da5-4567-9650-974b946aca9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986857857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2986857857
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1362431903
Short name T213
Test name
Test status
Simulation time 17980874027 ps
CPU time 85.84 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:55:01 PM PDT 24
Peak memory 266948 kb
Host smart-702153be-baca-4d35-a751-3230af7c05eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362431903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1362431903
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.269316160
Short name T187
Test name
Test status
Simulation time 15518658865 ps
CPU time 116.26 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 274736 kb
Host smart-04128e96-670c-42d4-9a62-6c7676cd2855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269316160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.269316160
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1915351952
Short name T190
Test name
Test status
Simulation time 14282937735 ps
CPU time 162.9 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:58:55 PM PDT 24
Peak memory 274456 kb
Host smart-a862a9a3-25d3-42ec-8455-214f8e14ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915351952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1915351952
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2663174490
Short name T123
Test name
Test status
Simulation time 38316413 ps
CPU time 1.37 seconds
Started Aug 18 05:08:49 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 206848 kb
Host smart-7e33d31d-9767-4911-baf9-b366cbb0228a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663174490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
663174490
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2861842686
Short name T693
Test name
Test status
Simulation time 18601186586 ps
CPU time 113.15 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:59:24 PM PDT 24
Peak memory 266636 kb
Host smart-a458ca72-10f6-491c-ad69-f7165f38b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861842686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2861842686
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2776662520
Short name T230
Test name
Test status
Simulation time 272537754388 ps
CPU time 466.79 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 05:04:34 PM PDT 24
Peak memory 264488 kb
Host smart-a0fa9554-50a1-45c5-aaf7-5f883f28e837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776662520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2776662520
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3765126691
Short name T14
Test name
Test status
Simulation time 4257855796 ps
CPU time 59.86 seconds
Started Aug 18 04:57:36 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 241924 kb
Host smart-5dfe9eef-339d-4ff3-96f2-a83fce3fbca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765126691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3765126691
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3971488943
Short name T28
Test name
Test status
Simulation time 32443395755 ps
CPU time 16.3 seconds
Started Aug 18 04:57:23 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 217276 kb
Host smart-da9101c1-213d-4c38-be0b-ad4bd50223a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971488943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3971488943
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2446423436
Short name T234
Test name
Test status
Simulation time 215288007710 ps
CPU time 387.58 seconds
Started Aug 18 04:54:29 PM PDT 24
Finished Aug 18 05:00:57 PM PDT 24
Peak memory 240644 kb
Host smart-643c6dfc-d3ab-4b1b-9f3b-e6233777a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446423436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2446423436
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.724026941
Short name T205
Test name
Test status
Simulation time 51647076827 ps
CPU time 156.85 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 274232 kb
Host smart-0011c32a-3260-466b-9308-e6fcebc5351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724026941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.724026941
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2879632141
Short name T196
Test name
Test status
Simulation time 18650940586 ps
CPU time 126.37 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 05:00:04 PM PDT 24
Peak memory 269776 kb
Host smart-ad42d596-3030-4285-bb47-e3d2e0eb3889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879632141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2879632141
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2287825216
Short name T219
Test name
Test status
Simulation time 42436494867 ps
CPU time 396.74 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 05:00:31 PM PDT 24
Peak memory 282420 kb
Host smart-801aafd8-4651-45ad-a92b-68cfa9ac5e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287825216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2287825216
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3039506145
Short name T401
Test name
Test status
Simulation time 11276245 ps
CPU time 0.74 seconds
Started Aug 18 04:54:29 PM PDT 24
Finished Aug 18 04:54:30 PM PDT 24
Peak memory 205628 kb
Host smart-65ec70ac-1bf2-449c-a68a-98007f03009a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039506145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3039506145
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.372135753
Short name T307
Test name
Test status
Simulation time 4481891527 ps
CPU time 18.81 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:55:06 PM PDT 24
Peak memory 234728 kb
Host smart-57b211ff-90aa-4d1a-93e9-03294baa35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372135753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.372135753
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4133082864
Short name T115
Test name
Test status
Simulation time 449140495 ps
CPU time 12.64 seconds
Started Aug 18 05:09:38 PM PDT 24
Finished Aug 18 05:09:51 PM PDT 24
Peak memory 215128 kb
Host smart-7ec66a75-90a6-4246-b666-7c6cfe9c9196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133082864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4133082864
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3822234927
Short name T111
Test name
Test status
Simulation time 133562377 ps
CPU time 3.97 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:23 PM PDT 24
Peak memory 216196 kb
Host smart-785a7b3e-d0b5-48d1-9a84-aacb0718cf2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822234927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
822234927
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1663110054
Short name T195
Test name
Test status
Simulation time 17502620815 ps
CPU time 139.41 seconds
Started Aug 18 04:53:33 PM PDT 24
Finished Aug 18 04:55:53 PM PDT 24
Peak memory 272088 kb
Host smart-216bfc33-fb91-4cbf-a9bc-f6efeb101fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663110054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1663110054
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3700002641
Short name T283
Test name
Test status
Simulation time 78903578022 ps
CPU time 198.07 seconds
Started Aug 18 04:55:43 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 268440 kb
Host smart-bd08b007-9f88-45cf-abe1-08ccf2d0e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700002641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3700002641
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2627266872
Short name T139
Test name
Test status
Simulation time 4195131989 ps
CPU time 89.22 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:58:10 PM PDT 24
Peak memory 252500 kb
Host smart-47ff9b82-8590-45bb-ae46-203053d5b833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627266872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2627266872
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.483453396
Short name T59
Test name
Test status
Simulation time 60381481638 ps
CPU time 328.77 seconds
Started Aug 18 04:54:24 PM PDT 24
Finished Aug 18 04:59:53 PM PDT 24
Peak memory 257816 kb
Host smart-a5cdc879-5d38-4a0a-a7a9-8efcf06b9cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483453396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.483453396
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3197765032
Short name T34
Test name
Test status
Simulation time 98381825042 ps
CPU time 198.42 seconds
Started Aug 18 04:54:36 PM PDT 24
Finished Aug 18 04:57:54 PM PDT 24
Peak memory 257016 kb
Host smart-7a3f2eb2-bf21-4885-b490-c662ce20154a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197765032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3197765032
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.532596187
Short name T274
Test name
Test status
Simulation time 107443435829 ps
CPU time 255.58 seconds
Started Aug 18 04:53:15 PM PDT 24
Finished Aug 18 04:57:30 PM PDT 24
Peak memory 250168 kb
Host smart-90117ab5-e5be-4b49-a46a-4aa159adbb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532596187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.532596187
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2379170784
Short name T898
Test name
Test status
Simulation time 323226458332 ps
CPU time 763.73 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 05:07:41 PM PDT 24
Peak memory 274200 kb
Host smart-dbe3debd-430f-4773-a3fe-8308240c701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379170784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2379170784
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3715191084
Short name T305
Test name
Test status
Simulation time 2061739320 ps
CPU time 7.6 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:25 PM PDT 24
Peak memory 225240 kb
Host smart-31774db0-2d40-4ebb-9c77-3a2a4e698836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715191084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3715191084
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.392794007
Short name T524
Test name
Test status
Simulation time 30062735602 ps
CPU time 191 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:58:47 PM PDT 24
Peak memory 257388 kb
Host smart-47523120-5e6b-4a26-9b5c-6e55cae93ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392794007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.392794007
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4109731486
Short name T289
Test name
Test status
Simulation time 2486016527 ps
CPU time 66.64 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 04:57:08 PM PDT 24
Peak memory 257956 kb
Host smart-17072caf-0836-458f-8150-aeb1d0232e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109731486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4109731486
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3875552439
Short name T294
Test name
Test status
Simulation time 11207019159 ps
CPU time 52.56 seconds
Started Aug 18 04:54:11 PM PDT 24
Finished Aug 18 04:55:03 PM PDT 24
Peak memory 265756 kb
Host smart-85adf973-9d76-4645-9091-b53461c20624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875552439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3875552439
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1776688774
Short name T81
Test name
Test status
Simulation time 2239130598 ps
CPU time 15.63 seconds
Started Aug 18 05:08:51 PM PDT 24
Finished Aug 18 05:09:07 PM PDT 24
Peak memory 215332 kb
Host smart-f8872b4e-cddd-4bfd-9b51-7ee8d9631193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776688774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1776688774
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.444461051
Short name T561
Test name
Test status
Simulation time 7566273131 ps
CPU time 80.6 seconds
Started Aug 18 04:53:25 PM PDT 24
Finished Aug 18 04:54:45 PM PDT 24
Peak memory 253784 kb
Host smart-f756fc28-2c09-481a-b8b3-e547ab6fd767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444461051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
444461051
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.715610890
Short name T608
Test name
Test status
Simulation time 16495375270 ps
CPU time 26.66 seconds
Started Aug 18 04:54:30 PM PDT 24
Finished Aug 18 04:54:57 PM PDT 24
Peak memory 235680 kb
Host smart-bae45e6b-a68e-49c0-bb39-edc7433a6770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715610890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.715610890
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1340835024
Short name T286
Test name
Test status
Simulation time 29042935624 ps
CPU time 108.39 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 240644 kb
Host smart-9f544458-fd16-4de4-a801-70fb4dde5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340835024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1340835024
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2035436571
Short name T934
Test name
Test status
Simulation time 7780170263 ps
CPU time 111.75 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:56:57 PM PDT 24
Peak memory 254104 kb
Host smart-aa469720-0d23-43a1-872e-771c0633a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035436571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2035436571
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2202294517
Short name T329
Test name
Test status
Simulation time 26003393648 ps
CPU time 67.49 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:56:14 PM PDT 24
Peak memory 252804 kb
Host smart-eb87f0f9-ff3a-4c7d-bd78-af73a50caa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202294517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2202294517
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.619895068
Short name T302
Test name
Test status
Simulation time 641287086 ps
CPU time 16.16 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:54:10 PM PDT 24
Peak memory 225356 kb
Host smart-971d296d-74c9-424b-a5d2-c591d0ddc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619895068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.619895068
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2257159502
Short name T331
Test name
Test status
Simulation time 41095464 ps
CPU time 0.79 seconds
Started Aug 18 04:53:17 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 207328 kb
Host smart-e69d3a9c-76f0-450f-8866-b1cf54da0f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257159502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2257159502
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3944681571
Short name T101
Test name
Test status
Simulation time 184436872 ps
CPU time 3.74 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:54:59 PM PDT 24
Peak memory 225244 kb
Host smart-3d4fc2fd-af46-464b-875d-c7b6d902ae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944681571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3944681571
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2971477003
Short name T189
Test name
Test status
Simulation time 489094835 ps
CPU time 9.53 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:55:43 PM PDT 24
Peak memory 240352 kb
Host smart-9a8d80b8-cc93-48e4-a819-454813fc620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971477003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2971477003
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3576553615
Short name T97
Test name
Test status
Simulation time 40677777 ps
CPU time 1.31 seconds
Started Aug 18 05:08:51 PM PDT 24
Finished Aug 18 05:08:52 PM PDT 24
Peak memory 206920 kb
Host smart-6d73cb13-eb9f-4bc6-985a-2ccba332347c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576553615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3576553615
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.343515891
Short name T1086
Test name
Test status
Simulation time 26195991 ps
CPU time 1.84 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 215360 kb
Host smart-c08157f8-32bb-44b8-b502-3ddb28c6713d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343515891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.343515891
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3096294295
Short name T1112
Test name
Test status
Simulation time 7632151175 ps
CPU time 15.31 seconds
Started Aug 18 05:08:49 PM PDT 24
Finished Aug 18 05:09:05 PM PDT 24
Peak memory 215088 kb
Host smart-0b5192ca-b24a-4d74-b716-b9454e0c5fb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096294295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3096294295
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3413830803
Short name T132
Test name
Test status
Simulation time 371666335 ps
CPU time 12.1 seconds
Started Aug 18 05:08:53 PM PDT 24
Finished Aug 18 05:09:05 PM PDT 24
Peak memory 206736 kb
Host smart-c3513bdd-6fa0-47ac-adb7-8bc6ba38ab9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413830803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3413830803
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2272687309
Short name T1023
Test name
Test status
Simulation time 97422292 ps
CPU time 1.77 seconds
Started Aug 18 05:08:49 PM PDT 24
Finished Aug 18 05:08:51 PM PDT 24
Peak memory 216188 kb
Host smart-853ca9a1-2efc-483f-b762-11fae42fcae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272687309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2272687309
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2275190878
Short name T1060
Test name
Test status
Simulation time 14938362 ps
CPU time 0.75 seconds
Started Aug 18 05:08:51 PM PDT 24
Finished Aug 18 05:08:52 PM PDT 24
Peak memory 203716 kb
Host smart-745bc68f-2e5c-4d74-bcee-c05f9b0800c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275190878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
275190878
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3763380295
Short name T1082
Test name
Test status
Simulation time 28924938 ps
CPU time 2.47 seconds
Started Aug 18 05:08:49 PM PDT 24
Finished Aug 18 05:08:52 PM PDT 24
Peak memory 215004 kb
Host smart-551a6b33-936e-401f-8ccb-6d5805883d86
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763380295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3763380295
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2796825252
Short name T1014
Test name
Test status
Simulation time 13072010 ps
CPU time 0.68 seconds
Started Aug 18 05:08:52 PM PDT 24
Finished Aug 18 05:08:53 PM PDT 24
Peak memory 203448 kb
Host smart-dfd53bcf-51ed-45af-84c7-a7f9f461f6bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796825252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2796825252
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2676728121
Short name T1034
Test name
Test status
Simulation time 429308595 ps
CPU time 3.09 seconds
Started Aug 18 05:08:52 PM PDT 24
Finished Aug 18 05:08:55 PM PDT 24
Peak memory 214992 kb
Host smart-16b0d3d9-96b2-4575-b720-76fb3fa7bc97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676728121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2676728121
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3737698004
Short name T1032
Test name
Test status
Simulation time 30580670 ps
CPU time 2.22 seconds
Started Aug 18 05:08:50 PM PDT 24
Finished Aug 18 05:08:52 PM PDT 24
Peak memory 215284 kb
Host smart-74bd274d-5908-4ce2-9acb-8e4f2c68c710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737698004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
737698004
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.445288500
Short name T1063
Test name
Test status
Simulation time 1514204744 ps
CPU time 8.15 seconds
Started Aug 18 05:09:00 PM PDT 24
Finished Aug 18 05:09:09 PM PDT 24
Peak memory 206816 kb
Host smart-0fc980de-99b8-4fa3-8b06-a6b449010850
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445288500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.445288500
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.997430323
Short name T126
Test name
Test status
Simulation time 1294769087 ps
CPU time 21.89 seconds
Started Aug 18 05:09:01 PM PDT 24
Finished Aug 18 05:09:23 PM PDT 24
Peak memory 206736 kb
Host smart-79321957-557a-4878-8ae8-7951404c9ee1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997430323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.997430323
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3271692051
Short name T98
Test name
Test status
Simulation time 32607747 ps
CPU time 1.2 seconds
Started Aug 18 05:08:59 PM PDT 24
Finished Aug 18 05:09:00 PM PDT 24
Peak memory 206744 kb
Host smart-70364b0f-8544-4feb-b11b-babfc7805fae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271692051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3271692051
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1105503081
Short name T1022
Test name
Test status
Simulation time 103245259 ps
CPU time 1.89 seconds
Started Aug 18 05:09:00 PM PDT 24
Finished Aug 18 05:09:02 PM PDT 24
Peak memory 215980 kb
Host smart-584d82c7-44d3-4340-83c9-80682e3d5ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105503081 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1105503081
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.211172165
Short name T130
Test name
Test status
Simulation time 54633545 ps
CPU time 1.85 seconds
Started Aug 18 05:09:04 PM PDT 24
Finished Aug 18 05:09:06 PM PDT 24
Peak memory 215108 kb
Host smart-46d5e6f8-0716-48d8-91a4-ea0647fd3abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211172165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.211172165
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.278113659
Short name T1126
Test name
Test status
Simulation time 55077990 ps
CPU time 0.7 seconds
Started Aug 18 05:09:01 PM PDT 24
Finished Aug 18 05:09:02 PM PDT 24
Peak memory 203584 kb
Host smart-86e0a60d-d97b-44a0-a04f-223d95708d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278113659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.278113659
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.990168773
Short name T127
Test name
Test status
Simulation time 28770302 ps
CPU time 2.39 seconds
Started Aug 18 05:09:01 PM PDT 24
Finished Aug 18 05:09:03 PM PDT 24
Peak memory 214924 kb
Host smart-9fc70200-df1c-44b4-9bd5-9448fa868c13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990168773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.990168773
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.322003129
Short name T1024
Test name
Test status
Simulation time 19123091 ps
CPU time 0.67 seconds
Started Aug 18 05:09:00 PM PDT 24
Finished Aug 18 05:09:00 PM PDT 24
Peak memory 203552 kb
Host smart-b563f9ef-aff2-4506-896d-d2a72b5e2aee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322003129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.322003129
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2518618176
Short name T1121
Test name
Test status
Simulation time 308783370 ps
CPU time 4.55 seconds
Started Aug 18 05:08:59 PM PDT 24
Finished Aug 18 05:09:04 PM PDT 24
Peak memory 215072 kb
Host smart-71e1174a-1ac8-4045-8ccf-4947843ee596
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518618176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2518618176
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3974817095
Short name T113
Test name
Test status
Simulation time 151849665 ps
CPU time 2.72 seconds
Started Aug 18 05:08:50 PM PDT 24
Finished Aug 18 05:08:53 PM PDT 24
Peak memory 215132 kb
Host smart-7d6ed2a1-0bef-4001-be24-b5a8f4b66292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974817095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
974817095
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4024357762
Short name T177
Test name
Test status
Simulation time 615648547 ps
CPU time 20.94 seconds
Started Aug 18 05:08:49 PM PDT 24
Finished Aug 18 05:09:11 PM PDT 24
Peak memory 215192 kb
Host smart-eb30c122-a10a-4464-a593-ca96ae51a97a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024357762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4024357762
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2756864480
Short name T1057
Test name
Test status
Simulation time 120851813 ps
CPU time 3.6 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:35 PM PDT 24
Peak memory 218180 kb
Host smart-5eb56ae1-aa3d-4e65-86d2-047f596fee17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756864480 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2756864480
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2014294408
Short name T131
Test name
Test status
Simulation time 327801866 ps
CPU time 2.66 seconds
Started Aug 18 05:09:30 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 215096 kb
Host smart-f02478c5-cd73-4f59-8d32-fa5b80c4ba23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014294408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2014294408
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.263796103
Short name T1051
Test name
Test status
Simulation time 36727763 ps
CPU time 0.74 seconds
Started Aug 18 05:09:32 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 203636 kb
Host smart-ae30ac89-9960-417f-a991-d26020286a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263796103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.263796103
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3494920446
Short name T1058
Test name
Test status
Simulation time 1499795532 ps
CPU time 3.6 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:32 PM PDT 24
Peak memory 215040 kb
Host smart-22c1535b-00ae-44ea-b2a4-cbaa8244d895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494920446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3494920446
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1919286720
Short name T1084
Test name
Test status
Simulation time 599345606 ps
CPU time 18.69 seconds
Started Aug 18 05:09:32 PM PDT 24
Finished Aug 18 05:09:50 PM PDT 24
Peak memory 215732 kb
Host smart-6a9da585-d2d3-4a29-9a19-e0648aa97586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919286720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1919286720
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.59070335
Short name T154
Test name
Test status
Simulation time 100988576 ps
CPU time 2.88 seconds
Started Aug 18 05:09:42 PM PDT 24
Finished Aug 18 05:09:44 PM PDT 24
Peak memory 216172 kb
Host smart-3f938e29-e360-4eee-bf31-4efa8b79c053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59070335 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.59070335
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4032473186
Short name T1117
Test name
Test status
Simulation time 117761964 ps
CPU time 2.66 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 215172 kb
Host smart-2216ba46-ab2b-44f2-9ad0-52788ee97492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032473186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4032473186
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3816459675
Short name T1064
Test name
Test status
Simulation time 36030317 ps
CPU time 0.69 seconds
Started Aug 18 05:09:30 PM PDT 24
Finished Aug 18 05:09:31 PM PDT 24
Peak memory 203852 kb
Host smart-f67a2ff5-7392-434d-a9bf-16a01025f23d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816459675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3816459675
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.851034695
Short name T1036
Test name
Test status
Simulation time 72144117 ps
CPU time 1.68 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:31 PM PDT 24
Peak memory 214920 kb
Host smart-aea67fa6-159d-4d0a-ba38-70de0607dfca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851034695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.851034695
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4157583264
Short name T110
Test name
Test status
Simulation time 173720474 ps
CPU time 3.98 seconds
Started Aug 18 05:09:30 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 215240 kb
Host smart-d6ed7a88-8772-463e-93da-29791a98808f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157583264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4157583264
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1052996473
Short name T174
Test name
Test status
Simulation time 795368975 ps
CPU time 13.79 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:43 PM PDT 24
Peak memory 215340 kb
Host smart-c5ac79b5-b02c-4471-b453-21044f86564d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052996473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1052996473
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3768670600
Short name T80
Test name
Test status
Simulation time 619393871 ps
CPU time 3.88 seconds
Started Aug 18 05:09:41 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 217984 kb
Host smart-4d471dae-f62b-4ba4-9a16-bf47a7e82b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768670600 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3768670600
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4155806201
Short name T1087
Test name
Test status
Simulation time 182647068 ps
CPU time 2.49 seconds
Started Aug 18 05:09:42 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 206844 kb
Host smart-5499ecab-09d3-4741-8564-05fd89233648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155806201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4155806201
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4169479641
Short name T1105
Test name
Test status
Simulation time 27560384 ps
CPU time 0.75 seconds
Started Aug 18 05:09:44 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 203664 kb
Host smart-509ef65b-b0ce-4a3c-9d2c-fbef2f581719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169479641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4169479641
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.315245403
Short name T1049
Test name
Test status
Simulation time 364058035 ps
CPU time 3.44 seconds
Started Aug 18 05:09:41 PM PDT 24
Finished Aug 18 05:09:44 PM PDT 24
Peak memory 215072 kb
Host smart-1cdcc02c-5aa5-46b9-97fa-61b9ff259dce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315245403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.315245403
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.264903893
Short name T1070
Test name
Test status
Simulation time 136812215 ps
CPU time 3.35 seconds
Started Aug 18 05:09:41 PM PDT 24
Finished Aug 18 05:09:44 PM PDT 24
Peak memory 215248 kb
Host smart-e2022853-4a8d-4631-a728-810f31feda83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264903893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.264903893
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3309949166
Short name T170
Test name
Test status
Simulation time 541035479 ps
CPU time 7.46 seconds
Started Aug 18 05:09:44 PM PDT 24
Finished Aug 18 05:09:51 PM PDT 24
Peak memory 215904 kb
Host smart-3648b86c-62f1-4bf5-95c0-e03d6f6b8746
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309949166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3309949166
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3206446041
Short name T156
Test name
Test status
Simulation time 61720732 ps
CPU time 1.78 seconds
Started Aug 18 05:09:46 PM PDT 24
Finished Aug 18 05:09:48 PM PDT 24
Peak memory 215368 kb
Host smart-f1e3967c-21ca-44ed-8741-b7bb370b5aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206446041 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3206446041
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.672624611
Short name T128
Test name
Test status
Simulation time 200071523 ps
CPU time 2.46 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:43 PM PDT 24
Peak memory 214900 kb
Host smart-8b97556f-ca36-44ce-acd4-4184717b5173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672624611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.672624611
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.909367497
Short name T1123
Test name
Test status
Simulation time 38572899 ps
CPU time 0.74 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 203632 kb
Host smart-8d31a599-3cbe-4c72-891b-abcaed5255b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909367497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.909367497
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1810508425
Short name T1018
Test name
Test status
Simulation time 50645793 ps
CPU time 1.83 seconds
Started Aug 18 05:09:38 PM PDT 24
Finished Aug 18 05:09:40 PM PDT 24
Peak memory 214936 kb
Host smart-15642e5f-c398-4cd6-bc6a-45cb9346b100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810508425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1810508425
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.163415782
Short name T118
Test name
Test status
Simulation time 675440473 ps
CPU time 4.82 seconds
Started Aug 18 05:09:39 PM PDT 24
Finished Aug 18 05:09:44 PM PDT 24
Peak memory 215244 kb
Host smart-ab3bbb0e-cbd3-4f6c-9c25-7e5ff724ec9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163415782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.163415782
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1695760328
Short name T1109
Test name
Test status
Simulation time 1492966944 ps
CPU time 7.56 seconds
Started Aug 18 05:09:45 PM PDT 24
Finished Aug 18 05:09:53 PM PDT 24
Peak memory 215676 kb
Host smart-faf6459b-88f2-4926-aee1-dad9a7129b34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695760328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1695760328
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1587347376
Short name T1107
Test name
Test status
Simulation time 219577737 ps
CPU time 2.02 seconds
Started Aug 18 05:09:39 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 216492 kb
Host smart-d9cff733-ed9f-4a8d-99bc-0fab1dcb04c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587347376 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1587347376
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.266471703
Short name T125
Test name
Test status
Simulation time 21035104 ps
CPU time 1.3 seconds
Started Aug 18 05:09:44 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 215036 kb
Host smart-e4d43767-c8e3-44b7-aff0-7707d4d407ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266471703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.266471703
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3981444314
Short name T1068
Test name
Test status
Simulation time 12222160 ps
CPU time 0.72 seconds
Started Aug 18 05:09:41 PM PDT 24
Finished Aug 18 05:09:42 PM PDT 24
Peak memory 204000 kb
Host smart-cadf68de-6b7b-49bd-be00-137604130307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981444314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3981444314
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3860192767
Short name T1101
Test name
Test status
Simulation time 155002012 ps
CPU time 4.48 seconds
Started Aug 18 05:09:39 PM PDT 24
Finished Aug 18 05:09:44 PM PDT 24
Peak memory 214936 kb
Host smart-489eacfc-dfae-483c-a7b6-ee0b6393d889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860192767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3860192767
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4081806926
Short name T1127
Test name
Test status
Simulation time 1254427964 ps
CPU time 5.72 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:46 PM PDT 24
Peak memory 215244 kb
Host smart-3951aed1-957a-40b0-abad-ea720ba45be4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081806926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4081806926
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4244287450
Short name T178
Test name
Test status
Simulation time 1204950456 ps
CPU time 19.17 seconds
Started Aug 18 05:09:44 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 215184 kb
Host smart-cc06ed8c-02ae-4cca-82fa-5154e5c4bd52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244287450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4244287450
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2348859294
Short name T120
Test name
Test status
Simulation time 393888236 ps
CPU time 2.8 seconds
Started Aug 18 05:09:42 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 216864 kb
Host smart-e38099c3-6dc5-4259-839a-20daac22143a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348859294 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2348859294
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1954882159
Short name T155
Test name
Test status
Simulation time 357160457 ps
CPU time 2.45 seconds
Started Aug 18 05:09:46 PM PDT 24
Finished Aug 18 05:09:49 PM PDT 24
Peak memory 215040 kb
Host smart-bd0e9bdc-f8af-421e-ac0a-3271c5de1ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954882159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1954882159
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.201721287
Short name T1114
Test name
Test status
Simulation time 38568896 ps
CPU time 0.7 seconds
Started Aug 18 05:09:46 PM PDT 24
Finished Aug 18 05:09:47 PM PDT 24
Peak memory 203720 kb
Host smart-3b6baf8f-2c84-4607-984b-95209ce57785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201721287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.201721287
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2557269475
Short name T1075
Test name
Test status
Simulation time 230981802 ps
CPU time 3.03 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:43 PM PDT 24
Peak memory 214928 kb
Host smart-b412b5f7-d80f-40ab-b95d-cb270e27aa03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557269475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2557269475
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3548803200
Short name T107
Test name
Test status
Simulation time 764807586 ps
CPU time 5.11 seconds
Started Aug 18 05:09:46 PM PDT 24
Finished Aug 18 05:09:52 PM PDT 24
Peak memory 215244 kb
Host smart-826ec8c0-34cd-433b-9219-20b5d0134cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548803200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3548803200
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2066198037
Short name T119
Test name
Test status
Simulation time 59238222 ps
CPU time 1.76 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 216048 kb
Host smart-2d0c973a-7aaa-475b-8aa8-29486551d48d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066198037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2066198037
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1242298590
Short name T135
Test name
Test status
Simulation time 88853666 ps
CPU time 2.55 seconds
Started Aug 18 05:09:39 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 215008 kb
Host smart-ad5e2d59-016c-4132-8928-5f971a0e2075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242298590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1242298590
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1314503278
Short name T1012
Test name
Test status
Simulation time 29825078 ps
CPU time 0.8 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 203772 kb
Host smart-675637db-bc00-4b11-becb-f01a4f7745c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314503278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1314503278
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1803485572
Short name T152
Test name
Test status
Simulation time 71299046 ps
CPU time 1.79 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:42 PM PDT 24
Peak memory 206684 kb
Host smart-2c80afc9-7803-460d-b8a8-1e33c4351ebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803485572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1803485572
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.928576730
Short name T1122
Test name
Test status
Simulation time 116688646 ps
CPU time 1.86 seconds
Started Aug 18 05:09:41 PM PDT 24
Finished Aug 18 05:09:43 PM PDT 24
Peak memory 215160 kb
Host smart-82057641-6da7-4fd3-8885-c476771806a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928576730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.928576730
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3995364671
Short name T1113
Test name
Test status
Simulation time 306271246 ps
CPU time 8.11 seconds
Started Aug 18 05:09:39 PM PDT 24
Finished Aug 18 05:09:47 PM PDT 24
Peak memory 215512 kb
Host smart-3f3bbddd-c1b8-4462-ab11-eb6dad8ef38d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995364671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3995364671
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2520824064
Short name T1065
Test name
Test status
Simulation time 97161918 ps
CPU time 1.63 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:56 PM PDT 24
Peak memory 215144 kb
Host smart-a002171c-7dd1-4848-890d-bd4e20292519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520824064 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2520824064
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3069153892
Short name T1073
Test name
Test status
Simulation time 468610408 ps
CPU time 2.81 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:43 PM PDT 24
Peak memory 215092 kb
Host smart-d28ffd5c-9308-4648-b95a-e52bb4c3e322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069153892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3069153892
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1001605926
Short name T1061
Test name
Test status
Simulation time 16883566 ps
CPU time 0.76 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 203564 kb
Host smart-1389c6f9-f3e3-41d4-9dd1-d67343a80d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001605926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1001605926
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1226063290
Short name T1099
Test name
Test status
Simulation time 235267852 ps
CPU time 4.01 seconds
Started Aug 18 05:09:42 PM PDT 24
Finished Aug 18 05:09:46 PM PDT 24
Peak memory 215080 kb
Host smart-d4a95bbc-7fce-4dd6-ae6a-b271675aafb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226063290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1226063290
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1969852265
Short name T112
Test name
Test status
Simulation time 43125110 ps
CPU time 2.84 seconds
Started Aug 18 05:09:42 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 215260 kb
Host smart-e39160e4-992c-4b59-999c-169889c58946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969852265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1969852265
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3489460717
Short name T1104
Test name
Test status
Simulation time 1879394805 ps
CPU time 14.75 seconds
Started Aug 18 05:09:40 PM PDT 24
Finished Aug 18 05:09:55 PM PDT 24
Peak memory 215120 kb
Host smart-9881652d-2559-400f-893a-1f3810f0d738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489460717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3489460717
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3450132413
Short name T153
Test name
Test status
Simulation time 74550521 ps
CPU time 1.92 seconds
Started Aug 18 05:09:55 PM PDT 24
Finished Aug 18 05:09:57 PM PDT 24
Peak memory 214964 kb
Host smart-64971375-def8-4145-94db-49a67294fa06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450132413 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3450132413
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2802063446
Short name T1088
Test name
Test status
Simulation time 91446350 ps
CPU time 2.44 seconds
Started Aug 18 05:09:53 PM PDT 24
Finished Aug 18 05:09:56 PM PDT 24
Peak memory 214960 kb
Host smart-40bcaeab-97d0-41cf-a691-458a16bdc33c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802063446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2802063446
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3223495937
Short name T1097
Test name
Test status
Simulation time 12538703 ps
CPU time 0.72 seconds
Started Aug 18 05:09:53 PM PDT 24
Finished Aug 18 05:09:54 PM PDT 24
Peak memory 203948 kb
Host smart-9fb801c8-3208-4c41-bcc6-b774a08d341b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223495937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3223495937
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2674878370
Short name T1115
Test name
Test status
Simulation time 46642343 ps
CPU time 2.91 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:57 PM PDT 24
Peak memory 214936 kb
Host smart-859cd2b1-4001-40ca-aea4-b647a242a8c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674878370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2674878370
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2895067454
Short name T1077
Test name
Test status
Simulation time 109318007 ps
CPU time 4.18 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:58 PM PDT 24
Peak memory 215224 kb
Host smart-fe876d59-1b3f-4ca1-9254-e2235eafbb59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895067454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2895067454
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3124134516
Short name T176
Test name
Test status
Simulation time 920653092 ps
CPU time 13.73 seconds
Started Aug 18 05:09:55 PM PDT 24
Finished Aug 18 05:10:08 PM PDT 24
Peak memory 215264 kb
Host smart-076bb27b-3c11-4f69-b8cc-5ede043f3a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124134516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3124134516
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.378986623
Short name T1090
Test name
Test status
Simulation time 56407305 ps
CPU time 3.93 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:58 PM PDT 24
Peak memory 218112 kb
Host smart-67628ab3-838c-4717-bb54-76f0b061bd8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378986623 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.378986623
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2266936780
Short name T1093
Test name
Test status
Simulation time 259341927 ps
CPU time 2.13 seconds
Started Aug 18 05:09:55 PM PDT 24
Finished Aug 18 05:09:57 PM PDT 24
Peak memory 215040 kb
Host smart-ffb2b4f0-fe35-4e05-99d0-3377139c431c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266936780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2266936780
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2547845748
Short name T1085
Test name
Test status
Simulation time 24558004 ps
CPU time 0.76 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:55 PM PDT 24
Peak memory 204064 kb
Host smart-9b5f9ae3-6ce6-4fcd-b062-091b21fe36e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547845748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2547845748
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1808249812
Short name T1044
Test name
Test status
Simulation time 136896493 ps
CPU time 1.9 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:56 PM PDT 24
Peak memory 206864 kb
Host smart-705bb0a6-1251-464e-8673-7dc4a7cbb203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808249812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1808249812
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1131697424
Short name T1047
Test name
Test status
Simulation time 120767239 ps
CPU time 2.44 seconds
Started Aug 18 05:09:53 PM PDT 24
Finished Aug 18 05:09:56 PM PDT 24
Peak memory 215156 kb
Host smart-4af5c9c0-57fb-415a-9373-307637bb7e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131697424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1131697424
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1158643403
Short name T172
Test name
Test status
Simulation time 1601067114 ps
CPU time 6.48 seconds
Started Aug 18 05:09:55 PM PDT 24
Finished Aug 18 05:10:01 PM PDT 24
Peak memory 214980 kb
Host smart-927f22f9-7c9c-4e2b-ac7e-12c79f8c8310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158643403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1158643403
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1516438281
Short name T1094
Test name
Test status
Simulation time 442332936 ps
CPU time 8.09 seconds
Started Aug 18 05:09:09 PM PDT 24
Finished Aug 18 05:09:18 PM PDT 24
Peak memory 206648 kb
Host smart-19c7bc1e-42de-4281-9832-716341cca2fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516438281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1516438281
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3888556547
Short name T1009
Test name
Test status
Simulation time 1208863290 ps
CPU time 14.43 seconds
Started Aug 18 05:09:12 PM PDT 24
Finished Aug 18 05:09:26 PM PDT 24
Peak memory 206952 kb
Host smart-65188922-167d-4ac0-9ba0-00ca5b2dd5aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888556547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3888556547
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2818818398
Short name T1118
Test name
Test status
Simulation time 150155812 ps
CPU time 1.39 seconds
Started Aug 18 05:09:12 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 206880 kb
Host smart-4baca56e-eb96-4987-897a-90be46b13cab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818818398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2818818398
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2583255941
Short name T1048
Test name
Test status
Simulation time 209600178 ps
CPU time 1.77 seconds
Started Aug 18 05:09:11 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 215168 kb
Host smart-9f3b1db6-51e6-4775-9953-639a45606930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583255941 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2583255941
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1552747108
Short name T124
Test name
Test status
Simulation time 86894192 ps
CPU time 2.64 seconds
Started Aug 18 05:09:12 PM PDT 24
Finished Aug 18 05:09:15 PM PDT 24
Peak memory 215008 kb
Host smart-ca3ec614-e451-429f-899b-92f214ff979c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552747108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
552747108
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.948808140
Short name T1020
Test name
Test status
Simulation time 14581705 ps
CPU time 0.77 seconds
Started Aug 18 05:09:01 PM PDT 24
Finished Aug 18 05:09:02 PM PDT 24
Peak memory 203640 kb
Host smart-a0521656-f749-4510-9f38-6df4324e45e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948808140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.948808140
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3484003661
Short name T129
Test name
Test status
Simulation time 92488061 ps
CPU time 1.98 seconds
Started Aug 18 05:09:11 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 215040 kb
Host smart-d8acabe7-72d5-4103-a818-db10ab5eaab5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484003661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3484003661
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.616613131
Short name T1043
Test name
Test status
Simulation time 15029762 ps
CPU time 0.66 seconds
Started Aug 18 05:09:00 PM PDT 24
Finished Aug 18 05:09:01 PM PDT 24
Peak memory 203528 kb
Host smart-cddc6a1f-6dd7-4eb5-bda8-19188f043a6f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616613131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.616613131
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.234939876
Short name T1111
Test name
Test status
Simulation time 251851240 ps
CPU time 3.99 seconds
Started Aug 18 05:09:12 PM PDT 24
Finished Aug 18 05:09:16 PM PDT 24
Peak memory 214936 kb
Host smart-1eb89885-e6c3-4e7d-b32b-eea7e3f1fc08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234939876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.234939876
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2374512363
Short name T1035
Test name
Test status
Simulation time 113161854 ps
CPU time 2.26 seconds
Started Aug 18 05:09:04 PM PDT 24
Finished Aug 18 05:09:06 PM PDT 24
Peak memory 216280 kb
Host smart-7dfbf8c9-be80-4e8a-b7d2-39a8d23ac13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374512363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
374512363
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.556065083
Short name T1131
Test name
Test status
Simulation time 1490498462 ps
CPU time 18.74 seconds
Started Aug 18 05:09:01 PM PDT 24
Finished Aug 18 05:09:19 PM PDT 24
Peak memory 215160 kb
Host smart-f8e62150-de83-455d-9197-47bc801d84fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556065083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.556065083
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.501464670
Short name T1059
Test name
Test status
Simulation time 59412542 ps
CPU time 0.74 seconds
Started Aug 18 05:09:54 PM PDT 24
Finished Aug 18 05:09:55 PM PDT 24
Peak memory 203648 kb
Host smart-520dca4e-0090-43a6-a003-66c90d085a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501464670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.501464670
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2943107418
Short name T1011
Test name
Test status
Simulation time 48500508 ps
CPU time 0.73 seconds
Started Aug 18 05:09:57 PM PDT 24
Finished Aug 18 05:09:58 PM PDT 24
Peak memory 203648 kb
Host smart-d8277f59-e62b-4f56-85ff-469b38a695ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943107418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2943107418
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4179111937
Short name T1089
Test name
Test status
Simulation time 82458652 ps
CPU time 0.74 seconds
Started Aug 18 05:09:55 PM PDT 24
Finished Aug 18 05:09:56 PM PDT 24
Peak memory 203592 kb
Host smart-08f2044d-5313-4d05-b218-077c9895acae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179111937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4179111937
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.271787384
Short name T1130
Test name
Test status
Simulation time 17848532 ps
CPU time 0.75 seconds
Started Aug 18 05:09:53 PM PDT 24
Finished Aug 18 05:09:54 PM PDT 24
Peak memory 203716 kb
Host smart-42507072-45ca-4107-9904-f096e65059d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271787384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.271787384
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3509667347
Short name T1041
Test name
Test status
Simulation time 88748062 ps
CPU time 0.73 seconds
Started Aug 18 05:10:02 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203724 kb
Host smart-56554931-4b3b-4980-a6df-8ddd275c25fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509667347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3509667347
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4287026516
Short name T1039
Test name
Test status
Simulation time 20529391 ps
CPU time 0.74 seconds
Started Aug 18 05:10:02 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203712 kb
Host smart-41c3058e-71da-4af3-bed7-1135953a5ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287026516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4287026516
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.161117454
Short name T1081
Test name
Test status
Simulation time 41415633 ps
CPU time 0.76 seconds
Started Aug 18 05:10:02 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203716 kb
Host smart-89744abb-79e4-4383-a341-4b1db2824a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161117454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.161117454
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.561436024
Short name T1119
Test name
Test status
Simulation time 47632033 ps
CPU time 0.72 seconds
Started Aug 18 05:10:06 PM PDT 24
Finished Aug 18 05:10:07 PM PDT 24
Peak memory 203732 kb
Host smart-28a257f0-27cc-490e-ae78-d4930cc42784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561436024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.561436024
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2951606185
Short name T1120
Test name
Test status
Simulation time 12508756 ps
CPU time 0.76 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203636 kb
Host smart-9cceb7ba-651b-4cd5-87b9-45d53b9eeef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951606185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2951606185
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2092317086
Short name T1062
Test name
Test status
Simulation time 70466875 ps
CPU time 0.77 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203876 kb
Host smart-ed5f6acf-23c3-4771-89b6-016ed099ca44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092317086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2092317086
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1311732640
Short name T1015
Test name
Test status
Simulation time 1276906488 ps
CPU time 8.61 seconds
Started Aug 18 05:09:10 PM PDT 24
Finished Aug 18 05:09:19 PM PDT 24
Peak memory 214888 kb
Host smart-11ba76e3-4b6e-4bfe-bb33-acfdedeae583
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311732640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1311732640
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2859803010
Short name T1110
Test name
Test status
Simulation time 2375924355 ps
CPU time 33.5 seconds
Started Aug 18 05:09:11 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 206868 kb
Host smart-97cd2cde-fcfd-49d0-82a4-2c18d9a45f06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859803010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2859803010
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3395860452
Short name T96
Test name
Test status
Simulation time 118707185 ps
CPU time 1.18 seconds
Started Aug 18 05:09:10 PM PDT 24
Finished Aug 18 05:09:11 PM PDT 24
Peak memory 206852 kb
Host smart-a0e9855f-d481-4349-afc2-b53bab06b248
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395860452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3395860452
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2081644495
Short name T1076
Test name
Test status
Simulation time 26627623 ps
CPU time 1.87 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:21 PM PDT 24
Peak memory 216176 kb
Host smart-6ffecef0-ae6d-4949-9db7-cdeb27c299db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081644495 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2081644495
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2385592046
Short name T150
Test name
Test status
Simulation time 50112305 ps
CPU time 1.39 seconds
Started Aug 18 05:09:12 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 214904 kb
Host smart-928508c0-4c61-4e82-8049-1b522f766089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385592046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
385592046
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1917210893
Short name T1017
Test name
Test status
Simulation time 37003731 ps
CPU time 0.73 seconds
Started Aug 18 05:09:10 PM PDT 24
Finished Aug 18 05:09:11 PM PDT 24
Peak memory 203600 kb
Host smart-ee8c5075-1276-4bd3-9102-f8e5d4d779aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917210893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
917210893
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2040562699
Short name T1080
Test name
Test status
Simulation time 34543388 ps
CPU time 1.27 seconds
Started Aug 18 05:09:12 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 214924 kb
Host smart-22984fc0-9bc9-47de-beb4-0fff5defbe48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040562699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2040562699
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3751335669
Short name T1021
Test name
Test status
Simulation time 16396681 ps
CPU time 0.65 seconds
Started Aug 18 05:09:10 PM PDT 24
Finished Aug 18 05:09:11 PM PDT 24
Peak memory 203500 kb
Host smart-354af014-b4b6-47e9-86cc-4764928d3bd9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751335669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3751335669
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.732108840
Short name T1025
Test name
Test status
Simulation time 119043787 ps
CPU time 2.06 seconds
Started Aug 18 05:09:18 PM PDT 24
Finished Aug 18 05:09:21 PM PDT 24
Peak memory 214908 kb
Host smart-76c77403-84c6-49b1-be10-eb1ff0de15bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732108840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.732108840
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.609844549
Short name T79
Test name
Test status
Simulation time 108813067 ps
CPU time 1.87 seconds
Started Aug 18 05:09:11 PM PDT 24
Finished Aug 18 05:09:13 PM PDT 24
Peak memory 215296 kb
Host smart-a2f11408-dcaa-4157-b262-0b40d8f4c26a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609844549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.609844549
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4122203672
Short name T173
Test name
Test status
Simulation time 346283870 ps
CPU time 6.95 seconds
Started Aug 18 05:09:13 PM PDT 24
Finished Aug 18 05:09:20 PM PDT 24
Peak memory 215244 kb
Host smart-b2e83daa-6794-4898-96d4-11ab892ecc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122203672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4122203672
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4000156446
Short name T1100
Test name
Test status
Simulation time 25732518 ps
CPU time 0.75 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203928 kb
Host smart-107e9f48-ffe5-40af-a981-a88c8ca733fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000156446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4000156446
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.414452245
Short name T1098
Test name
Test status
Simulation time 14737513 ps
CPU time 0.81 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203600 kb
Host smart-815c6a8b-95a4-470e-bee6-aa9305a9b646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414452245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.414452245
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.484755133
Short name T1128
Test name
Test status
Simulation time 43628144 ps
CPU time 0.74 seconds
Started Aug 18 05:10:01 PM PDT 24
Finished Aug 18 05:10:02 PM PDT 24
Peak memory 203652 kb
Host smart-c5306e64-0894-41ba-a4bb-f77370cdb569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484755133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.484755133
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3242113910
Short name T1053
Test name
Test status
Simulation time 86754758 ps
CPU time 0.78 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203676 kb
Host smart-59107dc8-d874-4dff-adff-0327309a6b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242113910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3242113910
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3436796757
Short name T1129
Test name
Test status
Simulation time 52952888 ps
CPU time 0.78 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203772 kb
Host smart-8f67b391-08da-4a00-985e-5499003e4dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436796757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3436796757
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.504437154
Short name T1106
Test name
Test status
Simulation time 23526312 ps
CPU time 0.73 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203508 kb
Host smart-13b9989e-c4d7-4e08-a188-5e695b7b3de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504437154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.504437154
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1131133667
Short name T1067
Test name
Test status
Simulation time 56629173 ps
CPU time 0.75 seconds
Started Aug 18 05:10:02 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203712 kb
Host smart-bd8b64a8-87b2-4800-8636-cc9d7dcfedd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131133667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1131133667
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.550173530
Short name T1031
Test name
Test status
Simulation time 45761217 ps
CPU time 0.71 seconds
Started Aug 18 05:10:06 PM PDT 24
Finished Aug 18 05:10:06 PM PDT 24
Peak memory 203996 kb
Host smart-643d8e8c-ebc2-4e8f-ada5-a3446b2393b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550173530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.550173530
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2282786109
Short name T1050
Test name
Test status
Simulation time 14551252 ps
CPU time 0.74 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 203624 kb
Host smart-5f5d8421-c45b-4c1f-a58f-41c5da36fa50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282786109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2282786109
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3438540230
Short name T1016
Test name
Test status
Simulation time 50092277 ps
CPU time 0.74 seconds
Started Aug 18 05:10:09 PM PDT 24
Finished Aug 18 05:10:10 PM PDT 24
Peak memory 203724 kb
Host smart-67df629f-1e54-4866-9000-080f2d97aff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438540230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3438540230
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4254978994
Short name T133
Test name
Test status
Simulation time 1238404049 ps
CPU time 8.27 seconds
Started Aug 18 05:09:20 PM PDT 24
Finished Aug 18 05:09:28 PM PDT 24
Peak memory 206680 kb
Host smart-0c901829-c6ce-4dd6-b53f-1cfdc6b71a3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254978994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4254978994
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1554169800
Short name T1008
Test name
Test status
Simulation time 888068717 ps
CPU time 12.49 seconds
Started Aug 18 05:09:20 PM PDT 24
Finished Aug 18 05:09:32 PM PDT 24
Peak memory 214940 kb
Host smart-4ed6f3c6-8b29-464b-b6db-5bcf49880760
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554169800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1554169800
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2195018860
Short name T95
Test name
Test status
Simulation time 32296252 ps
CPU time 1.23 seconds
Started Aug 18 05:09:21 PM PDT 24
Finished Aug 18 05:09:22 PM PDT 24
Peak memory 206828 kb
Host smart-0a015579-537a-442a-9f8a-63c039a51881
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195018860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2195018860
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2093006857
Short name T151
Test name
Test status
Simulation time 715415678 ps
CPU time 3.61 seconds
Started Aug 18 05:09:21 PM PDT 24
Finished Aug 18 05:09:24 PM PDT 24
Peak memory 217396 kb
Host smart-4b2e234b-6bf0-45ea-86d5-bef9b9191c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093006857 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2093006857
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3564595975
Short name T143
Test name
Test status
Simulation time 513788888 ps
CPU time 2.47 seconds
Started Aug 18 05:09:20 PM PDT 24
Finished Aug 18 05:09:22 PM PDT 24
Peak memory 215068 kb
Host smart-fac24f61-dabb-4ce4-8e8d-f90428dba1b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564595975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
564595975
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.44585993
Short name T1042
Test name
Test status
Simulation time 18862669 ps
CPU time 0.72 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:19 PM PDT 24
Peak memory 203600 kb
Host smart-1b242f83-a1f6-4fa0-8afd-d2e1a634b287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44585993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.44585993
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2117913280
Short name T1066
Test name
Test status
Simulation time 32096423 ps
CPU time 1.33 seconds
Started Aug 18 05:09:20 PM PDT 24
Finished Aug 18 05:09:21 PM PDT 24
Peak memory 215124 kb
Host smart-8d239a63-fb5b-4341-8d76-5d48fe5239dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117913280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2117913280
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3875611264
Short name T1116
Test name
Test status
Simulation time 21322720 ps
CPU time 0.67 seconds
Started Aug 18 05:09:21 PM PDT 24
Finished Aug 18 05:09:21 PM PDT 24
Peak memory 203532 kb
Host smart-d2fd984f-5ecd-4796-a24a-1be628432382
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875611264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3875611264
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2273920526
Short name T1069
Test name
Test status
Simulation time 161741663 ps
CPU time 2.67 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:22 PM PDT 24
Peak memory 215000 kb
Host smart-84c8c3b5-dda5-4e5f-9573-ceaede704c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273920526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2273920526
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4272439850
Short name T1079
Test name
Test status
Simulation time 315237979 ps
CPU time 5.85 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:25 PM PDT 24
Peak memory 215376 kb
Host smart-97f87da5-540b-4c55-a95a-287b4dc3dc84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272439850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
272439850
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1572106799
Short name T171
Test name
Test status
Simulation time 2433412607 ps
CPU time 19.8 seconds
Started Aug 18 05:09:21 PM PDT 24
Finished Aug 18 05:09:41 PM PDT 24
Peak memory 215140 kb
Host smart-818c7d41-49a6-4fa9-8e37-2507bb19ae58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572106799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1572106799
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2031696124
Short name T1046
Test name
Test status
Simulation time 16334269 ps
CPU time 0.78 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 203636 kb
Host smart-bce89a58-976d-4bce-b0d7-aa80cc0b612f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031696124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2031696124
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3782109570
Short name T1045
Test name
Test status
Simulation time 11204016 ps
CPU time 0.77 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203616 kb
Host smart-9303a356-acfb-4f63-8b68-044700bc95c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782109570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3782109570
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4096237382
Short name T1095
Test name
Test status
Simulation time 17957461 ps
CPU time 0.8 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203596 kb
Host smart-1060733e-e2df-4236-9021-603e70b1dd76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096237382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4096237382
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2365330952
Short name T1027
Test name
Test status
Simulation time 49398366 ps
CPU time 0.83 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 203712 kb
Host smart-a7020af1-72bb-48e3-bb8c-61552687da62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365330952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2365330952
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3671860009
Short name T1071
Test name
Test status
Simulation time 13240305 ps
CPU time 0.77 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 203904 kb
Host smart-41e8c9cf-45e9-48fa-ab4a-5ecf22fc256a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671860009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3671860009
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.201245787
Short name T1019
Test name
Test status
Simulation time 15271769 ps
CPU time 0.76 seconds
Started Aug 18 05:10:06 PM PDT 24
Finished Aug 18 05:10:07 PM PDT 24
Peak memory 203744 kb
Host smart-61fd4a2c-c741-49b1-a1b7-8cb6dba6b530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201245787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.201245787
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1135378267
Short name T1030
Test name
Test status
Simulation time 25446258 ps
CPU time 0.76 seconds
Started Aug 18 05:10:04 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203676 kb
Host smart-e09b8099-ac06-45d2-b7d8-f93eacb28490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135378267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1135378267
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3426534319
Short name T1108
Test name
Test status
Simulation time 15285187 ps
CPU time 0.79 seconds
Started Aug 18 05:10:03 PM PDT 24
Finished Aug 18 05:10:04 PM PDT 24
Peak memory 203620 kb
Host smart-ced841c1-5e4a-400f-86d1-1b081e47608b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426534319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3426534319
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1038315554
Short name T1010
Test name
Test status
Simulation time 13898307 ps
CPU time 0.75 seconds
Started Aug 18 05:10:05 PM PDT 24
Finished Aug 18 05:10:05 PM PDT 24
Peak memory 203612 kb
Host smart-dbe9e270-41c2-485f-86c0-841ed7257f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038315554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1038315554
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1102988154
Short name T1103
Test name
Test status
Simulation time 11595866 ps
CPU time 0.73 seconds
Started Aug 18 05:10:02 PM PDT 24
Finished Aug 18 05:10:03 PM PDT 24
Peak memory 203724 kb
Host smart-ff4f618a-44ed-4aa2-9ef3-3cb7849c0657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102988154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1102988154
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3809308401
Short name T117
Test name
Test status
Simulation time 53087060 ps
CPU time 3.28 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:23 PM PDT 24
Peak memory 217440 kb
Host smart-1c2efe86-067d-4cf8-a739-5225ba137dd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809308401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3809308401
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1880485561
Short name T1124
Test name
Test status
Simulation time 235700804 ps
CPU time 1.84 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:21 PM PDT 24
Peak memory 215084 kb
Host smart-371df502-7d31-4c5b-b503-8b896b69ab95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880485561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
880485561
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.548603220
Short name T1096
Test name
Test status
Simulation time 14468632 ps
CPU time 0.74 seconds
Started Aug 18 05:09:21 PM PDT 24
Finished Aug 18 05:09:22 PM PDT 24
Peak memory 203904 kb
Host smart-7bcf8500-adad-4369-87c7-4f1d7db69b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548603220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.548603220
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2818053901
Short name T1038
Test name
Test status
Simulation time 122785726 ps
CPU time 3.39 seconds
Started Aug 18 05:09:19 PM PDT 24
Finished Aug 18 05:09:23 PM PDT 24
Peak memory 215048 kb
Host smart-c2c298f9-89ef-4176-a3e1-bb131c162360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818053901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2818053901
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.556766859
Short name T109
Test name
Test status
Simulation time 1407984766 ps
CPU time 8.06 seconds
Started Aug 18 05:09:18 PM PDT 24
Finished Aug 18 05:09:26 PM PDT 24
Peak memory 215004 kb
Host smart-d94a88c5-9b84-4ef3-8856-a4e5d8cb41ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556766859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.556766859
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3888892589
Short name T1074
Test name
Test status
Simulation time 83560410 ps
CPU time 1.69 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:31 PM PDT 24
Peak memory 215092 kb
Host smart-1ff53cae-b7ee-41e0-9889-66ecc0dace8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888892589 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3888892589
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1855885695
Short name T1028
Test name
Test status
Simulation time 699810900 ps
CPU time 1.94 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:31 PM PDT 24
Peak memory 215020 kb
Host smart-690e67b8-41fa-423e-a7f0-01ef8d078818
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855885695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
855885695
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3024486512
Short name T1125
Test name
Test status
Simulation time 17749342 ps
CPU time 0.72 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:32 PM PDT 24
Peak memory 203620 kb
Host smart-6d2c0b51-8e64-459e-ad6c-9fa0db3c5fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024486512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
024486512
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4216787896
Short name T1026
Test name
Test status
Simulation time 119095485 ps
CPU time 3.99 seconds
Started Aug 18 05:09:30 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 215024 kb
Host smart-5d04381d-0cf3-4d43-98dd-3471a196f279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216787896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4216787896
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.311189600
Short name T1040
Test name
Test status
Simulation time 65162788 ps
CPU time 1.9 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 215260 kb
Host smart-2d067329-bbc1-4357-8d6a-0b72fdee608c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311189600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.311189600
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1322877479
Short name T1054
Test name
Test status
Simulation time 11141106214 ps
CPU time 25.91 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:55 PM PDT 24
Peak memory 215636 kb
Host smart-6670132b-4fa4-429a-8bd5-2a8080ae2456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322877479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1322877479
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2681875843
Short name T1091
Test name
Test status
Simulation time 179791941 ps
CPU time 1.66 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:32 PM PDT 24
Peak memory 215124 kb
Host smart-d8fbe9ec-79c0-46d0-8db7-7a605a8eea2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681875843 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2681875843
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1197814451
Short name T1102
Test name
Test status
Simulation time 91428165 ps
CPU time 2.66 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 214864 kb
Host smart-98911c55-b448-4b94-b00f-df0e91c7b2d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197814451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
197814451
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.398895582
Short name T1013
Test name
Test status
Simulation time 29847326 ps
CPU time 0.73 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:30 PM PDT 24
Peak memory 204048 kb
Host smart-f263ff42-f509-4b45-aa54-421c895633ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398895582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.398895582
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.68552034
Short name T1055
Test name
Test status
Simulation time 59740065 ps
CPU time 4.11 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:35 PM PDT 24
Peak memory 215056 kb
Host smart-319b3613-7263-427a-a201-63e553f422bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68552034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi
_device_same_csr_outstanding.68552034
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1305628653
Short name T1052
Test name
Test status
Simulation time 1121248034 ps
CPU time 23.17 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:54 PM PDT 24
Peak memory 215164 kb
Host smart-875f47b2-0a47-42f9-80cc-bbc04342974e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305628653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1305628653
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3902470602
Short name T1056
Test name
Test status
Simulation time 154138662 ps
CPU time 2.91 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 216096 kb
Host smart-6223bfc3-19bd-4feb-825f-0c7160a2e1d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902470602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3902470602
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1298670376
Short name T1037
Test name
Test status
Simulation time 29828558 ps
CPU time 1.69 seconds
Started Aug 18 05:09:32 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 215012 kb
Host smart-87aecd1f-1be4-4e74-8d42-ad459a39a1f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298670376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
298670376
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3590467942
Short name T1083
Test name
Test status
Simulation time 19313302 ps
CPU time 0.77 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:32 PM PDT 24
Peak memory 203648 kb
Host smart-02d36372-7f9e-47e5-a8d9-c5e1e7f6da7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590467942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
590467942
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1830406193
Short name T1029
Test name
Test status
Simulation time 90572583 ps
CPU time 3.62 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 214996 kb
Host smart-a0197c9c-5199-4a06-90c1-8572ab7a835e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830406193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1830406193
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3972153600
Short name T116
Test name
Test status
Simulation time 760848291 ps
CPU time 3.17 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:35 PM PDT 24
Peak memory 215320 kb
Host smart-eaa1d7ba-2c9d-4513-9526-5df49c762dab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972153600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
972153600
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.256937435
Short name T175
Test name
Test status
Simulation time 1579415236 ps
CPU time 12.17 seconds
Started Aug 18 05:09:32 PM PDT 24
Finished Aug 18 05:09:45 PM PDT 24
Peak memory 215068 kb
Host smart-5e8464a9-e478-45c4-8a31-799ff7499076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256937435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.256937435
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2582951783
Short name T1033
Test name
Test status
Simulation time 50575904 ps
CPU time 1.62 seconds
Started Aug 18 05:09:29 PM PDT 24
Finished Aug 18 05:09:31 PM PDT 24
Peak memory 214972 kb
Host smart-689f8d36-cbe3-4726-b3ad-b6ad6726af40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582951783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2582951783
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.189409242
Short name T134
Test name
Test status
Simulation time 27029187 ps
CPU time 1.93 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 214976 kb
Host smart-facf0ed9-a42d-47a4-a518-bad5e12f5587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189409242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.189409242
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2898464371
Short name T1092
Test name
Test status
Simulation time 20849499 ps
CPU time 0.73 seconds
Started Aug 18 05:09:31 PM PDT 24
Finished Aug 18 05:09:32 PM PDT 24
Peak memory 203660 kb
Host smart-dcbfc3b9-51bd-4edf-819a-5887986677a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898464371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
898464371
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2036857398
Short name T1072
Test name
Test status
Simulation time 150700435 ps
CPU time 3.94 seconds
Started Aug 18 05:09:30 PM PDT 24
Finished Aug 18 05:09:34 PM PDT 24
Peak memory 215028 kb
Host smart-c1409858-b7c3-4f39-9ae7-a356dbc14cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036857398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2036857398
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3467446570
Short name T1078
Test name
Test status
Simulation time 253885019 ps
CPU time 3.81 seconds
Started Aug 18 05:09:30 PM PDT 24
Finished Aug 18 05:09:33 PM PDT 24
Peak memory 215132 kb
Host smart-f8cbbd65-a672-4c12-b441-caff58f0f14c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467446570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
467446570
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2258696307
Short name T538
Test name
Test status
Simulation time 14545380 ps
CPU time 0.74 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:23 PM PDT 24
Peak memory 205696 kb
Host smart-80cfd2e3-b9de-4547-a922-0d92028a7b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258696307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
258696307
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.460652312
Short name T469
Test name
Test status
Simulation time 330284265 ps
CPU time 2.54 seconds
Started Aug 18 04:53:16 PM PDT 24
Finished Aug 18 04:53:19 PM PDT 24
Peak memory 233428 kb
Host smart-20777537-f152-4c68-afff-a911d0d2a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460652312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.460652312
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1621418351
Short name T675
Test name
Test status
Simulation time 62074659 ps
CPU time 0.75 seconds
Started Aug 18 04:53:17 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 216572 kb
Host smart-c0580c8c-afb6-472d-9ae4-6a38638ea0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621418351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1621418351
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3831921
Short name T224
Test name
Test status
Simulation time 11338018737 ps
CPU time 85.88 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:54:40 PM PDT 24
Peak memory 266572 kb
Host smart-c55f75da-0e7b-4af1-aff6-e338664d5cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.3831921
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4197754814
Short name T47
Test name
Test status
Simulation time 465998635 ps
CPU time 5 seconds
Started Aug 18 04:53:15 PM PDT 24
Finished Aug 18 04:53:20 PM PDT 24
Peak memory 241768 kb
Host smart-d3600957-8a7d-406c-a103-e288e9ed759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197754814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4197754814
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3358067302
Short name T15
Test name
Test status
Simulation time 3895508117 ps
CPU time 21.6 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:53:35 PM PDT 24
Peak memory 233696 kb
Host smart-405d1d44-f637-4032-92d6-b7c57d1f25bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358067302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3358067302
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4127447273
Short name T715
Test name
Test status
Simulation time 1401579364 ps
CPU time 4.01 seconds
Started Aug 18 04:53:15 PM PDT 24
Finished Aug 18 04:53:19 PM PDT 24
Peak memory 233548 kb
Host smart-ae58294f-2df7-4b61-b857-86d8ef589b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127447273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4127447273
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3343501941
Short name T437
Test name
Test status
Simulation time 672430924 ps
CPU time 7.32 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:21 PM PDT 24
Peak memory 225340 kb
Host smart-17a5411b-821c-4f30-8f59-0cd9881527d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343501941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3343501941
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1560607964
Short name T614
Test name
Test status
Simulation time 166522409 ps
CPU time 4.26 seconds
Started Aug 18 04:53:16 PM PDT 24
Finished Aug 18 04:53:20 PM PDT 24
Peak memory 233540 kb
Host smart-37af2c38-5590-4f5c-bec4-4cfeb6ee54aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560607964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1560607964
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3859641952
Short name T927
Test name
Test status
Simulation time 337769001 ps
CPU time 3.29 seconds
Started Aug 18 04:53:13 PM PDT 24
Finished Aug 18 04:53:16 PM PDT 24
Peak memory 225400 kb
Host smart-38abd2ba-0a0d-4020-a03f-636dd96fd19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859641952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3859641952
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1557858065
Short name T883
Test name
Test status
Simulation time 370022937 ps
CPU time 3.8 seconds
Started Aug 18 04:53:17 PM PDT 24
Finished Aug 18 04:53:21 PM PDT 24
Peak memory 224392 kb
Host smart-717a48ad-c55c-4efb-9ba0-9bcfaf918ce1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1557858065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1557858065
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3600878652
Short name T322
Test name
Test status
Simulation time 11946810201 ps
CPU time 78.74 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 250884 kb
Host smart-5d6a91d9-6e4b-4408-a197-51adf62b15c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600878652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3600878652
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3962617606
Short name T660
Test name
Test status
Simulation time 9718371489 ps
CPU time 24.68 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:39 PM PDT 24
Peak memory 217516 kb
Host smart-bf5a5cfe-8fbd-475d-ba46-9dca7491e87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962617606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3962617606
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4158246065
Short name T428
Test name
Test status
Simulation time 20695083126 ps
CPU time 9.46 seconds
Started Aug 18 04:53:17 PM PDT 24
Finished Aug 18 04:53:26 PM PDT 24
Peak memory 217316 kb
Host smart-39099c46-104e-490f-91b7-54c4ac65c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158246065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4158246065
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3770891669
Short name T553
Test name
Test status
Simulation time 410419035 ps
CPU time 3.56 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:18 PM PDT 24
Peak memory 217020 kb
Host smart-dcdb66a8-0aed-4ac9-a01e-842825c2c657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770891669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3770891669
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1241029339
Short name T694
Test name
Test status
Simulation time 146176904 ps
CPU time 0.85 seconds
Started Aug 18 04:53:14 PM PDT 24
Finished Aug 18 04:53:15 PM PDT 24
Peak memory 206648 kb
Host smart-1074fc7a-67c9-4082-9138-879494da71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241029339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1241029339
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.899395720
Short name T489
Test name
Test status
Simulation time 218411542 ps
CPU time 2.41 seconds
Started Aug 18 04:53:17 PM PDT 24
Finished Aug 18 04:53:19 PM PDT 24
Peak memory 225052 kb
Host smart-065853f9-7e77-4cea-9988-c6a42542952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899395720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.899395720
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.63609026
Short name T594
Test name
Test status
Simulation time 45575119 ps
CPU time 0.69 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 206308 kb
Host smart-3260e138-fba7-4a04-a3b5-6c716f02376e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63609026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.63609026
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.899759333
Short name T870
Test name
Test status
Simulation time 1070485041 ps
CPU time 11.66 seconds
Started Aug 18 04:53:25 PM PDT 24
Finished Aug 18 04:53:37 PM PDT 24
Peak memory 225296 kb
Host smart-24359dce-4f59-4762-b81f-f3717b6dd874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899759333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.899759333
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1019539893
Short name T373
Test name
Test status
Simulation time 20644000 ps
CPU time 0.76 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 207452 kb
Host smart-cd343591-57e7-4e3e-944b-413a46837614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019539893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1019539893
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.500979113
Short name T825
Test name
Test status
Simulation time 26095607672 ps
CPU time 81.79 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:54:44 PM PDT 24
Peak memory 233636 kb
Host smart-d039f3b7-24ec-489a-9b44-df2aaa0383d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500979113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.500979113
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1383634051
Short name T834
Test name
Test status
Simulation time 105053715479 ps
CPU time 263.22 seconds
Started Aug 18 04:53:25 PM PDT 24
Finished Aug 18 04:57:48 PM PDT 24
Peak memory 258276 kb
Host smart-a71be9f3-bf5d-4b48-bc2b-3a5abd3ac50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383634051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1383634051
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.940171816
Short name T55
Test name
Test status
Simulation time 87715888847 ps
CPU time 340.55 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 250016 kb
Host smart-276ba5d4-8c74-43f5-a35e-82a5b0d0c331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940171816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
940171816
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1482701757
Short name T887
Test name
Test status
Simulation time 445687474 ps
CPU time 8.13 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:30 PM PDT 24
Peak memory 233500 kb
Host smart-135feda1-28f3-4622-b917-bf212687e344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482701757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1482701757
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2411879943
Short name T487
Test name
Test status
Simulation time 790197749 ps
CPU time 6.79 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:30 PM PDT 24
Peak memory 225576 kb
Host smart-0a01c17e-028f-42b4-a0dc-c15cf9a2c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411879943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2411879943
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1560622543
Short name T829
Test name
Test status
Simulation time 702584999 ps
CPU time 3.95 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:28 PM PDT 24
Peak memory 233568 kb
Host smart-0854ef20-162b-44dc-9c75-24ba9f3b532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560622543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1560622543
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3158347261
Short name T227
Test name
Test status
Simulation time 5035022028 ps
CPU time 10.43 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:33 PM PDT 24
Peak memory 230880 kb
Host smart-a86fa755-c627-4c3c-b600-2909a75fdd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158347261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3158347261
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1138801213
Short name T374
Test name
Test status
Simulation time 1002941301 ps
CPU time 3.32 seconds
Started Aug 18 04:53:23 PM PDT 24
Finished Aug 18 04:53:26 PM PDT 24
Peak memory 219924 kb
Host smart-95b4f601-0259-4dd7-ae34-3838140f37e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138801213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1138801213
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.997182189
Short name T83
Test name
Test status
Simulation time 311631740 ps
CPU time 1.14 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:23 PM PDT 24
Peak memory 236548 kb
Host smart-ad6232c7-a368-4725-a550-d14c99756ca7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997182189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.997182189
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.604731776
Short name T35
Test name
Test status
Simulation time 66444137 ps
CPU time 1.01 seconds
Started Aug 18 04:53:23 PM PDT 24
Finished Aug 18 04:53:24 PM PDT 24
Peak memory 208460 kb
Host smart-c5e9d53a-f166-48f6-b32c-205bc68276c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604731776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.604731776
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.322949911
Short name T992
Test name
Test status
Simulation time 4379331751 ps
CPU time 14.46 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:39 PM PDT 24
Peak memory 217272 kb
Host smart-64ff1424-05b8-4ddb-9f17-16c067e4e92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322949911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.322949911
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.358247071
Short name T364
Test name
Test status
Simulation time 1835426167 ps
CPU time 6.02 seconds
Started Aug 18 04:53:23 PM PDT 24
Finished Aug 18 04:53:29 PM PDT 24
Peak memory 217060 kb
Host smart-d1bded87-7ff7-47c2-a69a-a9f96771ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358247071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.358247071
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2844349977
Short name T510
Test name
Test status
Simulation time 165273078 ps
CPU time 1.97 seconds
Started Aug 18 04:53:22 PM PDT 24
Finished Aug 18 04:53:24 PM PDT 24
Peak memory 217148 kb
Host smart-0bf2fa9d-bcdd-44d9-8551-7f1e1ca3aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844349977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2844349977
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2578599384
Short name T649
Test name
Test status
Simulation time 80394863 ps
CPU time 0.92 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:25 PM PDT 24
Peak memory 206808 kb
Host smart-39ffac50-bd24-434c-a1d4-f13fc08dcd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578599384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2578599384
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2607819205
Short name T545
Test name
Test status
Simulation time 2985471670 ps
CPU time 12.99 seconds
Started Aug 18 04:53:24 PM PDT 24
Finished Aug 18 04:53:38 PM PDT 24
Peak memory 233656 kb
Host smart-10eb397a-9b4f-4d03-abe2-e37af9d8382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607819205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2607819205
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2787399658
Short name T624
Test name
Test status
Simulation time 190140770 ps
CPU time 3.39 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 225364 kb
Host smart-d9f316e5-7b22-4332-b3e0-74c4eda70620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787399658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2787399658
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1815519784
Short name T402
Test name
Test status
Simulation time 135744540 ps
CPU time 0.77 seconds
Started Aug 18 04:54:28 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 207472 kb
Host smart-76cee680-8e49-4407-b476-49d0d9d39a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815519784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1815519784
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2438166283
Short name T265
Test name
Test status
Simulation time 174858921277 ps
CPU time 446.68 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 05:01:53 PM PDT 24
Peak memory 263424 kb
Host smart-7863beed-fa3e-44b3-960f-f725400eb406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438166283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2438166283
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2225220646
Short name T666
Test name
Test status
Simulation time 1386605584 ps
CPU time 8.64 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:34 PM PDT 24
Peak memory 225368 kb
Host smart-4acb4a9d-b94e-48b7-aaf0-8e817c10d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225220646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2225220646
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.240024254
Short name T591
Test name
Test status
Simulation time 217452980 ps
CPU time 3.24 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:28 PM PDT 24
Peak memory 233560 kb
Host smart-ae18086c-335e-4078-bfe5-d4d1525f3ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240024254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.240024254
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1406255865
Short name T223
Test name
Test status
Simulation time 1553069282 ps
CPU time 4.59 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 233452 kb
Host smart-a3cf0c6f-7b37-4923-bb82-1e4547e94284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406255865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1406255865
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4048259846
Short name T88
Test name
Test status
Simulation time 51419203348 ps
CPU time 55.2 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:55:21 PM PDT 24
Peak memory 241760 kb
Host smart-abec28d6-9909-4785-9fca-485fbda4a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048259846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4048259846
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.883620022
Short name T54
Test name
Test status
Simulation time 34450801307 ps
CPU time 47.53 seconds
Started Aug 18 04:54:27 PM PDT 24
Finished Aug 18 04:55:14 PM PDT 24
Peak memory 237456 kb
Host smart-1910ac3a-04c8-473b-9b17-a26ca18178e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883620022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.883620022
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3412106932
Short name T872
Test name
Test status
Simulation time 1115484033 ps
CPU time 12.56 seconds
Started Aug 18 04:54:30 PM PDT 24
Finished Aug 18 04:54:42 PM PDT 24
Peak memory 223528 kb
Host smart-f9c2ca76-6a67-4324-a3b0-42f31d0cdc38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3412106932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3412106932
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.458336405
Short name T894
Test name
Test status
Simulation time 8286659833 ps
CPU time 39.52 seconds
Started Aug 18 04:54:28 PM PDT 24
Finished Aug 18 04:55:08 PM PDT 24
Peak memory 241892 kb
Host smart-aba8ba90-0de5-4e9f-b0ae-5b9f04078644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458336405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.458336405
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3256901943
Short name T313
Test name
Test status
Simulation time 321613374 ps
CPU time 2.16 seconds
Started Aug 18 04:54:27 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 218296 kb
Host smart-00da35a4-e15e-417c-a890-28db6f69f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256901943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3256901943
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3917325923
Short name T679
Test name
Test status
Simulation time 4132363345 ps
CPU time 15.04 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:40 PM PDT 24
Peak memory 217228 kb
Host smart-7ebdf58f-c7af-44e2-8a3c-7838de035152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917325923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3917325923
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.738128931
Short name T410
Test name
Test status
Simulation time 57096330 ps
CPU time 1.28 seconds
Started Aug 18 04:54:28 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 217144 kb
Host smart-927950d6-54d2-438a-93a1-fd04efa61738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738128931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.738128931
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1641527961
Short name T632
Test name
Test status
Simulation time 21109960 ps
CPU time 0.74 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:26 PM PDT 24
Peak memory 206768 kb
Host smart-cf971728-269a-4bca-b896-ad2718897837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641527961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1641527961
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2495288025
Short name T546
Test name
Test status
Simulation time 916535977 ps
CPU time 6.77 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 241744 kb
Host smart-f8864ba0-a6dd-4fa5-963f-ecdd1145d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495288025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2495288025
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1615888547
Short name T706
Test name
Test status
Simulation time 44371437 ps
CPU time 0.74 seconds
Started Aug 18 04:54:34 PM PDT 24
Finished Aug 18 04:54:35 PM PDT 24
Peak memory 205688 kb
Host smart-4f846400-5291-495e-a028-86f7daa6dba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615888547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1615888547
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2514251235
Short name T740
Test name
Test status
Simulation time 3036184627 ps
CPU time 8.54 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 233576 kb
Host smart-13173ba2-3982-4f6e-9441-c208ccf5ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514251235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2514251235
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3394209884
Short name T506
Test name
Test status
Simulation time 28792769 ps
CPU time 0.79 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:27 PM PDT 24
Peak memory 207356 kb
Host smart-d53d7eb4-c442-4faa-93bd-02780bea6327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394209884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3394209884
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.283593223
Short name T71
Test name
Test status
Simulation time 47942358301 ps
CPU time 81.75 seconds
Started Aug 18 04:54:43 PM PDT 24
Finished Aug 18 04:56:05 PM PDT 24
Peak memory 265416 kb
Host smart-8788950e-3cce-48fb-8e73-d0744f3b8443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283593223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.283593223
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4178849520
Short name T214
Test name
Test status
Simulation time 8539898594 ps
CPU time 80.95 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:55:59 PM PDT 24
Peak memory 249488 kb
Host smart-79d26039-33c2-46d8-8cec-04694636ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178849520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4178849520
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2088438840
Short name T640
Test name
Test status
Simulation time 83091217414 ps
CPU time 218.98 seconds
Started Aug 18 04:54:34 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 253036 kb
Host smart-a0960a82-f11e-4b83-9f0a-1a38ced7a065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088438840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2088438840
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3647649239
Short name T977
Test name
Test status
Simulation time 250146387 ps
CPU time 3.04 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 225368 kb
Host smart-06ab66b7-e27f-427b-adf7-8242bf7d6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647649239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3647649239
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.149408110
Short name T10
Test name
Test status
Simulation time 4178005097 ps
CPU time 27.78 seconds
Started Aug 18 04:54:36 PM PDT 24
Finished Aug 18 04:55:04 PM PDT 24
Peak memory 225400 kb
Host smart-c735df2a-67e8-413c-a3f6-88b4912e7e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149408110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.149408110
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3465429378
Short name T838
Test name
Test status
Simulation time 342267871 ps
CPU time 4.9 seconds
Started Aug 18 04:54:33 PM PDT 24
Finished Aug 18 04:54:38 PM PDT 24
Peak memory 233620 kb
Host smart-7dedd4d3-f19e-4b14-a783-271777392002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465429378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3465429378
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3085525143
Short name T763
Test name
Test status
Simulation time 5248296903 ps
CPU time 56.12 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:55:23 PM PDT 24
Peak memory 233652 kb
Host smart-6507db48-efae-4338-bf60-62ea8420fac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085525143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3085525143
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.39838365
Short name T272
Test name
Test status
Simulation time 6870765335 ps
CPU time 11.4 seconds
Started Aug 18 04:54:32 PM PDT 24
Finished Aug 18 04:54:44 PM PDT 24
Peak memory 225448 kb
Host smart-d2433a3c-d3cb-4b66-86ce-1fe9c60b1a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39838365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.39838365
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2553755445
Short name T783
Test name
Test status
Simulation time 1930125202 ps
CPU time 6.87 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 235860 kb
Host smart-108b8ddb-ae53-4926-82c3-0e33b03792e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553755445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2553755445
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.880721303
Short name T48
Test name
Test status
Simulation time 1721662948 ps
CPU time 11.18 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:54:56 PM PDT 24
Peak memory 222928 kb
Host smart-aa8ad540-f156-4e26-85fe-d0a6e61f3800
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=880721303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.880721303
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2430292722
Short name T75
Test name
Test status
Simulation time 3350180387 ps
CPU time 12.18 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:38 PM PDT 24
Peak memory 217768 kb
Host smart-b82ae17d-aaca-4044-acbc-fe29d6091f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430292722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2430292722
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3212859258
Short name T427
Test name
Test status
Simulation time 14356801656 ps
CPU time 13.31 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:38 PM PDT 24
Peak memory 218272 kb
Host smart-19aba919-3f23-49a0-8110-ee075c076748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212859258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3212859258
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1391333550
Short name T391
Test name
Test status
Simulation time 634538713 ps
CPU time 6.37 seconds
Started Aug 18 04:54:27 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 217112 kb
Host smart-e6194365-aa53-467f-908f-34240529a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391333550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1391333550
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.209214261
Short name T416
Test name
Test status
Simulation time 23890638 ps
CPU time 0.74 seconds
Started Aug 18 04:54:27 PM PDT 24
Finished Aug 18 04:54:28 PM PDT 24
Peak memory 206808 kb
Host smart-bbf4cd57-5f30-4f24-8ff6-71d14afb589a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209214261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.209214261
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3534708251
Short name T246
Test name
Test status
Simulation time 4013184613 ps
CPU time 7.35 seconds
Started Aug 18 04:54:33 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 233752 kb
Host smart-834ba856-905c-4456-af3e-f4018fca7674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534708251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3534708251
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.533279942
Short name T481
Test name
Test status
Simulation time 14682769 ps
CPU time 0.73 seconds
Started Aug 18 04:54:35 PM PDT 24
Finished Aug 18 04:54:36 PM PDT 24
Peak memory 206544 kb
Host smart-df233641-a43d-49b2-8ce6-6bfa31044d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533279942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.533279942
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2056815201
Short name T26
Test name
Test status
Simulation time 456505798 ps
CPU time 4.26 seconds
Started Aug 18 04:54:34 PM PDT 24
Finished Aug 18 04:54:39 PM PDT 24
Peak memory 225124 kb
Host smart-3b9001cd-5031-46b9-aa30-b22256578384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056815201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2056815201
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.515370918
Short name T798
Test name
Test status
Simulation time 71084071 ps
CPU time 0.8 seconds
Started Aug 18 04:54:40 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 207744 kb
Host smart-9d2f5277-e54c-4241-9bf3-fba257155be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515370918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.515370918
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3878046804
Short name T61
Test name
Test status
Simulation time 2792436175 ps
CPU time 40.3 seconds
Started Aug 18 04:54:35 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 250468 kb
Host smart-c5fbd6de-306c-4c50-9a54-25125778ef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878046804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3878046804
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2585845319
Short name T756
Test name
Test status
Simulation time 64158132008 ps
CPU time 144.49 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:57:10 PM PDT 24
Peak memory 268608 kb
Host smart-74dfa25d-39e1-403b-b34f-acad5a718360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585845319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2585845319
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4237036409
Short name T184
Test name
Test status
Simulation time 96303543446 ps
CPU time 382.15 seconds
Started Aug 18 04:54:39 PM PDT 24
Finished Aug 18 05:01:02 PM PDT 24
Peak memory 272008 kb
Host smart-a8993f61-f3f9-4d27-bcc0-9ccad452d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237036409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4237036409
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2162782291
Short name T897
Test name
Test status
Simulation time 532701025 ps
CPU time 4.03 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:54:43 PM PDT 24
Peak memory 225372 kb
Host smart-2e3edb95-ed7e-472f-9029-5d7689cafc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162782291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2162782291
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1573469805
Short name T202
Test name
Test status
Simulation time 5817551061 ps
CPU time 52.04 seconds
Started Aug 18 04:54:34 PM PDT 24
Finished Aug 18 04:55:26 PM PDT 24
Peak memory 240836 kb
Host smart-a08b1972-e991-4cca-b47c-c4c761885179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573469805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1573469805
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2433759021
Short name T758
Test name
Test status
Simulation time 354917383 ps
CPU time 5.65 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:54:44 PM PDT 24
Peak memory 233580 kb
Host smart-faedd8ea-b76e-49d3-b546-ba7562c6e4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433759021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2433759021
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.57724637
Short name T530
Test name
Test status
Simulation time 1590031750 ps
CPU time 4.69 seconds
Started Aug 18 04:54:40 PM PDT 24
Finished Aug 18 04:54:45 PM PDT 24
Peak memory 225268 kb
Host smart-305a46a3-68d6-4cd3-a454-f47188faee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57724637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.57724637
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.72162369
Short name T920
Test name
Test status
Simulation time 2479091806 ps
CPU time 5.44 seconds
Started Aug 18 04:54:35 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 225456 kb
Host smart-92a75299-6c28-451c-b6c1-c4eeffcdd2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72162369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.72162369
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3813490102
Short name T970
Test name
Test status
Simulation time 9109799981 ps
CPU time 10.09 seconds
Started Aug 18 04:54:37 PM PDT 24
Finished Aug 18 04:54:47 PM PDT 24
Peak memory 238900 kb
Host smart-078e730d-402a-4575-9f33-0e4e7d7411b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813490102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3813490102
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3903758422
Short name T770
Test name
Test status
Simulation time 191158647 ps
CPU time 3.87 seconds
Started Aug 18 04:54:36 PM PDT 24
Finished Aug 18 04:54:40 PM PDT 24
Peak memory 219936 kb
Host smart-276ce0c1-61ed-488b-86b3-5cfa080eba5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903758422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3903758422
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1072211868
Short name T929
Test name
Test status
Simulation time 196073123 ps
CPU time 1.05 seconds
Started Aug 18 04:54:40 PM PDT 24
Finished Aug 18 04:54:41 PM PDT 24
Peak memory 208456 kb
Host smart-fc161964-5633-4576-83c9-ec9a4514ddb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072211868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1072211868
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4047799691
Short name T325
Test name
Test status
Simulation time 3781629979 ps
CPU time 11.5 seconds
Started Aug 18 04:54:34 PM PDT 24
Finished Aug 18 04:54:46 PM PDT 24
Peak memory 217284 kb
Host smart-7fab4096-4fd6-460f-bc2d-2b54202c32fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047799691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4047799691
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2956821168
Short name T542
Test name
Test status
Simulation time 6988890171 ps
CPU time 5 seconds
Started Aug 18 04:54:35 PM PDT 24
Finished Aug 18 04:54:40 PM PDT 24
Peak memory 217336 kb
Host smart-6e2d8e95-cd6c-4dba-a79f-84ac9e3f5961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956821168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2956821168
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3055000391
Short name T23
Test name
Test status
Simulation time 96058318 ps
CPU time 0.81 seconds
Started Aug 18 04:54:37 PM PDT 24
Finished Aug 18 04:54:38 PM PDT 24
Peak memory 206736 kb
Host smart-5016e961-6244-4b34-9b1c-c8493b0074cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055000391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3055000391
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2548223309
Short name T423
Test name
Test status
Simulation time 165122006 ps
CPU time 0.94 seconds
Started Aug 18 04:54:44 PM PDT 24
Finished Aug 18 04:54:45 PM PDT 24
Peak memory 207228 kb
Host smart-f0773e3d-88db-4f83-ae2b-8c1deed3e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548223309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2548223309
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1753680935
Short name T249
Test name
Test status
Simulation time 377759418 ps
CPU time 4.54 seconds
Started Aug 18 04:54:39 PM PDT 24
Finished Aug 18 04:54:44 PM PDT 24
Peak memory 233784 kb
Host smart-04b7bb75-2667-4a75-bbe1-f90a0fbd4f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753680935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1753680935
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2075960889
Short name T502
Test name
Test status
Simulation time 39704861 ps
CPU time 0.69 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:54:48 PM PDT 24
Peak memory 206292 kb
Host smart-e0827383-1ea2-43ab-ba77-76ffb34b0757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075960889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2075960889
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2372314112
Short name T350
Test name
Test status
Simulation time 3389484008 ps
CPU time 19.9 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 233632 kb
Host smart-c56faf90-f7ea-4884-8cc4-edacbbc45ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372314112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2372314112
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2239671930
Short name T395
Test name
Test status
Simulation time 17307755 ps
CPU time 0.71 seconds
Started Aug 18 04:54:38 PM PDT 24
Finished Aug 18 04:54:39 PM PDT 24
Peak memory 206392 kb
Host smart-841cc25c-44e1-4d1e-9620-9c3fd1342d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239671930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2239671930
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3835858271
Short name T708
Test name
Test status
Simulation time 7144051997 ps
CPU time 61.36 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 249996 kb
Host smart-f16d2910-86b9-4589-840e-eba22db5dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835858271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3835858271
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1701459904
Short name T885
Test name
Test status
Simulation time 1664849856 ps
CPU time 26.34 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:55:13 PM PDT 24
Peak memory 218516 kb
Host smart-aecb4546-bc23-471c-bba9-a3dd49a9f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701459904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1701459904
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2843140566
Short name T389
Test name
Test status
Simulation time 154389881 ps
CPU time 2.81 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:54:49 PM PDT 24
Peak memory 233476 kb
Host smart-9acfa887-b03e-4ac5-94a8-b858f2745787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843140566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2843140566
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2827492853
Short name T627
Test name
Test status
Simulation time 11434774824 ps
CPU time 37.98 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:55:24 PM PDT 24
Peak memory 233716 kb
Host smart-f65203ef-c1b1-40aa-b9d9-65e493494053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827492853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2827492853
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1167345422
Short name T220
Test name
Test status
Simulation time 6736949375 ps
CPU time 11.31 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:54:57 PM PDT 24
Peak memory 225344 kb
Host smart-a4751488-925f-4b81-a8e6-4c828d4107b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167345422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1167345422
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2487183360
Short name T241
Test name
Test status
Simulation time 6014339247 ps
CPU time 12.53 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 225468 kb
Host smart-9031d1f8-9004-4c47-973c-8a6ba6c890d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487183360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2487183360
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3117076444
Short name T746
Test name
Test status
Simulation time 1390750498 ps
CPU time 4.23 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 220340 kb
Host smart-563124d8-757d-4325-8bbf-c5d20b5e9338
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117076444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3117076444
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3957149454
Short name T978
Test name
Test status
Simulation time 58784118 ps
CPU time 1.15 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 207732 kb
Host smart-fb0a2ce3-e76e-4997-b805-1dea1775af47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957149454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3957149454
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2654946401
Short name T773
Test name
Test status
Simulation time 1006510635 ps
CPU time 9.56 seconds
Started Aug 18 04:54:39 PM PDT 24
Finished Aug 18 04:54:48 PM PDT 24
Peak memory 217212 kb
Host smart-2e62d203-38f6-4944-adbe-0ae724df5f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654946401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2654946401
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4127209739
Short name T536
Test name
Test status
Simulation time 12346732022 ps
CPU time 6.41 seconds
Started Aug 18 04:54:40 PM PDT 24
Finished Aug 18 04:54:47 PM PDT 24
Peak memory 217296 kb
Host smart-5826d11b-5a0d-4a50-8538-14310f9bac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127209739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4127209739
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.584252534
Short name T337
Test name
Test status
Simulation time 35762644 ps
CPU time 1.06 seconds
Started Aug 18 04:54:35 PM PDT 24
Finished Aug 18 04:54:36 PM PDT 24
Peak memory 208360 kb
Host smart-b44ecc7c-ab71-48aa-a7fb-173ccba61c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584252534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.584252534
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2220709399
Short name T361
Test name
Test status
Simulation time 542258473 ps
CPU time 1.01 seconds
Started Aug 18 04:54:36 PM PDT 24
Finished Aug 18 04:54:37 PM PDT 24
Peak memory 206852 kb
Host smart-03983592-c5cd-47d0-bc9b-0060e85a675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220709399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2220709399
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2344305755
Short name T865
Test name
Test status
Simulation time 20126993757 ps
CPU time 29.69 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 235720 kb
Host smart-210f14d9-b8d7-4fc1-81d4-8fef69fd151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344305755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2344305755
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2946956259
Short name T926
Test name
Test status
Simulation time 43514635 ps
CPU time 0.71 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:54:48 PM PDT 24
Peak memory 206100 kb
Host smart-c807da9c-06ed-4419-b797-e8f3f2047242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946956259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2946956259
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2330248551
Short name T58
Test name
Test status
Simulation time 940003591 ps
CPU time 5.22 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:54:52 PM PDT 24
Peak memory 233588 kb
Host smart-4e366a24-0759-4c3c-9d97-4b19a2f0d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330248551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2330248551
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1409091191
Short name T363
Test name
Test status
Simulation time 116788716 ps
CPU time 0.72 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:54:47 PM PDT 24
Peak memory 206380 kb
Host smart-13febff7-81a8-4d6b-b886-c9a96b20d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409091191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1409091191
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3619053657
Short name T70
Test name
Test status
Simulation time 2564777631 ps
CPU time 26.72 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 237228 kb
Host smart-a978d836-0e63-48c8-a62c-e87a76f1075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619053657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3619053657
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3796803753
Short name T730
Test name
Test status
Simulation time 470829557045 ps
CPU time 553.18 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 05:04:02 PM PDT 24
Peak memory 264052 kb
Host smart-bfd4e2ed-d142-4802-8929-451e36e9d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796803753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3796803753
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.29354102
Short name T900
Test name
Test status
Simulation time 4442724541 ps
CPU time 27.32 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 252624 kb
Host smart-aeb8771d-7c7f-4aad-964d-99cc7ad80854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29354102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.29354102
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.905085232
Short name T847
Test name
Test status
Simulation time 55032464 ps
CPU time 3.17 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 233524 kb
Host smart-23cfc876-ff8d-420a-a8e3-b4cdb192e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905085232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.905085232
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2215814387
Short name T216
Test name
Test status
Simulation time 46700474949 ps
CPU time 194.5 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:58:01 PM PDT 24
Peak memory 254676 kb
Host smart-eef9c346-6ba0-43c4-a6e8-9912e74ef6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215814387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2215814387
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.567495649
Short name T626
Test name
Test status
Simulation time 59257205314 ps
CPU time 38.56 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:55:28 PM PDT 24
Peak memory 225492 kb
Host smart-d22d9be1-183e-43c3-b453-02a9d7f2cfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567495649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.567495649
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.60125798
Short name T237
Test name
Test status
Simulation time 4528196059 ps
CPU time 35.27 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:55:22 PM PDT 24
Peak memory 233672 kb
Host smart-a1a65397-87e9-47bc-8c88-fd313ad4cde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60125798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.60125798
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2779517034
Short name T262
Test name
Test status
Simulation time 11674409211 ps
CPU time 30.73 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:55:17 PM PDT 24
Peak memory 235784 kb
Host smart-8020832c-2681-4a5c-aaff-955313410dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779517034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2779517034
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2243918755
Short name T105
Test name
Test status
Simulation time 29194459303 ps
CPU time 22.24 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:55:10 PM PDT 24
Peak memory 225372 kb
Host smart-023288ce-f96d-44d5-9454-a86b218c3073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243918755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2243918755
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.637028929
Short name T149
Test name
Test status
Simulation time 355081302 ps
CPU time 3.54 seconds
Started Aug 18 04:54:48 PM PDT 24
Finished Aug 18 04:54:52 PM PDT 24
Peak memory 223920 kb
Host smart-850b3cbb-e8ec-4666-b8d0-165b147cf0a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637028929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.637028929
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2249766387
Short name T169
Test name
Test status
Simulation time 127259017 ps
CPU time 0.93 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 207608 kb
Host smart-610065a9-d70a-4d96-bf37-b199434efd62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249766387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2249766387
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.710790161
Short name T705
Test name
Test status
Simulation time 156996558 ps
CPU time 2.38 seconds
Started Aug 18 04:54:49 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 217124 kb
Host smart-3e12e326-d31f-4f5c-98a4-e9c118b8ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710790161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.710790161
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.522733711
Short name T447
Test name
Test status
Simulation time 1320013283 ps
CPU time 5.56 seconds
Started Aug 18 04:54:45 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 217168 kb
Host smart-0336b9ee-a7b0-4938-bd2a-ac8fa8e9a74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522733711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.522733711
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.77496607
Short name T676
Test name
Test status
Simulation time 339484142 ps
CPU time 5.04 seconds
Started Aug 18 04:54:46 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 217140 kb
Host smart-c81a9b0f-cbda-460f-b7a7-e4247ed60a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77496607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.77496607
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1528971068
Short name T642
Test name
Test status
Simulation time 136982610 ps
CPU time 0.83 seconds
Started Aug 18 04:54:50 PM PDT 24
Finished Aug 18 04:54:51 PM PDT 24
Peak memory 206820 kb
Host smart-00abb61b-2787-485b-8357-069e8d40d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528971068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1528971068
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3558890898
Short name T686
Test name
Test status
Simulation time 4202718450 ps
CPU time 6.75 seconds
Started Aug 18 04:54:50 PM PDT 24
Finished Aug 18 04:54:57 PM PDT 24
Peak memory 225544 kb
Host smart-3d038130-91b9-4733-9c7a-66ec198e6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558890898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3558890898
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1015244039
Short name T704
Test name
Test status
Simulation time 14358486 ps
CPU time 0.73 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:54:57 PM PDT 24
Peak memory 205724 kb
Host smart-ac5e5a8e-c3dc-40ce-b323-566b21f053a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015244039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1015244039
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2023827283
Short name T450
Test name
Test status
Simulation time 45918254 ps
CPU time 0.76 seconds
Started Aug 18 04:54:47 PM PDT 24
Finished Aug 18 04:54:48 PM PDT 24
Peak memory 206360 kb
Host smart-a97415bb-01bb-453c-88af-6caacbfb5716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023827283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2023827283
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3810339832
Short name T942
Test name
Test status
Simulation time 46782156 ps
CPU time 0.76 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:54:56 PM PDT 24
Peak memory 216608 kb
Host smart-a6258508-06cc-47dc-b4b0-fc00268a9db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810339832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3810339832
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3251286927
Short name T568
Test name
Test status
Simulation time 27977087947 ps
CPU time 116.16 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:56:51 PM PDT 24
Peak memory 253912 kb
Host smart-37189e4a-a145-4d06-b8ed-0239a02ce2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251286927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3251286927
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3925403592
Short name T990
Test name
Test status
Simulation time 2919095831 ps
CPU time 34.33 seconds
Started Aug 18 04:54:54 PM PDT 24
Finished Aug 18 04:55:28 PM PDT 24
Peak memory 233716 kb
Host smart-d0fbd62d-bcfe-40d2-bbe7-1865830da830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925403592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3925403592
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2765112421
Short name T580
Test name
Test status
Simulation time 79666989264 ps
CPU time 97.79 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 255388 kb
Host smart-163e90fa-b0be-4b25-9cb5-ffc7c30c13f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765112421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2765112421
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2411780604
Short name T76
Test name
Test status
Simulation time 2758082813 ps
CPU time 19.38 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 225428 kb
Host smart-5b3f2779-8b7a-463c-bf76-fb943a6b5333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411780604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2411780604
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.931027569
Short name T991
Test name
Test status
Simulation time 2031561651 ps
CPU time 8.93 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:55:04 PM PDT 24
Peak memory 233556 kb
Host smart-dfae18aa-43fb-46c1-92ff-6ba68d4c087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931027569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.931027569
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3054468027
Short name T435
Test name
Test status
Simulation time 33394904 ps
CPU time 2.27 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:54:59 PM PDT 24
Peak memory 233148 kb
Host smart-9a74ff61-d804-4c10-be6a-c82fa15639cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054468027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3054468027
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3725636564
Short name T601
Test name
Test status
Simulation time 2334926534 ps
CPU time 5.06 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:55:01 PM PDT 24
Peak memory 233592 kb
Host smart-06e24ec8-2700-4b5a-905c-ce242d7b03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725636564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3725636564
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2015062127
Short name T569
Test name
Test status
Simulation time 117192793 ps
CPU time 3.46 seconds
Started Aug 18 04:55:00 PM PDT 24
Finished Aug 18 04:55:03 PM PDT 24
Peak memory 223560 kb
Host smart-0c1600be-9e7a-42a4-884a-89a422f04464
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015062127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2015062127
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1663699130
Short name T158
Test name
Test status
Simulation time 41698419510 ps
CPU time 331.16 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 05:00:26 PM PDT 24
Peak memory 266484 kb
Host smart-1cfe8a10-78df-4247-bbc4-ef1446697e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663699130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1663699130
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.768618525
Short name T544
Test name
Test status
Simulation time 2930988208 ps
CPU time 17.34 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 217572 kb
Host smart-19a32192-e2a4-4790-8e4f-27f8ac3347c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768618525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.768618525
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2065488321
Short name T557
Test name
Test status
Simulation time 724663643 ps
CPU time 5.75 seconds
Started Aug 18 04:54:54 PM PDT 24
Finished Aug 18 04:55:00 PM PDT 24
Peak memory 217172 kb
Host smart-0f254c1c-26e3-4822-bd6a-717b98fdfe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065488321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2065488321
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2517649873
Short name T669
Test name
Test status
Simulation time 93155367 ps
CPU time 0.7 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:54:57 PM PDT 24
Peak memory 206488 kb
Host smart-1fae5a05-8532-40de-aadd-68dcdc13d86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517649873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2517649873
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2258361266
Short name T406
Test name
Test status
Simulation time 34753939 ps
CPU time 0.86 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 206848 kb
Host smart-9cd61845-383f-4c38-ad6e-449740f3031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258361266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2258361266
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1890567226
Short name T238
Test name
Test status
Simulation time 3258471384 ps
CPU time 5.99 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:55:02 PM PDT 24
Peak memory 233704 kb
Host smart-80bf5ff7-abdf-4a53-8de7-7b70d0128209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890567226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1890567226
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1810556988
Short name T691
Test name
Test status
Simulation time 12029607 ps
CPU time 0.72 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 206276 kb
Host smart-a68954fa-4931-4da6-8364-79c9e6d9d89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810556988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1810556988
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.347565201
Short name T257
Test name
Test status
Simulation time 827594818 ps
CPU time 4.07 seconds
Started Aug 18 04:54:54 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 233492 kb
Host smart-15c6de82-8ff5-4331-abcb-d58a3069504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347565201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.347565201
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.690481962
Short name T336
Test name
Test status
Simulation time 77834796 ps
CPU time 0.73 seconds
Started Aug 18 04:54:54 PM PDT 24
Finished Aug 18 04:54:55 PM PDT 24
Peak memory 206556 kb
Host smart-8f6a3d81-5142-4e7f-9a92-da08483483be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690481962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.690481962
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3787467951
Short name T51
Test name
Test status
Simulation time 40373988094 ps
CPU time 40.44 seconds
Started Aug 18 04:55:00 PM PDT 24
Finished Aug 18 04:55:40 PM PDT 24
Peak memory 250172 kb
Host smart-ae449536-b6f6-4919-b066-22244a9f462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787467951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3787467951
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2639993546
Short name T893
Test name
Test status
Simulation time 914661005 ps
CPU time 18.12 seconds
Started Aug 18 04:54:58 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 241720 kb
Host smart-3600a186-b87f-43ec-b8a5-5eaaba391e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639993546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2639993546
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3328102974
Short name T180
Test name
Test status
Simulation time 20166623491 ps
CPU time 80.54 seconds
Started Aug 18 04:54:58 PM PDT 24
Finished Aug 18 04:56:19 PM PDT 24
Peak memory 250376 kb
Host smart-f07cf960-02b7-4653-a4ac-572585a828de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328102974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3328102974
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3886506450
Short name T880
Test name
Test status
Simulation time 831936390 ps
CPU time 2.29 seconds
Started Aug 18 04:55:01 PM PDT 24
Finished Aug 18 04:55:03 PM PDT 24
Peak memory 223660 kb
Host smart-9eaf26d9-7d7e-4596-a3f4-17f55cdb99f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886506450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3886506450
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4104803824
Short name T281
Test name
Test status
Simulation time 13496701810 ps
CPU time 27.46 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:55:25 PM PDT 24
Peak memory 236740 kb
Host smart-2144943f-b5e7-4068-9414-3d40be3d7918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104803824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4104803824
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.625817749
Short name T432
Test name
Test status
Simulation time 10728268824 ps
CPU time 29.57 seconds
Started Aug 18 04:54:58 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 233608 kb
Host smart-737a2b9a-6701-4574-8b19-92c8f3a692b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625817749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.625817749
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1674889217
Short name T403
Test name
Test status
Simulation time 6558156158 ps
CPU time 12.98 seconds
Started Aug 18 04:55:00 PM PDT 24
Finished Aug 18 04:55:13 PM PDT 24
Peak memory 233592 kb
Host smart-c941aba9-bb2b-4afd-92da-9a309261ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674889217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1674889217
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2171755840
Short name T387
Test name
Test status
Simulation time 1022128488 ps
CPU time 5.67 seconds
Started Aug 18 04:55:02 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 221396 kb
Host smart-c8aaa5ed-b84d-42b4-bd57-48bb0ab2eef1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2171755840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2171755840
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.87498871
Short name T878
Test name
Test status
Simulation time 26448640740 ps
CPU time 329.18 seconds
Started Aug 18 04:55:10 PM PDT 24
Finished Aug 18 05:00:40 PM PDT 24
Peak memory 267888 kb
Host smart-3ad9948f-3833-450f-bcec-2c6f2f449ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87498871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.87498871
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4060742816
Short name T786
Test name
Test status
Simulation time 2363269391 ps
CPU time 19.91 seconds
Started Aug 18 04:55:03 PM PDT 24
Finished Aug 18 04:55:23 PM PDT 24
Peak memory 217384 kb
Host smart-c036d042-8afb-4a67-b8cc-7ffac7815d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060742816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4060742816
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3303290338
Short name T332
Test name
Test status
Simulation time 1095113560 ps
CPU time 4.34 seconds
Started Aug 18 04:54:55 PM PDT 24
Finished Aug 18 04:55:00 PM PDT 24
Peak memory 217096 kb
Host smart-211693de-2ac3-491a-a672-ba3203319547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303290338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3303290338
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.888534617
Short name T828
Test name
Test status
Simulation time 29307954 ps
CPU time 1 seconds
Started Aug 18 04:54:57 PM PDT 24
Finished Aug 18 04:54:58 PM PDT 24
Peak memory 208396 kb
Host smart-6f561c1c-8cc2-4a61-ae7a-4fcd5643f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888534617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.888534617
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4218142602
Short name T504
Test name
Test status
Simulation time 39038400 ps
CPU time 0.72 seconds
Started Aug 18 04:54:56 PM PDT 24
Finished Aug 18 04:54:56 PM PDT 24
Peak memory 206836 kb
Host smart-09278216-1350-496c-9309-1e37891fbc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218142602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4218142602
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1112539575
Short name T239
Test name
Test status
Simulation time 30235058317 ps
CPU time 35.88 seconds
Started Aug 18 04:55:01 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 233536 kb
Host smart-22dff672-6aa8-4c8c-bbf9-1db567e922b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112539575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1112539575
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1060747732
Short name T864
Test name
Test status
Simulation time 22077885 ps
CPU time 0.79 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:05 PM PDT 24
Peak memory 206140 kb
Host smart-7091b68b-8b7a-472c-88d1-8078f609b28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060747732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1060747732
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.65041457
Short name T408
Test name
Test status
Simulation time 1251807776 ps
CPU time 5.24 seconds
Started Aug 18 04:55:09 PM PDT 24
Finished Aug 18 04:55:14 PM PDT 24
Peak memory 233504 kb
Host smart-8bfa97c8-d90e-430d-89a0-ba526c31cb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65041457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.65041457
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3079049665
Short name T12
Test name
Test status
Simulation time 41306491 ps
CPU time 0.72 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:06 PM PDT 24
Peak memory 206168 kb
Host smart-48a56959-42f5-4a4b-a54f-5c0ecd48ee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079049665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3079049665
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2380379376
Short name T720
Test name
Test status
Simulation time 74293059948 ps
CPU time 272.81 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:59:37 PM PDT 24
Peak memory 257948 kb
Host smart-41fe893f-a70d-4ed8-8002-f1f3e234dc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380379376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2380379376
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2042164073
Short name T817
Test name
Test status
Simulation time 1546290859 ps
CPU time 18.69 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:24 PM PDT 24
Peak memory 238880 kb
Host smart-9b7ed33d-962e-412e-be7f-f811214d1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042164073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2042164073
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2029050832
Short name T141
Test name
Test status
Simulation time 381108094229 ps
CPU time 1005.76 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 05:11:51 PM PDT 24
Peak memory 282824 kb
Host smart-b758e62a-fac4-406e-86b6-5f072394ec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029050832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2029050832
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2990795489
Short name T858
Test name
Test status
Simulation time 2162114115 ps
CPU time 15.92 seconds
Started Aug 18 04:55:08 PM PDT 24
Finished Aug 18 04:55:24 PM PDT 24
Peak memory 239172 kb
Host smart-d2faa04b-0178-43e8-8478-23563dd2f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990795489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2990795489
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2580166749
Short name T888
Test name
Test status
Simulation time 5297337513 ps
CPU time 53.43 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:59 PM PDT 24
Peak memory 252828 kb
Host smart-b4a8b529-b707-498b-a985-2bd1c1172236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580166749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2580166749
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.909803182
Short name T243
Test name
Test status
Simulation time 1060064413 ps
CPU time 12.07 seconds
Started Aug 18 04:55:07 PM PDT 24
Finished Aug 18 04:55:19 PM PDT 24
Peak memory 225316 kb
Host smart-a27da42f-acf0-4160-9e16-1df3ba43bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909803182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.909803182
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2520266115
Short name T957
Test name
Test status
Simulation time 1188864500 ps
CPU time 8.32 seconds
Started Aug 18 04:55:07 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 225276 kb
Host smart-bdc9bf8f-4a36-4f23-9750-2d95bebfb926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520266115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2520266115
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3932018149
Short name T840
Test name
Test status
Simulation time 425750426 ps
CPU time 2.29 seconds
Started Aug 18 04:55:10 PM PDT 24
Finished Aug 18 04:55:13 PM PDT 24
Peak memory 225220 kb
Host smart-871f8535-5beb-4cb3-84bd-964a38b2fa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932018149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3932018149
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3199249354
Short name T776
Test name
Test status
Simulation time 25107710295 ps
CPU time 21.05 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 236516 kb
Host smart-88cc210a-8034-4b70-9ad3-32e275e0b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199249354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3199249354
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.748393139
Short name T804
Test name
Test status
Simulation time 1748063294 ps
CPU time 8.68 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 224012 kb
Host smart-5dc5fb3c-0cf8-4bf3-a9df-d462787d5150
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=748393139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.748393139
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4159842815
Short name T954
Test name
Test status
Simulation time 73851594862 ps
CPU time 203.33 seconds
Started Aug 18 04:55:10 PM PDT 24
Finished Aug 18 04:58:34 PM PDT 24
Peak memory 262192 kb
Host smart-8b2c312c-c654-4fab-bba1-4dda5ba382d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159842815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4159842815
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3547469641
Short name T550
Test name
Test status
Simulation time 8134518860 ps
CPU time 34.1 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:40 PM PDT 24
Peak memory 217276 kb
Host smart-57fa49a1-b906-4b80-930e-175031a6712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547469641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3547469641
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2864859043
Short name T837
Test name
Test status
Simulation time 444455344 ps
CPU time 1.99 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 208772 kb
Host smart-830806ea-056c-4e4d-bf4a-7ad17e1988f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864859043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2864859043
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2538931334
Short name T598
Test name
Test status
Simulation time 61827643 ps
CPU time 1.62 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:06 PM PDT 24
Peak memory 218404 kb
Host smart-e085f622-fc01-4f28-a649-05727f97f8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538931334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2538931334
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4048999626
Short name T371
Test name
Test status
Simulation time 138255769 ps
CPU time 0.88 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 206780 kb
Host smart-e6b25319-2e36-4b6a-8173-0ba72abf22f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048999626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4048999626
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3124933184
Short name T200
Test name
Test status
Simulation time 3930889900 ps
CPU time 9.12 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:14 PM PDT 24
Peak memory 233608 kb
Host smart-a7cf85d7-0c72-4b2f-962a-f2c04f5971bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124933184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3124933184
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3899024052
Short name T479
Test name
Test status
Simulation time 13276844 ps
CPU time 0.75 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:17 PM PDT 24
Peak memory 206304 kb
Host smart-2ec2aa07-4173-4ccb-b0b2-841411a49fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899024052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3899024052
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4238390590
Short name T923
Test name
Test status
Simulation time 44217378 ps
CPU time 2.61 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:18 PM PDT 24
Peak memory 233620 kb
Host smart-842ed09d-dd8a-4493-806a-ad07674630fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238390590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4238390590
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2199670435
Short name T801
Test name
Test status
Simulation time 46362674 ps
CPU time 0.77 seconds
Started Aug 18 04:55:04 PM PDT 24
Finished Aug 18 04:55:05 PM PDT 24
Peak memory 206324 kb
Host smart-dc29e69e-9dd4-4d26-93c3-775259045d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199670435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2199670435
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.705351348
Short name T378
Test name
Test status
Simulation time 71268688795 ps
CPU time 132.48 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:57:30 PM PDT 24
Peak memory 250060 kb
Host smart-e590a895-0734-4416-8613-5b93f129dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705351348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.705351348
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2086757762
Short name T218
Test name
Test status
Simulation time 3195503315 ps
CPU time 88.33 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 251644 kb
Host smart-a8f0c2f9-f40b-477b-8b02-88d6f51ef040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086757762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2086757762
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3226332971
Short name T362
Test name
Test status
Simulation time 1157102744 ps
CPU time 10.59 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:28 PM PDT 24
Peak memory 236016 kb
Host smart-ea1a1b32-d833-4d3a-bbda-d02a165d87bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226332971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3226332971
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3065523749
Short name T268
Test name
Test status
Simulation time 31378804164 ps
CPU time 214.71 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:58:53 PM PDT 24
Peak memory 255988 kb
Host smart-d2e6cffb-f5fc-4d50-bd8a-febaa51cca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065523749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3065523749
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2984906442
Short name T186
Test name
Test status
Simulation time 404717734 ps
CPU time 3.71 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:19 PM PDT 24
Peak memory 233648 kb
Host smart-1ae034cb-2112-4560-a263-e4ec112c5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984906442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2984906442
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1373047709
Short name T340
Test name
Test status
Simulation time 816403635 ps
CPU time 15.69 seconds
Started Aug 18 04:55:22 PM PDT 24
Finished Aug 18 04:55:38 PM PDT 24
Peak memory 249692 kb
Host smart-79d24a16-e5e2-4a70-9b46-16bf3ac29d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373047709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1373047709
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.662838645
Short name T436
Test name
Test status
Simulation time 1185355432 ps
CPU time 10.15 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:25 PM PDT 24
Peak memory 233464 kb
Host smart-c17461a8-d227-476b-9b62-aa91df199fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662838645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.662838645
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1016321238
Short name T713
Test name
Test status
Simulation time 296741905 ps
CPU time 5.55 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:23 PM PDT 24
Peak memory 237800 kb
Host smart-118a5e53-0ae9-45bd-ab15-7e23a071db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016321238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1016321238
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1225893872
Short name T916
Test name
Test status
Simulation time 4426833638 ps
CPU time 11.9 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:28 PM PDT 24
Peak memory 223112 kb
Host smart-d6689ce6-9e8b-4d96-97c3-a8a42f264bbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1225893872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1225893872
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3627197773
Short name T259
Test name
Test status
Simulation time 388137256128 ps
CPU time 364.58 seconds
Started Aug 18 04:55:19 PM PDT 24
Finished Aug 18 05:01:23 PM PDT 24
Peak memory 254732 kb
Host smart-2be653c7-c086-4c52-9ef6-e4a3ff0dcd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627197773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3627197773
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3047894543
Short name T810
Test name
Test status
Simulation time 55176315 ps
CPU time 0.72 seconds
Started Aug 18 04:55:07 PM PDT 24
Finished Aug 18 04:55:08 PM PDT 24
Peak memory 206476 kb
Host smart-e332747a-0653-4f74-8b7b-89d48db326c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047894543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3047894543
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4050164456
Short name T429
Test name
Test status
Simulation time 3231440107 ps
CPU time 9.82 seconds
Started Aug 18 04:55:04 PM PDT 24
Finished Aug 18 04:55:14 PM PDT 24
Peak memory 217196 kb
Host smart-c6a02b14-2f6e-4702-ac42-f5681ccad414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050164456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4050164456
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.318925300
Short name T335
Test name
Test status
Simulation time 80881673 ps
CPU time 0.73 seconds
Started Aug 18 04:55:06 PM PDT 24
Finished Aug 18 04:55:07 PM PDT 24
Peak memory 206272 kb
Host smart-6d9bfbe4-f577-4b9a-897c-ae532aca7fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318925300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.318925300
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4212435974
Short name T731
Test name
Test status
Simulation time 68223147 ps
CPU time 0.87 seconds
Started Aug 18 04:55:05 PM PDT 24
Finished Aug 18 04:55:06 PM PDT 24
Peak memory 206812 kb
Host smart-d3e91286-0a28-46e2-aebe-803cc6eb22b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212435974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4212435974
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2662282987
Short name T275
Test name
Test status
Simulation time 2319245805 ps
CPU time 7.35 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:24 PM PDT 24
Peak memory 225704 kb
Host smart-fb399169-a6bc-4ebe-95ac-9f7f0174c4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662282987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2662282987
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1196859807
Short name T848
Test name
Test status
Simulation time 12161725 ps
CPU time 0.75 seconds
Started Aug 18 04:55:21 PM PDT 24
Finished Aug 18 04:55:22 PM PDT 24
Peak memory 206592 kb
Host smart-9382c41e-5cb1-41ed-9453-64be292c7212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196859807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1196859807
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3736679212
Short name T784
Test name
Test status
Simulation time 655578686 ps
CPU time 3.79 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:20 PM PDT 24
Peak memory 225276 kb
Host smart-058cef4b-4010-4bc1-ab52-612ed5c8e7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736679212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3736679212
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.348708628
Short name T576
Test name
Test status
Simulation time 19939812 ps
CPU time 0.82 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 207636 kb
Host smart-7c914ca4-6357-4f5e-a676-ce3c2df2d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348708628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.348708628
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2840675514
Short name T193
Test name
Test status
Simulation time 56956367071 ps
CPU time 69.29 seconds
Started Aug 18 04:55:22 PM PDT 24
Finished Aug 18 04:56:32 PM PDT 24
Peak memory 271420 kb
Host smart-65e5bd14-73c4-44c0-a614-c26b9e5faf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840675514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2840675514
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3384005262
Short name T736
Test name
Test status
Simulation time 246644302603 ps
CPU time 230.51 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 265048 kb
Host smart-55d52cd7-e776-495c-9505-71e9a8dc0036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384005262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3384005262
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1091211419
Short name T290
Test name
Test status
Simulation time 59630305443 ps
CPU time 591.98 seconds
Started Aug 18 04:55:21 PM PDT 24
Finished Aug 18 05:05:13 PM PDT 24
Peak memory 271428 kb
Host smart-98d6f7d1-fb1f-443d-a7ca-0b957d531bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091211419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1091211419
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2750828584
Short name T540
Test name
Test status
Simulation time 8738493470 ps
CPU time 40.75 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:59 PM PDT 24
Peak memory 253340 kb
Host smart-d153eacd-1e3a-4b7f-a158-0eea61c7934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750828584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2750828584
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2160852981
Short name T390
Test name
Test status
Simulation time 4107919076 ps
CPU time 13.76 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:31 PM PDT 24
Peak memory 233640 kb
Host smart-80e4ebfe-5250-4325-a436-1e54017a62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160852981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2160852981
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1868976533
Short name T882
Test name
Test status
Simulation time 9673550188 ps
CPU time 39.57 seconds
Started Aug 18 04:55:22 PM PDT 24
Finished Aug 18 04:56:01 PM PDT 24
Peak memory 233636 kb
Host smart-28ace21f-5ee7-4190-91dc-e9c1e5f87614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868976533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1868976533
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2972256141
Short name T732
Test name
Test status
Simulation time 2056124182 ps
CPU time 6.76 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:25 PM PDT 24
Peak memory 233560 kb
Host smart-578495e8-b589-4206-849d-cab71ef52a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972256141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2972256141
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1232607379
Short name T790
Test name
Test status
Simulation time 4175875800 ps
CPU time 3.96 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:21 PM PDT 24
Peak memory 225416 kb
Host smart-c0d81aa3-f7eb-4358-ba2d-334ca80543b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232607379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1232607379
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2585549643
Short name T541
Test name
Test status
Simulation time 1483282729 ps
CPU time 14.17 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:31 PM PDT 24
Peak memory 222940 kb
Host smart-38a9599a-bc9a-4131-a71e-66b7437eb07b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2585549643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2585549643
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2548194086
Short name T796
Test name
Test status
Simulation time 308359515 ps
CPU time 2.85 seconds
Started Aug 18 04:55:21 PM PDT 24
Finished Aug 18 04:55:24 PM PDT 24
Peak memory 217200 kb
Host smart-a169e198-77b3-4f36-bec1-1247bba11a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548194086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2548194086
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.495755066
Short name T456
Test name
Test status
Simulation time 3589512314 ps
CPU time 7.64 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:24 PM PDT 24
Peak memory 217288 kb
Host smart-b1f2cb5d-31a3-40ff-b8d3-5202824f8c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495755066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.495755066
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1752482848
Short name T646
Test name
Test status
Simulation time 133314285 ps
CPU time 0.9 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:19 PM PDT 24
Peak memory 207820 kb
Host smart-b204922b-0123-4c6a-9ba2-463648de7be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752482848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1752482848
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2103284801
Short name T680
Test name
Test status
Simulation time 20068177 ps
CPU time 0.74 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:16 PM PDT 24
Peak memory 206740 kb
Host smart-f0f0f85c-2f53-4fb2-9b57-aeee71eac1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103284801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2103284801
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1977738554
Short name T367
Test name
Test status
Simulation time 369671935 ps
CPU time 5.97 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:21 PM PDT 24
Peak memory 241676 kb
Host smart-8b829d44-f77d-4e4c-94b8-413f0848316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977738554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1977738554
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1709215210
Short name T716
Test name
Test status
Simulation time 13929724 ps
CPU time 0.73 seconds
Started Aug 18 04:53:33 PM PDT 24
Finished Aug 18 04:53:34 PM PDT 24
Peak memory 206236 kb
Host smart-abaa3435-8324-4786-84e9-f18c52cea908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709215210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
709215210
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3932594790
Short name T748
Test name
Test status
Simulation time 1405696595 ps
CPU time 14.72 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:49 PM PDT 24
Peak memory 225412 kb
Host smart-f294ed65-817d-4b91-a491-31034aa87f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932594790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3932594790
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.210281566
Short name T881
Test name
Test status
Simulation time 54747925 ps
CPU time 0.77 seconds
Started Aug 18 04:53:38 PM PDT 24
Finished Aug 18 04:53:39 PM PDT 24
Peak memory 207336 kb
Host smart-ca1caffd-22b8-4b61-9ccd-fb395f76f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210281566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.210281566
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.476409050
Short name T63
Test name
Test status
Simulation time 16628699781 ps
CPU time 64.39 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:54:40 PM PDT 24
Peak memory 250196 kb
Host smart-f7873aa0-f084-4374-ba6e-43f1063b4ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476409050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
476409050
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.537042618
Short name T448
Test name
Test status
Simulation time 3675395783 ps
CPU time 28.35 seconds
Started Aug 18 04:53:37 PM PDT 24
Finished Aug 18 04:54:05 PM PDT 24
Peak memory 233696 kb
Host smart-807c40d8-aefb-4441-be0b-54f75890da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537042618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.537042618
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2513787737
Short name T191
Test name
Test status
Simulation time 55059047386 ps
CPU time 57.81 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:54:32 PM PDT 24
Peak memory 225432 kb
Host smart-d6d9ab76-078d-40e9-96bb-2e6870fc78f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513787737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2513787737
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3212732575
Short name T910
Test name
Test status
Simulation time 1270929785 ps
CPU time 7.64 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:53:43 PM PDT 24
Peak memory 233564 kb
Host smart-b3634ef1-7bb2-48f7-b6af-60df8ef1e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212732575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3212732575
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2793341244
Short name T612
Test name
Test status
Simulation time 50318945 ps
CPU time 2.36 seconds
Started Aug 18 04:53:33 PM PDT 24
Finished Aug 18 04:53:35 PM PDT 24
Peak memory 233628 kb
Host smart-6b8f777d-f0ec-479d-876d-1ef37048a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793341244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2793341244
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1723115188
Short name T263
Test name
Test status
Simulation time 6364026641 ps
CPU time 18.42 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:53:53 PM PDT 24
Peak memory 233716 kb
Host smart-9c9f714e-648a-433d-a538-4273cbc33584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723115188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1723115188
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3962240262
Short name T830
Test name
Test status
Simulation time 987558176 ps
CPU time 3.26 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:38 PM PDT 24
Peak memory 233492 kb
Host smart-b575cc5d-0fbb-4deb-a772-1af4c239c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962240262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3962240262
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1825281944
Short name T439
Test name
Test status
Simulation time 2100827060 ps
CPU time 16.76 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:51 PM PDT 24
Peak memory 223016 kb
Host smart-c666de67-da56-4769-8c97-13a361773fcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1825281944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1825281944
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.301871721
Short name T19
Test name
Test status
Simulation time 119157912 ps
CPU time 0.98 seconds
Started Aug 18 04:53:37 PM PDT 24
Finished Aug 18 04:53:39 PM PDT 24
Peak memory 235984 kb
Host smart-953abea4-787e-4e33-bb6c-dc0f40143527
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301871721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.301871721
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2615046063
Short name T183
Test name
Test status
Simulation time 51109818615 ps
CPU time 261.47 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:57:56 PM PDT 24
Peak memory 258312 kb
Host smart-28f6f92c-c947-4525-81a6-59a484e27ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615046063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2615046063
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3862848899
Short name T40
Test name
Test status
Simulation time 12191586 ps
CPU time 0.71 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:53:36 PM PDT 24
Peak memory 206472 kb
Host smart-699269cc-ac6f-4901-b9e1-774efe7dbf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862848899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3862848899
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.92042832
Short name T791
Test name
Test status
Simulation time 11671440652 ps
CPU time 16.18 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:50 PM PDT 24
Peak memory 217168 kb
Host smart-90435f26-057d-4004-a1e4-a0dc3e936b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92042832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.92042832
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1930727032
Short name T7
Test name
Test status
Simulation time 130815564 ps
CPU time 2.63 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:53:38 PM PDT 24
Peak memory 217036 kb
Host smart-60e74c32-5260-4eca-996f-481e9851e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930727032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1930727032
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1441162561
Short name T370
Test name
Test status
Simulation time 58054126 ps
CPU time 0.77 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:53:36 PM PDT 24
Peak memory 206840 kb
Host smart-ab01594f-0e09-4fcf-976f-cbf22c9f257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441162561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1441162561
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4098935046
Short name T526
Test name
Test status
Simulation time 3861710022 ps
CPU time 17.08 seconds
Started Aug 18 04:53:35 PM PDT 24
Finished Aug 18 04:53:52 PM PDT 24
Peak memory 241812 kb
Host smart-6dc5d0e5-0fd6-46b2-95ab-3a86097d9264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098935046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4098935046
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4225900986
Short name T485
Test name
Test status
Simulation time 24137208 ps
CPU time 0.73 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:55:30 PM PDT 24
Peak memory 206204 kb
Host smart-2847ff9a-47af-4782-8914-f72caba1418e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225900986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4225900986
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.183859939
Short name T518
Test name
Test status
Simulation time 37977821 ps
CPU time 2.41 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:55:31 PM PDT 24
Peak memory 225352 kb
Host smart-0a6967be-4060-4eca-bc1a-ef4da1d9d5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183859939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.183859939
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3786799312
Short name T904
Test name
Test status
Simulation time 42844177 ps
CPU time 0.79 seconds
Started Aug 18 04:55:20 PM PDT 24
Finished Aug 18 04:55:21 PM PDT 24
Peak memory 207404 kb
Host smart-7c9ca1c5-4c11-4d65-81de-91c18ab01486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786799312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3786799312
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2685914546
Short name T588
Test name
Test status
Simulation time 81920828 ps
CPU time 0.76 seconds
Started Aug 18 04:55:25 PM PDT 24
Finished Aug 18 04:55:25 PM PDT 24
Peak memory 216680 kb
Host smart-a27f76f9-10df-4deb-8f40-02a17dd73aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685914546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2685914546
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.298810518
Short name T911
Test name
Test status
Simulation time 7973763494 ps
CPU time 63.41 seconds
Started Aug 18 04:55:30 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 252460 kb
Host smart-cbfcb212-8c3b-4fb1-a4f2-3a271c5f316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298810518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.298810518
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2892568699
Short name T980
Test name
Test status
Simulation time 1308034549 ps
CPU time 2.57 seconds
Started Aug 18 04:55:25 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 225380 kb
Host smart-fed79753-63da-4148-a7c1-0d4b5f8ded06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892568699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2892568699
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2282359890
Short name T50
Test name
Test status
Simulation time 23632333243 ps
CPU time 162.09 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:58:14 PM PDT 24
Peak memory 250096 kb
Host smart-fa620a42-4eb8-4e80-b6c4-c1d23e2a2d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282359890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2282359890
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2271221493
Short name T413
Test name
Test status
Simulation time 353848831 ps
CPU time 3.84 seconds
Started Aug 18 04:55:14 PM PDT 24
Finished Aug 18 04:55:17 PM PDT 24
Peak memory 233520 kb
Host smart-c8c27378-a55e-4635-a51b-4ccf1fce611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271221493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2271221493
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3495280333
Short name T104
Test name
Test status
Simulation time 8050510194 ps
CPU time 27.02 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:44 PM PDT 24
Peak memory 249708 kb
Host smart-0146f533-5d39-4e60-9227-e6c64f98c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495280333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3495280333
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3861033587
Short name T987
Test name
Test status
Simulation time 164809969 ps
CPU time 2.7 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:20 PM PDT 24
Peak memory 225308 kb
Host smart-d00eda86-cdee-43c5-98d3-fe918a78c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861033587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3861033587
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3404926642
Short name T209
Test name
Test status
Simulation time 96093013084 ps
CPU time 26.44 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:45 PM PDT 24
Peak memory 225452 kb
Host smart-c02233ec-7a01-47ce-8d9f-8c09955873a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404926642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3404926642
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3596825900
Short name T471
Test name
Test status
Simulation time 1207281140 ps
CPU time 8.46 seconds
Started Aug 18 04:55:24 PM PDT 24
Finished Aug 18 04:55:32 PM PDT 24
Peak memory 221176 kb
Host smart-08a4217b-bdc1-4a7c-a08d-9106e50ada93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3596825900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3596825900
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2260832827
Short name T749
Test name
Test status
Simulation time 79716807 ps
CPU time 1.06 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:35 PM PDT 24
Peak memory 207832 kb
Host smart-f3c5d232-b4a6-4d97-9ec8-6cbfc4536988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260832827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2260832827
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3953980437
Short name T616
Test name
Test status
Simulation time 1209581399 ps
CPU time 12.17 seconds
Started Aug 18 04:55:18 PM PDT 24
Finished Aug 18 04:55:31 PM PDT 24
Peak memory 217408 kb
Host smart-e704a612-a913-47c8-a34c-cc176f4b024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953980437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3953980437
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2598351937
Short name T610
Test name
Test status
Simulation time 3040460999 ps
CPU time 2.59 seconds
Started Aug 18 04:55:15 PM PDT 24
Finished Aug 18 04:55:18 PM PDT 24
Peak memory 208872 kb
Host smart-64a9d913-23e5-4a05-bc5b-5d67fb38ba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598351937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2598351937
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4024240205
Short name T762
Test name
Test status
Simulation time 1513820103 ps
CPU time 12.52 seconds
Started Aug 18 04:55:17 PM PDT 24
Finished Aug 18 04:55:29 PM PDT 24
Peak memory 217076 kb
Host smart-03259a9e-68e9-445a-8731-a715818a1550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024240205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4024240205
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.844516692
Short name T1003
Test name
Test status
Simulation time 125441943 ps
CPU time 0.87 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:17 PM PDT 24
Peak memory 206892 kb
Host smart-61ce5703-703e-4a85-905d-24de230446ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844516692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.844516692
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.190822528
Short name T989
Test name
Test status
Simulation time 10044656538 ps
CPU time 10.96 seconds
Started Aug 18 04:55:16 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 225524 kb
Host smart-214bfa04-5fee-4f61-98e9-9c6d4fd80a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190822528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.190822528
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.422292862
Short name T68
Test name
Test status
Simulation time 17211114 ps
CPU time 0.73 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:55:30 PM PDT 24
Peak memory 206280 kb
Host smart-7dfdf7fc-ac45-4df5-a082-cd6f120afeef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422292862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.422292862
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4118279803
Short name T5
Test name
Test status
Simulation time 10182846112 ps
CPU time 15.06 seconds
Started Aug 18 04:55:32 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 225400 kb
Host smart-a420a295-a948-423c-9455-5bb9b6cadc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118279803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4118279803
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1616515186
Short name T90
Test name
Test status
Simulation time 21821634 ps
CPU time 0.75 seconds
Started Aug 18 04:55:32 PM PDT 24
Finished Aug 18 04:55:33 PM PDT 24
Peak memory 207736 kb
Host smart-8bc339ae-8b00-4996-91b4-8c5acf6838f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616515186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1616515186
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.592975436
Short name T44
Test name
Test status
Simulation time 158424779405 ps
CPU time 68.46 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:56:40 PM PDT 24
Peak memory 255752 kb
Host smart-c3fe3f39-671a-4840-a641-d58b33b90249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592975436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.592975436
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1171666006
Short name T285
Test name
Test status
Simulation time 2703124389 ps
CPU time 75.58 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 251540 kb
Host smart-ddff9ada-fc84-4e66-a2e9-ab9cdbf26c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171666006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1171666006
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3568371077
Short name T824
Test name
Test status
Simulation time 1715166893 ps
CPU time 10.78 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:42 PM PDT 24
Peak memory 236960 kb
Host smart-1eaa184a-f8ce-4b14-a7db-45b8ded34c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568371077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3568371077
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.505885813
Short name T494
Test name
Test status
Simulation time 41653368 ps
CPU time 0.72 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:34 PM PDT 24
Peak memory 216508 kb
Host smart-0ef17c3d-148a-4630-9938-887347cd14d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505885813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.505885813
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4286300495
Short name T981
Test name
Test status
Simulation time 1411689544 ps
CPU time 14.78 seconds
Started Aug 18 04:55:27 PM PDT 24
Finished Aug 18 04:55:42 PM PDT 24
Peak memory 230280 kb
Host smart-56a7f1e9-e6a4-402d-a5ce-5aa42b84e583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286300495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4286300495
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.846724122
Short name T879
Test name
Test status
Simulation time 5287573776 ps
CPU time 10.3 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:44 PM PDT 24
Peak memory 225368 kb
Host smart-3ad5220f-a072-466c-9f41-49a9d6e6ef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846724122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.846724122
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3059220651
Short name T689
Test name
Test status
Simulation time 111993375955 ps
CPU time 16.9 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 04:55:45 PM PDT 24
Peak memory 225636 kb
Host smart-7cc4c17d-fdd8-4208-9822-44f9cdb4eceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059220651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3059220651
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3711069842
Short name T741
Test name
Test status
Simulation time 629625560 ps
CPU time 6.57 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 04:55:34 PM PDT 24
Peak memory 221644 kb
Host smart-7ec64ece-7425-47ae-b8a3-eeea51fe6691
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3711069842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3711069842
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1080706552
Short name T979
Test name
Test status
Simulation time 2181015882 ps
CPU time 18.81 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:53 PM PDT 24
Peak memory 218504 kb
Host smart-3d5f80a3-a838-4277-85a8-30ce9c1b148f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080706552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1080706552
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1865915767
Short name T842
Test name
Test status
Simulation time 2579610651 ps
CPU time 30.34 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 04:55:59 PM PDT 24
Peak memory 217380 kb
Host smart-9491d054-6d99-481c-8f9f-d1482a5ba7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865915767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1865915767
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.75425175
Short name T474
Test name
Test status
Simulation time 1198882668 ps
CPU time 3.33 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:55:32 PM PDT 24
Peak memory 217164 kb
Host smart-8b4ff53e-16ad-4248-8319-082714ffbb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75425175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.75425175
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2952624788
Short name T678
Test name
Test status
Simulation time 55689748 ps
CPU time 2.65 seconds
Started Aug 18 04:55:24 PM PDT 24
Finished Aug 18 04:55:27 PM PDT 24
Peak memory 217072 kb
Host smart-867ef1e7-ef90-4caf-af8d-7b69858a5132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952624788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2952624788
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.763187989
Short name T512
Test name
Test status
Simulation time 145182285 ps
CPU time 1.11 seconds
Started Aug 18 04:55:24 PM PDT 24
Finished Aug 18 04:55:26 PM PDT 24
Peak memory 207812 kb
Host smart-a4e32c34-3b4a-4ebf-8bd4-eb19ec5e5eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763187989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.763187989
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1608649862
Short name T965
Test name
Test status
Simulation time 996204478 ps
CPU time 8.11 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:40 PM PDT 24
Peak memory 233628 kb
Host smart-dae05330-04a2-4207-8ae6-ff8ebcbeaf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608649862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1608649862
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2520728386
Short name T618
Test name
Test status
Simulation time 27950617 ps
CPU time 0.7 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:55:36 PM PDT 24
Peak memory 205676 kb
Host smart-879ed0b4-3a16-442e-8928-7863b2047d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520728386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2520728386
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.497583774
Short name T446
Test name
Test status
Simulation time 308863672 ps
CPU time 2.24 seconds
Started Aug 18 04:55:25 PM PDT 24
Finished Aug 18 04:55:28 PM PDT 24
Peak memory 233540 kb
Host smart-8d6f8c5a-4cb7-45dc-9c90-7f7f49b50598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497583774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.497583774
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3478275498
Short name T477
Test name
Test status
Simulation time 18335660 ps
CPU time 0.79 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:31 PM PDT 24
Peak memory 207652 kb
Host smart-e063994d-f1e3-49d9-87c6-aafb14fc8a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478275498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3478275498
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3889409651
Short name T73
Test name
Test status
Simulation time 37652696331 ps
CPU time 285.9 seconds
Started Aug 18 04:55:23 PM PDT 24
Finished Aug 18 05:00:09 PM PDT 24
Peak memory 257564 kb
Host smart-7af1fac6-d6ff-48d7-bd33-0c1eae831541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889409651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3889409651
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3036636525
Short name T66
Test name
Test status
Simulation time 310315824583 ps
CPU time 509.95 seconds
Started Aug 18 04:55:32 PM PDT 24
Finished Aug 18 05:04:02 PM PDT 24
Peak memory 266472 kb
Host smart-a274dec9-2d8e-4d91-9d68-70e8ec80c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036636525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3036636525
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2702010934
Short name T760
Test name
Test status
Simulation time 12917070750 ps
CPU time 127.65 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:57:42 PM PDT 24
Peak memory 241896 kb
Host smart-d1d7f81d-808a-4607-929e-dbf247c58f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702010934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2702010934
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.780913697
Short name T993
Test name
Test status
Simulation time 483544622 ps
CPU time 8.21 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:39 PM PDT 24
Peak memory 225264 kb
Host smart-b383c862-5a2c-4e1a-8f28-ab898a69c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780913697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.780913697
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3115225850
Short name T514
Test name
Test status
Simulation time 25459896063 ps
CPU time 79.71 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:56:53 PM PDT 24
Peak memory 251476 kb
Host smart-3f9b8e59-1423-47c1-94ab-cb3af2d91d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115225850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3115225850
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1514000417
Short name T562
Test name
Test status
Simulation time 2000057713 ps
CPU time 7.12 seconds
Started Aug 18 04:55:29 PM PDT 24
Finished Aug 18 04:55:36 PM PDT 24
Peak memory 225320 kb
Host smart-e49f59c3-ded5-4eea-97ee-d9e815e550d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514000417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1514000417
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4247186692
Short name T559
Test name
Test status
Simulation time 3958455170 ps
CPU time 36.43 seconds
Started Aug 18 04:55:32 PM PDT 24
Finished Aug 18 04:56:08 PM PDT 24
Peak memory 233596 kb
Host smart-616193d6-b06b-4b2e-87fc-6a9d3ad11577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247186692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4247186692
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3420219657
Short name T500
Test name
Test status
Simulation time 2900585649 ps
CPU time 3.85 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 233580 kb
Host smart-c48519a2-4e34-4cf5-a24b-7e1e12a7dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420219657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3420219657
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4106143232
Short name T424
Test name
Test status
Simulation time 188773081 ps
CPU time 4.19 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:35 PM PDT 24
Peak memory 233488 kb
Host smart-ca7e41f8-8e15-4f72-9a66-803ca104daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106143232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4106143232
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3007277408
Short name T146
Test name
Test status
Simulation time 256413455 ps
CPU time 3.74 seconds
Started Aug 18 04:55:30 PM PDT 24
Finished Aug 18 04:55:34 PM PDT 24
Peak memory 223872 kb
Host smart-897a7a39-5417-4509-80aa-1e0ca20dd254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007277408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3007277408
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2186509996
Short name T670
Test name
Test status
Simulation time 61659676 ps
CPU time 0.92 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:55:34 PM PDT 24
Peak memory 207476 kb
Host smart-44ec4494-e4de-4764-90b9-353f78fbdabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186509996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2186509996
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3289443014
Short name T845
Test name
Test status
Simulation time 10027765460 ps
CPU time 5.18 seconds
Started Aug 18 04:55:27 PM PDT 24
Finished Aug 18 04:55:33 PM PDT 24
Peak memory 217232 kb
Host smart-19310fcf-f5c0-4831-ace4-b680f98e6666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289443014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3289443014
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3737222915
Short name T891
Test name
Test status
Simulation time 4567752573 ps
CPU time 14.66 seconds
Started Aug 18 04:55:27 PM PDT 24
Finished Aug 18 04:55:42 PM PDT 24
Peak memory 217164 kb
Host smart-8dde5df6-8bc7-424d-bc65-2d60fd3e3199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737222915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3737222915
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2419285789
Short name T803
Test name
Test status
Simulation time 80135987 ps
CPU time 1.38 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:32 PM PDT 24
Peak memory 217076 kb
Host smart-e25318c7-95d7-4d2a-a6df-10a1578f9f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419285789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2419285789
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3634488133
Short name T952
Test name
Test status
Simulation time 112179233 ps
CPU time 0.76 seconds
Started Aug 18 04:55:28 PM PDT 24
Finished Aug 18 04:55:29 PM PDT 24
Peak memory 207028 kb
Host smart-89a1a57a-d88f-4428-b675-77e59aa3a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634488133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3634488133
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.575339466
Short name T857
Test name
Test status
Simulation time 432896141 ps
CPU time 5.41 seconds
Started Aug 18 04:55:31 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 238904 kb
Host smart-1d739b21-3f4e-4e0c-a0c9-0928b10aa9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575339466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.575339466
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2646082762
Short name T631
Test name
Test status
Simulation time 21905759 ps
CPU time 0.71 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:35 PM PDT 24
Peak memory 205552 kb
Host smart-f06e7017-c276-4221-90a9-db3f601e1694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646082762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2646082762
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3258496819
Short name T253
Test name
Test status
Simulation time 1832883687 ps
CPU time 5.55 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:40 PM PDT 24
Peak memory 225260 kb
Host smart-1901dac3-ecd1-4387-9750-bb88b2821fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258496819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3258496819
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2221688027
Short name T464
Test name
Test status
Simulation time 19297249 ps
CPU time 0.81 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 207692 kb
Host smart-0011f171-eab1-477f-ba8d-8229f1c957fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221688027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2221688027
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.245120646
Short name T766
Test name
Test status
Simulation time 70344460 ps
CPU time 0.79 seconds
Started Aug 18 04:55:37 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 216532 kb
Host smart-21b738c2-5356-489e-bb08-f11ecaa6159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245120646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.245120646
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3633063639
Short name T226
Test name
Test status
Simulation time 2783385810 ps
CPU time 29.41 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 241904 kb
Host smart-59bc5665-6bb8-4733-ad0a-251e0099f83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633063639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3633063639
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.999419405
Short name T971
Test name
Test status
Simulation time 6800891606 ps
CPU time 28.97 seconds
Started Aug 18 04:55:39 PM PDT 24
Finished Aug 18 04:56:08 PM PDT 24
Peak memory 241780 kb
Host smart-4b5029a0-3915-4bdb-b49f-4a98d2092f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999419405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.999419405
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2351626808
Short name T577
Test name
Test status
Simulation time 18684523535 ps
CPU time 23.11 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:55:56 PM PDT 24
Peak memory 238100 kb
Host smart-92a00ea5-ed3e-4b21-8c09-250732208b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351626808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2351626808
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1260758335
Short name T279
Test name
Test status
Simulation time 1838614153 ps
CPU time 7.25 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:55:43 PM PDT 24
Peak memory 233496 kb
Host smart-f12de20b-8b2d-45a2-9ed9-8f74ea966d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260758335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1260758335
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.174379494
Short name T921
Test name
Test status
Simulation time 190168821 ps
CPU time 6.52 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:55:43 PM PDT 24
Peak memory 233496 kb
Host smart-c3dea3de-9be4-433a-af16-6b6313b1061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174379494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.174379494
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.450399406
Short name T719
Test name
Test status
Simulation time 838133613 ps
CPU time 4.7 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:55:39 PM PDT 24
Peak memory 225248 kb
Host smart-8c1a831d-0d2a-4532-a302-a0de960b6fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450399406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.450399406
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1925854893
Short name T727
Test name
Test status
Simulation time 1299758505 ps
CPU time 6.49 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:55:41 PM PDT 24
Peak memory 225292 kb
Host smart-49094b92-e854-43c4-b38e-8b9e14fbb4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925854893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1925854893
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3615802482
Short name T147
Test name
Test status
Simulation time 2458770815 ps
CPU time 12.7 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:46 PM PDT 24
Peak memory 223704 kb
Host smart-fe94c8d1-7b3b-482b-b49a-9e74ecb386d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3615802482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3615802482
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2381949012
Short name T65
Test name
Test status
Simulation time 35434335497 ps
CPU time 147.63 seconds
Started Aug 18 04:55:37 PM PDT 24
Finished Aug 18 04:58:04 PM PDT 24
Peak memory 268204 kb
Host smart-1ec509cd-56fb-47ba-acd4-cde8f6151c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381949012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2381949012
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.249457377
Short name T574
Test name
Test status
Simulation time 930480404 ps
CPU time 14.05 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:55:49 PM PDT 24
Peak memory 217492 kb
Host smart-d978a4b4-3e18-42e8-8a1a-e7a5b6899168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249457377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.249457377
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.625412511
Short name T444
Test name
Test status
Simulation time 949247097 ps
CPU time 3.33 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:55:38 PM PDT 24
Peak memory 217052 kb
Host smart-7e7b7e29-76a6-4e4f-8130-c947e4776182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625412511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.625412511
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3225481722
Short name T539
Test name
Test status
Simulation time 178556701 ps
CPU time 3.72 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:55:39 PM PDT 24
Peak memory 217200 kb
Host smart-0abec05f-2246-4a9a-b638-9a317276fbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225481722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3225481722
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.608162738
Short name T822
Test name
Test status
Simulation time 97673878 ps
CPU time 1.02 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:35 PM PDT 24
Peak memory 206892 kb
Host smart-128e0e7c-c868-49b8-af36-3514f58bc860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608162738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.608162738
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3790644637
Short name T754
Test name
Test status
Simulation time 2520088703 ps
CPU time 6.22 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:55:41 PM PDT 24
Peak memory 229532 kb
Host smart-56f7631a-0df2-4101-95cf-f1f19a14f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790644637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3790644637
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1792822035
Short name T466
Test name
Test status
Simulation time 12266626 ps
CPU time 0.71 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:55:46 PM PDT 24
Peak memory 206624 kb
Host smart-920cc3ed-40b7-41b7-a215-30d8719eaacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792822035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1792822035
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2987904145
Short name T655
Test name
Test status
Simulation time 186447829 ps
CPU time 4.02 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 04:55:45 PM PDT 24
Peak memory 233600 kb
Host smart-ad100ef7-5800-4399-93ef-680a042d423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987904145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2987904145
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.140019646
Short name T89
Test name
Test status
Simulation time 76885610 ps
CPU time 0.74 seconds
Started Aug 18 04:55:35 PM PDT 24
Finished Aug 18 04:55:36 PM PDT 24
Peak memory 206348 kb
Host smart-efcf5358-f50e-493f-846e-9d48d466f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140019646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.140019646
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.715734126
Short name T940
Test name
Test status
Simulation time 8218499687 ps
CPU time 86.43 seconds
Started Aug 18 04:55:47 PM PDT 24
Finished Aug 18 04:57:13 PM PDT 24
Peak memory 257768 kb
Host smart-f76b1baa-d581-4527-bbcb-2ff121bcf442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715734126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.715734126
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.510340482
Short name T375
Test name
Test status
Simulation time 58010903498 ps
CPU time 86.23 seconds
Started Aug 18 04:55:47 PM PDT 24
Finished Aug 18 04:57:13 PM PDT 24
Peak memory 267832 kb
Host smart-d6dbfd5f-d2e6-406f-a53d-a9ba503c6cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510340482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.510340482
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2930718234
Short name T999
Test name
Test status
Simulation time 33604407208 ps
CPU time 241.48 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 04:59:43 PM PDT 24
Peak memory 258356 kb
Host smart-6541bfb2-06ad-49cf-8846-7d4b5f8ff648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930718234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2930718234
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3943768185
Short name T443
Test name
Test status
Simulation time 148850989 ps
CPU time 5.45 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:55:51 PM PDT 24
Peak memory 225360 kb
Host smart-47f845f4-d4a1-4abc-a427-a8114becdeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943768185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3943768185
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.959338487
Short name T463
Test name
Test status
Simulation time 1471542299 ps
CPU time 8.02 seconds
Started Aug 18 04:55:37 PM PDT 24
Finished Aug 18 04:55:45 PM PDT 24
Peak memory 225440 kb
Host smart-437dc12b-d57e-403b-9518-ca0e4552c913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959338487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.959338487
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1610737849
Short name T565
Test name
Test status
Simulation time 163918552 ps
CPU time 3.84 seconds
Started Aug 18 04:55:33 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 233516 kb
Host smart-893ca669-a4c8-4de5-b3fc-b617f8b3b9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610737849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1610737849
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.459602909
Short name T163
Test name
Test status
Simulation time 4343862441 ps
CPU time 4.3 seconds
Started Aug 18 04:55:34 PM PDT 24
Finished Aug 18 04:55:38 PM PDT 24
Peak memory 225476 kb
Host smart-dd440dea-c50e-4141-96c7-dc42f6b0aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459602909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.459602909
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2676968043
Short name T52
Test name
Test status
Simulation time 15183833056 ps
CPU time 12.54 seconds
Started Aug 18 04:55:38 PM PDT 24
Finished Aug 18 04:55:51 PM PDT 24
Peak memory 233600 kb
Host smart-cc8e3f81-0550-4dd7-b5b6-6cdb2b499c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676968043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2676968043
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2582301902
Short name T819
Test name
Test status
Simulation time 4543637934 ps
CPU time 9.07 seconds
Started Aug 18 04:55:42 PM PDT 24
Finished Aug 18 04:55:51 PM PDT 24
Peak memory 220244 kb
Host smart-55b9fcd7-c666-4eb0-a757-e2c5e5ca2b09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2582301902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2582301902
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1299071739
Short name T160
Test name
Test status
Simulation time 34144338818 ps
CPU time 363.2 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 05:01:45 PM PDT 24
Peak memory 256892 kb
Host smart-d3cccdbc-4382-414a-984c-323b593a0fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299071739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1299071739
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3061020659
Short name T656
Test name
Test status
Simulation time 801300546 ps
CPU time 8.38 seconds
Started Aug 18 04:55:39 PM PDT 24
Finished Aug 18 04:55:48 PM PDT 24
Peak memory 220600 kb
Host smart-b75d7c85-0c13-4b71-bee1-164c485ccd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061020659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3061020659
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1047689531
Short name T368
Test name
Test status
Simulation time 647385429 ps
CPU time 4.75 seconds
Started Aug 18 04:55:37 PM PDT 24
Finished Aug 18 04:55:42 PM PDT 24
Peak memory 217212 kb
Host smart-87e3b898-5f98-4b05-a7c1-e6006a42c1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047689531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1047689531
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3462253696
Short name T709
Test name
Test status
Simulation time 17251292 ps
CPU time 0.86 seconds
Started Aug 18 04:55:36 PM PDT 24
Finished Aug 18 04:55:37 PM PDT 24
Peak memory 207424 kb
Host smart-83fbd66c-cfee-4637-a1d1-c01a56e5d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462253696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3462253696
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.723391012
Short name T343
Test name
Test status
Simulation time 151787639 ps
CPU time 0.92 seconds
Started Aug 18 04:55:37 PM PDT 24
Finished Aug 18 04:55:38 PM PDT 24
Peak memory 206788 kb
Host smart-e7c279df-e625-4ccc-a4c7-8dcc3953a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723391012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.723391012
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2243150345
Short name T814
Test name
Test status
Simulation time 3185796903 ps
CPU time 12.45 seconds
Started Aug 18 04:55:40 PM PDT 24
Finished Aug 18 04:55:53 PM PDT 24
Peak memory 233660 kb
Host smart-134aff78-20a1-407b-ad9f-8dfe2ce590f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243150345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2243150345
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4289817154
Short name T384
Test name
Test status
Simulation time 12509290 ps
CPU time 0.7 seconds
Started Aug 18 04:55:46 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 206148 kb
Host smart-e3c0f06b-15f6-43da-84c1-12acdbb1f194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289817154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4289817154
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.129921165
Short name T692
Test name
Test status
Simulation time 93596452 ps
CPU time 2.13 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 225292 kb
Host smart-f8c4bbb0-2e91-4501-bea3-4b52148873c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129921165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.129921165
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.794807732
Short name T815
Test name
Test status
Simulation time 25999213 ps
CPU time 0.75 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:55:46 PM PDT 24
Peak memory 206324 kb
Host smart-33ab1611-2308-4974-aa9a-4c8eec044abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794807732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.794807732
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1679677359
Short name T768
Test name
Test status
Simulation time 6938538056 ps
CPU time 14.69 seconds
Started Aug 18 04:55:43 PM PDT 24
Finished Aug 18 04:55:57 PM PDT 24
Peak memory 235316 kb
Host smart-3d04b599-e119-4930-a055-cd69aa72df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679677359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1679677359
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.196984394
Short name T572
Test name
Test status
Simulation time 4750953778 ps
CPU time 47.01 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 04:56:29 PM PDT 24
Peak memory 233828 kb
Host smart-e5fead68-d80a-49ac-b862-7bbb12771fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196984394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.196984394
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3506037109
Short name T94
Test name
Test status
Simulation time 29730376751 ps
CPU time 233.73 seconds
Started Aug 18 04:55:44 PM PDT 24
Finished Aug 18 04:59:38 PM PDT 24
Peak memory 255556 kb
Host smart-1a4904d3-147b-418c-b567-c93d5dd08e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506037109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3506037109
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1725965521
Short name T972
Test name
Test status
Simulation time 654922904 ps
CPU time 10.3 seconds
Started Aug 18 04:55:44 PM PDT 24
Finished Aug 18 04:55:55 PM PDT 24
Peak memory 225332 kb
Host smart-eb84adc3-9690-4a8d-ac58-aa424db2296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725965521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1725965521
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1227540895
Short name T871
Test name
Test status
Simulation time 711366777762 ps
CPU time 233.86 seconds
Started Aug 18 04:55:44 PM PDT 24
Finished Aug 18 04:59:38 PM PDT 24
Peak memory 251840 kb
Host smart-a2880af4-97aa-4f27-99ac-563310c93922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227540895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1227540895
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3952490628
Short name T589
Test name
Test status
Simulation time 121592920 ps
CPU time 2.43 seconds
Started Aug 18 04:55:44 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 233196 kb
Host smart-15755f3e-06ea-4f22-b1c0-11742c4099e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952490628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3952490628
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2715141064
Short name T199
Test name
Test status
Simulation time 7049477665 ps
CPU time 34.31 seconds
Started Aug 18 04:55:46 PM PDT 24
Finished Aug 18 04:56:21 PM PDT 24
Peak memory 225516 kb
Host smart-1c6dda73-6807-4ed2-a16b-6bdd5439208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715141064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2715141064
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1308955231
Short name T496
Test name
Test status
Simulation time 5101234053 ps
CPU time 6.37 seconds
Started Aug 18 04:55:43 PM PDT 24
Finished Aug 18 04:55:50 PM PDT 24
Peak memory 225428 kb
Host smart-a712fc6b-264e-41f2-9eda-4f7946856488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308955231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1308955231
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3145570406
Short name T924
Test name
Test status
Simulation time 1918088685 ps
CPU time 4.74 seconds
Started Aug 18 04:55:43 PM PDT 24
Finished Aug 18 04:55:48 PM PDT 24
Peak memory 225256 kb
Host smart-2b695171-281c-49c9-a6da-66c06e0c4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145570406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3145570406
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3163356983
Short name T575
Test name
Test status
Simulation time 807996369 ps
CPU time 4.85 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 04:55:46 PM PDT 24
Peak memory 220868 kb
Host smart-de292b9a-f0e6-4ef6-b5c6-53e60ae702f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163356983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3163356983
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2045032522
Short name T185
Test name
Test status
Simulation time 67915660322 ps
CPU time 251.72 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 04:59:53 PM PDT 24
Peak memory 252824 kb
Host smart-fd1d3d49-b039-4f3a-ad99-3d6ba8493fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045032522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2045032522
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2091444693
Short name T6
Test name
Test status
Simulation time 6376343063 ps
CPU time 20.61 seconds
Started Aug 18 04:55:41 PM PDT 24
Finished Aug 18 04:56:02 PM PDT 24
Peak memory 217332 kb
Host smart-16b2bcd2-2bd7-40f3-9a41-01b2b49e834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091444693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2091444693
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2072303675
Short name T808
Test name
Test status
Simulation time 861573628 ps
CPU time 2.4 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 217084 kb
Host smart-d283d2ed-1749-4b95-b066-53439ff73a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072303675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2072303675
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1155215971
Short name T27
Test name
Test status
Simulation time 89676874 ps
CPU time 1.33 seconds
Started Aug 18 04:55:42 PM PDT 24
Finished Aug 18 04:55:44 PM PDT 24
Peak memory 208776 kb
Host smart-43789854-aa1e-46ce-bb27-d7d32e5e86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155215971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1155215971
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3095356841
Short name T434
Test name
Test status
Simulation time 48578009 ps
CPU time 0.81 seconds
Started Aug 18 04:55:46 PM PDT 24
Finished Aug 18 04:55:47 PM PDT 24
Peak memory 206820 kb
Host smart-eadb98fa-911f-40c1-a7cd-ab723b6b1179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095356841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3095356841
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1889570488
Short name T535
Test name
Test status
Simulation time 14646741937 ps
CPU time 20.06 seconds
Started Aug 18 04:55:45 PM PDT 24
Finished Aug 18 04:56:05 PM PDT 24
Peak memory 225380 kb
Host smart-6a0f9eb2-e1f3-46bb-8f8a-7118749d7182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889570488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1889570488
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3555548226
Short name T906
Test name
Test status
Simulation time 99929100 ps
CPU time 0.69 seconds
Started Aug 18 04:55:50 PM PDT 24
Finished Aug 18 04:55:51 PM PDT 24
Peak memory 205712 kb
Host smart-580e72c5-671f-4dfa-84ae-a222a87652a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555548226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3555548226
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3320042258
Short name T867
Test name
Test status
Simulation time 410350893 ps
CPU time 2.99 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:55:55 PM PDT 24
Peak memory 225224 kb
Host smart-b93f7b02-9875-4b4a-8f90-158db4116853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320042258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3320042258
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1258424853
Short name T584
Test name
Test status
Simulation time 20807236 ps
CPU time 0.75 seconds
Started Aug 18 04:55:43 PM PDT 24
Finished Aug 18 04:55:44 PM PDT 24
Peak memory 207700 kb
Host smart-6d7e4bc7-815d-47e4-bee1-25d1517ab61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258424853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1258424853
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1566882033
Short name T232
Test name
Test status
Simulation time 4427406075 ps
CPU time 58.97 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:56:51 PM PDT 24
Peak memory 249980 kb
Host smart-7a3dcadf-35bc-4365-87b0-d58f342a4dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566882033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1566882033
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1448094265
Short name T596
Test name
Test status
Simulation time 4973069634 ps
CPU time 46.41 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 233696 kb
Host smart-974c675b-8bc4-4e5c-8376-62967e6caa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448094265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1448094265
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2568774778
Short name T654
Test name
Test status
Simulation time 5517637093 ps
CPU time 43.17 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 240440 kb
Host smart-264782c8-32cb-4209-95a9-fdf1afae18d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568774778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2568774778
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.970049498
Short name T757
Test name
Test status
Simulation time 476948379 ps
CPU time 7.57 seconds
Started Aug 18 04:55:53 PM PDT 24
Finished Aug 18 04:56:00 PM PDT 24
Peak memory 236648 kb
Host smart-434a6a2a-e93d-43f6-900b-8bebeb8c9cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970049498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.970049498
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2416998476
Short name T103
Test name
Test status
Simulation time 21680668141 ps
CPU time 177.49 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:58:52 PM PDT 24
Peak memory 255696 kb
Host smart-2c73bf8d-f7bd-4c5b-89df-006342f3370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416998476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2416998476
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.188480426
Short name T922
Test name
Test status
Simulation time 213021002 ps
CPU time 5.01 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:55:57 PM PDT 24
Peak memory 233608 kb
Host smart-03221e4a-50f2-4304-ab06-fb0d423c33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188480426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.188480426
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.908073520
Short name T273
Test name
Test status
Simulation time 2682241432 ps
CPU time 33.17 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:56:27 PM PDT 24
Peak memory 241576 kb
Host smart-79eff00b-82e6-4e14-9a19-62ff17585dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908073520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.908073520
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2817421813
Short name T896
Test name
Test status
Simulation time 7378281323 ps
CPU time 21.54 seconds
Started Aug 18 04:55:50 PM PDT 24
Finished Aug 18 04:56:11 PM PDT 24
Peak memory 233592 kb
Host smart-e49a06be-1695-487e-aa35-3a9bfd419528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817421813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2817421813
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.309115290
Short name T382
Test name
Test status
Simulation time 6835298210 ps
CPU time 5.75 seconds
Started Aug 18 04:55:55 PM PDT 24
Finished Aug 18 04:56:01 PM PDT 24
Peak memory 225404 kb
Host smart-b393a7b9-3d53-4036-8e35-b67999ae2ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309115290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.309115290
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4027153779
Short name T369
Test name
Test status
Simulation time 762170944 ps
CPU time 10.83 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:56:03 PM PDT 24
Peak memory 222852 kb
Host smart-ad66f047-0e76-4055-9bfc-63f3df1a42ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4027153779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4027153779
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1238569273
Short name T951
Test name
Test status
Simulation time 67142887246 ps
CPU time 70.51 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:57:02 PM PDT 24
Peak memory 250132 kb
Host smart-8ed25693-eda8-459c-b4ed-e869259cdb68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238569273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1238569273
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1228380134
Short name T490
Test name
Test status
Simulation time 876091896 ps
CPU time 5.52 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:55:58 PM PDT 24
Peak memory 217116 kb
Host smart-f90b10af-4dcb-4d4a-b1f8-a24e47d5b106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228380134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1228380134
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.50443905
Short name T941
Test name
Test status
Simulation time 7681275780 ps
CPU time 7.33 seconds
Started Aug 18 04:55:42 PM PDT 24
Finished Aug 18 04:55:50 PM PDT 24
Peak memory 217332 kb
Host smart-80d166e0-61f2-43d5-b0aa-c41c0ca30bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50443905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.50443905
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3514736949
Short name T415
Test name
Test status
Simulation time 152274998 ps
CPU time 2.16 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:55:53 PM PDT 24
Peak memory 217060 kb
Host smart-253d7e95-1fd7-496e-966b-fb30af5b0146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514736949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3514736949
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2307476792
Short name T356
Test name
Test status
Simulation time 29962868 ps
CPU time 0.73 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:55:55 PM PDT 24
Peak memory 206772 kb
Host smart-2b4b10e7-0ab2-44e6-8a87-101740aec24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307476792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2307476792
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.241148506
Short name T809
Test name
Test status
Simulation time 65062309 ps
CPU time 2.17 seconds
Started Aug 18 04:55:53 PM PDT 24
Finished Aug 18 04:55:55 PM PDT 24
Peak memory 224872 kb
Host smart-8aead123-fe8b-4624-b152-4b236af8e037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241148506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.241148506
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1268715679
Short name T519
Test name
Test status
Simulation time 11856152 ps
CPU time 0.72 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:03 PM PDT 24
Peak memory 206160 kb
Host smart-2ed7280a-91b9-49fe-b5e8-d80df11aac36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268715679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1268715679
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4290521897
Short name T365
Test name
Test status
Simulation time 1455406205 ps
CPU time 7.83 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:56:02 PM PDT 24
Peak memory 233516 kb
Host smart-f5e8fb56-b8f9-436b-8c79-14fb656d0319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290521897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4290521897
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3029567316
Short name T359
Test name
Test status
Simulation time 21116102 ps
CPU time 0.8 seconds
Started Aug 18 04:55:53 PM PDT 24
Finished Aug 18 04:55:54 PM PDT 24
Peak memory 207284 kb
Host smart-6d195aa2-774a-499f-a5ea-9a860231dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029567316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3029567316
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2279872570
Short name T831
Test name
Test status
Simulation time 2437815664 ps
CPU time 33.18 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:36 PM PDT 24
Peak memory 250100 kb
Host smart-a6835b4b-2324-412c-b6bd-e48829d312ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279872570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2279872570
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1074447204
Short name T194
Test name
Test status
Simulation time 33325402183 ps
CPU time 260.81 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 05:00:24 PM PDT 24
Peak memory 266408 kb
Host smart-b0612d5f-421f-4a82-9ac2-098021a53efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074447204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1074447204
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4073494697
Short name T197
Test name
Test status
Simulation time 306701819484 ps
CPU time 670.77 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 05:07:12 PM PDT 24
Peak memory 266612 kb
Host smart-8186347b-f2ef-424c-bea6-85fa5fa9436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073494697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4073494697
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1700290493
Short name T308
Test name
Test status
Simulation time 4161515600 ps
CPU time 14.24 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 253148 kb
Host smart-2948fe02-5de7-4da3-b39d-5cb0909c3de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700290493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1700290493
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.247140651
Short name T501
Test name
Test status
Simulation time 806313870 ps
CPU time 7.5 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:55:59 PM PDT 24
Peak memory 225216 kb
Host smart-f548006a-b66e-4f4d-b79d-21d8d905e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247140651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.247140651
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2832172293
Short name T255
Test name
Test status
Simulation time 23604825036 ps
CPU time 44.56 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:56:39 PM PDT 24
Peak memory 241028 kb
Host smart-5d9cb96a-dce9-4165-9f39-e1bf56249358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832172293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2832172293
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3383666468
Short name T964
Test name
Test status
Simulation time 3072776631 ps
CPU time 9.83 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:56:02 PM PDT 24
Peak memory 233700 kb
Host smart-fc455169-b864-41f3-92dc-e4cbbe25071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383666468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3383666468
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3298605913
Short name T330
Test name
Test status
Simulation time 29844163 ps
CPU time 2.14 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:55:53 PM PDT 24
Peak memory 224448 kb
Host smart-1a8bbc2a-5be8-4b55-a822-f7fb3d566919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298605913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3298605913
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3594621012
Short name T417
Test name
Test status
Simulation time 1739508612 ps
CPU time 5.16 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:08 PM PDT 24
Peak memory 223980 kb
Host smart-2950441c-0986-485c-817a-160bd3f6f44a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3594621012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3594621012
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1971362986
Short name T1000
Test name
Test status
Simulation time 13425117648 ps
CPU time 171.39 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:58:55 PM PDT 24
Peak memory 272752 kb
Host smart-58c23a84-4037-40b2-8c15-776e253f15a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971362986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1971362986
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2671416551
Short name T328
Test name
Test status
Simulation time 5405253754 ps
CPU time 15.09 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 217544 kb
Host smart-f571e162-fcd1-4a96-ba7d-a8b249077119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671416551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2671416551
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.55424850
Short name T619
Test name
Test status
Simulation time 3223923459 ps
CPU time 1.51 seconds
Started Aug 18 04:55:52 PM PDT 24
Finished Aug 18 04:55:54 PM PDT 24
Peak memory 208512 kb
Host smart-e82af076-8568-4bb8-92d2-2888c59c60a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55424850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.55424850
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2403061699
Short name T327
Test name
Test status
Simulation time 296809369 ps
CPU time 1.37 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:55:52 PM PDT 24
Peak memory 217204 kb
Host smart-1161bc13-af0c-4093-800c-918cf604d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403061699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2403061699
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1127112550
Short name T348
Test name
Test status
Simulation time 271509921 ps
CPU time 0.81 seconds
Started Aug 18 04:55:51 PM PDT 24
Finished Aug 18 04:55:52 PM PDT 24
Peak memory 206828 kb
Host smart-be91408c-9701-4152-8f56-638b81489e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127112550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1127112550
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2015456472
Short name T422
Test name
Test status
Simulation time 176888864 ps
CPU time 2.94 seconds
Started Aug 18 04:55:54 PM PDT 24
Finished Aug 18 04:55:57 PM PDT 24
Peak memory 225324 kb
Host smart-36297ab8-7d60-4393-9b9a-d694ced8bcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015456472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2015456472
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1029280901
Short name T465
Test name
Test status
Simulation time 14548458 ps
CPU time 0.73 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 04:56:02 PM PDT 24
Peak memory 206508 kb
Host smart-7960ac54-c818-4b41-be3c-aa40fbfb047e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029280901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1029280901
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3627699818
Short name T903
Test name
Test status
Simulation time 322003196 ps
CPU time 3.14 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 225292 kb
Host smart-296c7027-a7bd-459e-96e8-5aff153606a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627699818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3627699818
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1475197691
Short name T376
Test name
Test status
Simulation time 27662380 ps
CPU time 0.85 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:04 PM PDT 24
Peak memory 207428 kb
Host smart-2339a9ab-593c-489d-af11-33b742561e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475197691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1475197691
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.157348344
Short name T266
Test name
Test status
Simulation time 45706247342 ps
CPU time 203.33 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 04:59:25 PM PDT 24
Peak memory 273568 kb
Host smart-9b03c9ec-fa34-4bd3-bad6-a99782f0443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157348344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.157348344
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1734536090
Short name T683
Test name
Test status
Simulation time 50865562649 ps
CPU time 188.51 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:59:12 PM PDT 24
Peak memory 268796 kb
Host smart-dd5ee77d-cedc-4ca4-ae59-51af64a12a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734536090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1734536090
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1630242524
Short name T231
Test name
Test status
Simulation time 137661792164 ps
CPU time 341.15 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 05:01:43 PM PDT 24
Peak memory 261420 kb
Host smart-ee6ee96d-4ef7-442c-b442-779d64ba4620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630242524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1630242524
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.550231209
Short name T309
Test name
Test status
Simulation time 1285504472 ps
CPU time 9.34 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:12 PM PDT 24
Peak memory 234580 kb
Host smart-90a7aee9-433d-499b-afc3-9075d91a0241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550231209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.550231209
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.240634379
Short name T181
Test name
Test status
Simulation time 2378368305 ps
CPU time 6.55 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:09 PM PDT 24
Peak memory 225524 kb
Host smart-19f233f1-7011-4a39-b40d-38339641f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240634379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.240634379
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3245715863
Short name T836
Test name
Test status
Simulation time 879285992 ps
CPU time 8.51 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:11 PM PDT 24
Peak memory 233576 kb
Host smart-9a9928b7-a154-4f62-973b-534f2722bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245715863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3245715863
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1398729595
Short name T778
Test name
Test status
Simulation time 3853280536 ps
CPU time 17.44 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:20 PM PDT 24
Peak memory 237472 kb
Host smart-ea64978f-adcc-446d-8c7f-2335b1c7da92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398729595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1398729595
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.17114893
Short name T851
Test name
Test status
Simulation time 322874377 ps
CPU time 3.16 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:07 PM PDT 24
Peak memory 225280 kb
Host smart-b7ef55b3-c64a-4513-84b7-e0b6ff043ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17114893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.17114893
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4100703205
Short name T244
Test name
Test status
Simulation time 14554437146 ps
CPU time 42.32 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 251840 kb
Host smart-7bc5ddf6-530f-4a03-a5ad-053937eabcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100703205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4100703205
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2486506353
Short name T145
Test name
Test status
Simulation time 532269627 ps
CPU time 7.56 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:11 PM PDT 24
Peak memory 220788 kb
Host smart-6c1ec04f-fd60-4d0c-82b9-241160f9e6b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2486506353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2486506353
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.352900122
Short name T515
Test name
Test status
Simulation time 63211445 ps
CPU time 1.13 seconds
Started Aug 18 04:56:08 PM PDT 24
Finished Aug 18 04:56:10 PM PDT 24
Peak memory 207956 kb
Host smart-e2f90b66-1cee-4b6d-a016-772087c4af88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352900122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.352900122
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.593699861
Short name T426
Test name
Test status
Simulation time 3752018973 ps
CPU time 18.34 seconds
Started Aug 18 04:56:01 PM PDT 24
Finished Aug 18 04:56:20 PM PDT 24
Peak memory 217364 kb
Host smart-f0f4a51f-58a9-4bc8-a798-675c03d46cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593699861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.593699861
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2796600750
Short name T703
Test name
Test status
Simulation time 2076562287 ps
CPU time 11.22 seconds
Started Aug 18 04:56:05 PM PDT 24
Finished Aug 18 04:56:16 PM PDT 24
Peak memory 217152 kb
Host smart-1da3f8c3-af19-4f51-a78c-dd2eedfe88d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796600750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2796600750
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.840274893
Short name T495
Test name
Test status
Simulation time 139595931 ps
CPU time 0.74 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:04 PM PDT 24
Peak memory 206336 kb
Host smart-f66fe4be-e098-4a36-9ed4-e9eb8cb9c8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840274893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.840274893
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.477138306
Short name T164
Test name
Test status
Simulation time 211661897 ps
CPU time 0.84 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:05 PM PDT 24
Peak memory 206828 kb
Host smart-f0b0ad82-9cd0-4338-bf37-6b9fbe2c532b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477138306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.477138306
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3664790872
Short name T211
Test name
Test status
Simulation time 14663653395 ps
CPU time 29 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 233720 kb
Host smart-43a6f608-b95e-4ce4-aadb-07df46b39e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664790872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3664790872
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.87309329
Short name T45
Test name
Test status
Simulation time 39770428 ps
CPU time 0.74 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:14 PM PDT 24
Peak memory 205704 kb
Host smart-c734eb2c-c9f6-4340-86fe-243959027117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87309329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.87309329
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3793805173
Short name T862
Test name
Test status
Simulation time 43217815 ps
CPU time 2.62 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:07 PM PDT 24
Peak memory 233600 kb
Host smart-01103f84-3b4b-4949-bc58-7f706d950ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793805173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3793805173
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.815047842
Short name T816
Test name
Test status
Simulation time 16322247 ps
CPU time 0.8 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:04 PM PDT 24
Peak memory 206388 kb
Host smart-fc27552a-a29c-44c4-b95d-8b62e8ac31b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815047842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.815047842
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3888144802
Short name T201
Test name
Test status
Simulation time 357667653729 ps
CPU time 594.14 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 05:05:57 PM PDT 24
Peak memory 266448 kb
Host smart-a00ad401-5a2e-403a-9da0-6d594e569ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888144802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3888144802
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1248803248
Short name T222
Test name
Test status
Simulation time 11999249519 ps
CPU time 30.67 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:43 PM PDT 24
Peak memory 242020 kb
Host smart-33783069-ceb6-417e-84a6-725ad538faf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248803248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1248803248
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.293810425
Short name T457
Test name
Test status
Simulation time 228907325 ps
CPU time 3.07 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 233568 kb
Host smart-de63df20-b8ab-423b-b61b-25bd8937bfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293810425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.293810425
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4002807646
Short name T861
Test name
Test status
Simulation time 4300151912 ps
CPU time 51.99 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:57 PM PDT 24
Peak memory 251104 kb
Host smart-65baf645-12fb-43c3-91d1-6015496271ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002807646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4002807646
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3413768686
Short name T87
Test name
Test status
Simulation time 6578122962 ps
CPU time 17.17 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:20 PM PDT 24
Peak memory 233904 kb
Host smart-423d9eaf-a140-4580-b989-0f3477638eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413768686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3413768686
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2682940913
Short name T899
Test name
Test status
Simulation time 8417089779 ps
CPU time 28.24 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:32 PM PDT 24
Peak memory 241556 kb
Host smart-dca02597-71af-4606-957a-7b934998dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682940913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2682940913
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3644755324
Short name T271
Test name
Test status
Simulation time 10596339639 ps
CPU time 13.1 seconds
Started Aug 18 04:56:08 PM PDT 24
Finished Aug 18 04:56:22 PM PDT 24
Peak memory 225488 kb
Host smart-ba2f34e4-7ce9-4c40-9bc4-a4b92adb0442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644755324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3644755324
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2768648310
Short name T498
Test name
Test status
Simulation time 30885919 ps
CPU time 2.16 seconds
Started Aug 18 04:56:03 PM PDT 24
Finished Aug 18 04:56:06 PM PDT 24
Peak memory 224300 kb
Host smart-522a4b26-2ce7-4692-8913-b2d4b81f5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768648310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2768648310
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.650430808
Short name T548
Test name
Test status
Simulation time 923624122 ps
CPU time 7.25 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:09 PM PDT 24
Peak memory 223816 kb
Host smart-def73e44-15eb-45ea-a332-9cca8b784ec5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650430808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.650430808
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2930460498
Short name T478
Test name
Test status
Simulation time 264700411177 ps
CPU time 263.94 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 05:00:36 PM PDT 24
Peak memory 258344 kb
Host smart-78f3285e-9f2c-4621-bbf8-ed9647cc169f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930460498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2930460498
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3487454611
Short name T812
Test name
Test status
Simulation time 2188643772 ps
CPU time 28.41 seconds
Started Aug 18 04:56:04 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 221608 kb
Host smart-97260f8e-c671-4e6c-a93f-c495f276b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487454611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3487454611
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2350500587
Short name T742
Test name
Test status
Simulation time 10054296636 ps
CPU time 14.64 seconds
Started Aug 18 04:56:08 PM PDT 24
Finished Aug 18 04:56:22 PM PDT 24
Peak memory 217244 kb
Host smart-71b246f0-ccbf-4731-b1f4-db4094d33d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350500587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2350500587
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2979005998
Short name T734
Test name
Test status
Simulation time 17685765 ps
CPU time 0.83 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:03 PM PDT 24
Peak memory 206760 kb
Host smart-6833dc0d-95c2-421f-906d-1443633c925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979005998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2979005998
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.20827932
Short name T928
Test name
Test status
Simulation time 834765539 ps
CPU time 0.94 seconds
Started Aug 18 04:56:08 PM PDT 24
Finished Aug 18 04:56:09 PM PDT 24
Peak memory 206848 kb
Host smart-62262369-4e68-4656-952a-4d6a4091bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20827932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.20827932
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3344414375
Short name T737
Test name
Test status
Simulation time 1686271223 ps
CPU time 8.12 seconds
Started Aug 18 04:56:02 PM PDT 24
Finished Aug 18 04:56:11 PM PDT 24
Peak memory 233628 kb
Host smart-caff9cef-f83f-4afb-93ef-91876541301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344414375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3344414375
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1052763238
Short name T357
Test name
Test status
Simulation time 44815928 ps
CPU time 0.72 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:53:46 PM PDT 24
Peak memory 206760 kb
Host smart-e9530844-e1d2-403c-8a32-c1bb21fecb00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052763238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
052763238
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3497329471
Short name T252
Test name
Test status
Simulation time 1751565861 ps
CPU time 8.32 seconds
Started Aug 18 04:53:43 PM PDT 24
Finished Aug 18 04:53:51 PM PDT 24
Peak memory 233636 kb
Host smart-516d2cae-af73-4379-a40e-91617c02700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497329471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3497329471
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3369593489
Short name T684
Test name
Test status
Simulation time 58962986 ps
CPU time 0.78 seconds
Started Aug 18 04:53:34 PM PDT 24
Finished Aug 18 04:53:35 PM PDT 24
Peak memory 207328 kb
Host smart-cfccaf41-fbb0-4dc3-bbbf-75b4b5e929d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369593489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3369593489
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3843550935
Short name T204
Test name
Test status
Simulation time 51694468783 ps
CPU time 373.06 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:59:58 PM PDT 24
Peak memory 271252 kb
Host smart-b6f64173-4971-46cf-8642-86207329b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843550935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3843550935
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1940628206
Short name T458
Test name
Test status
Simulation time 2920952963 ps
CPU time 32.24 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 233756 kb
Host smart-808677f5-a341-45b6-8915-bab047cc6ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940628206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1940628206
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2419869092
Short name T142
Test name
Test status
Simulation time 74667180988 ps
CPU time 179.74 seconds
Started Aug 18 04:53:46 PM PDT 24
Finished Aug 18 04:56:46 PM PDT 24
Peak memory 268508 kb
Host smart-1df8e1c5-7800-4748-9a95-cc3ba1c0243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419869092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2419869092
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3567249340
Short name T306
Test name
Test status
Simulation time 66479838570 ps
CPU time 40.48 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:54:25 PM PDT 24
Peak memory 233684 kb
Host smart-4ddb0467-7828-4f78-a05c-a78e61e1fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567249340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3567249340
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.41740331
Short name T665
Test name
Test status
Simulation time 42231566153 ps
CPU time 287.2 seconds
Started Aug 18 04:53:47 PM PDT 24
Finished Aug 18 04:58:34 PM PDT 24
Peak memory 254616 kb
Host smart-af54f8da-3779-4cdb-8d1e-aca6b7230b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41740331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.41740331
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1696426904
Short name T884
Test name
Test status
Simulation time 575161969 ps
CPU time 3.26 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:47 PM PDT 24
Peak memory 233540 kb
Host smart-0ae516a5-63c1-4b55-a581-2cac1641628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696426904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1696426904
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3366361590
Short name T513
Test name
Test status
Simulation time 598063704 ps
CPU time 3.47 seconds
Started Aug 18 04:53:46 PM PDT 24
Finished Aug 18 04:53:49 PM PDT 24
Peak memory 225360 kb
Host smart-4a320845-505c-45dc-b3a7-296d54ce2922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366361590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3366361590
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.834425073
Short name T521
Test name
Test status
Simulation time 235603960 ps
CPU time 5.13 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:53:50 PM PDT 24
Peak memory 233524 kb
Host smart-f6dcf053-8792-4ec2-baa0-39f228eafb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834425073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
834425073
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2199642527
Short name T630
Test name
Test status
Simulation time 277684526 ps
CPU time 5.52 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:50 PM PDT 24
Peak memory 233456 kb
Host smart-713d10d3-33f7-4254-858a-029e70a459a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199642527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2199642527
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2926350695
Short name T826
Test name
Test status
Simulation time 1261077933 ps
CPU time 5.33 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:50 PM PDT 24
Peak memory 223972 kb
Host smart-a2825cae-7354-48b4-942a-50af64567ead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2926350695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2926350695
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4023663732
Short name T84
Test name
Test status
Simulation time 117785077 ps
CPU time 1.02 seconds
Started Aug 18 04:53:43 PM PDT 24
Finished Aug 18 04:53:44 PM PDT 24
Peak memory 237168 kb
Host smart-b0faa01e-86c3-4331-a78b-17ebd200fef1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023663732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4023663732
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1430421908
Short name T33
Test name
Test status
Simulation time 19791410360 ps
CPU time 194.38 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 250108 kb
Host smart-bde90c78-84ac-4522-b079-8634682ea757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430421908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1430421908
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3895148715
Short name T311
Test name
Test status
Simulation time 11357486783 ps
CPU time 18.19 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:54:04 PM PDT 24
Peak memory 217668 kb
Host smart-c2394eb6-a942-41ba-953d-2ed3ac2cc9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895148715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3895148715
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.868961844
Short name T351
Test name
Test status
Simulation time 5018889581 ps
CPU time 8.89 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:53 PM PDT 24
Peak memory 217220 kb
Host smart-2d8c9ceb-f911-4e74-a613-aac13e5cf9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868961844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.868961844
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.502071698
Short name T853
Test name
Test status
Simulation time 114169355 ps
CPU time 1.02 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:45 PM PDT 24
Peak memory 208004 kb
Host smart-1a96ebb1-8b5b-4f85-b7e5-51d58cc9101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502071698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.502071698
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3998647775
Short name T381
Test name
Test status
Simulation time 97378066 ps
CPU time 0.93 seconds
Started Aug 18 04:53:47 PM PDT 24
Finished Aug 18 04:53:48 PM PDT 24
Peak memory 207836 kb
Host smart-8011a102-1446-4b12-9a24-22df3a8e4323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998647775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3998647775
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.747236077
Short name T212
Test name
Test status
Simulation time 53015776459 ps
CPU time 32.88 seconds
Started Aug 18 04:53:47 PM PDT 24
Finished Aug 18 04:54:20 PM PDT 24
Peak memory 225468 kb
Host smart-26f6c3ed-bb2e-4509-8167-99622aceaf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747236077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.747236077
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2559914398
Short name T889
Test name
Test status
Simulation time 76928962 ps
CPU time 0.71 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:14 PM PDT 24
Peak memory 206268 kb
Host smart-38cfe072-eab0-4224-87e9-cd3a68413a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559914398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2559914398
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3221780161
Short name T250
Test name
Test status
Simulation time 5371610114 ps
CPU time 13.82 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:26 PM PDT 24
Peak memory 233572 kb
Host smart-5d307e12-6af9-4f50-afa5-bc2b7ce7555e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221780161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3221780161
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2575024024
Short name T600
Test name
Test status
Simulation time 75547352 ps
CPU time 0.81 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:13 PM PDT 24
Peak memory 207432 kb
Host smart-39c26828-426b-4e53-a3c7-d58cce2f009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575024024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2575024024
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3775728843
Short name T833
Test name
Test status
Simulation time 45908289616 ps
CPU time 159.03 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:58:52 PM PDT 24
Peak memory 250008 kb
Host smart-92c7d48f-c069-4d04-8758-9121eeba7e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775728843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3775728843
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3625860431
Short name T997
Test name
Test status
Simulation time 31573485138 ps
CPU time 41.59 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:54 PM PDT 24
Peak memory 250652 kb
Host smart-533eb755-157a-47d7-b73d-0a8aae29df3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625860431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3625860431
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2082804264
Short name T319
Test name
Test status
Simulation time 6930344142 ps
CPU time 27.55 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:40 PM PDT 24
Peak memory 240428 kb
Host smart-1c36e6fc-5c8e-4f25-8a3d-ab685bb4ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082804264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2082804264
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3405718327
Short name T420
Test name
Test status
Simulation time 1359800078 ps
CPU time 8.86 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:22 PM PDT 24
Peak memory 233604 kb
Host smart-f0298d74-b4b5-45d3-98de-319bba8fe21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405718327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3405718327
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.504572016
Short name T687
Test name
Test status
Simulation time 8702917575 ps
CPU time 61.04 seconds
Started Aug 18 04:56:15 PM PDT 24
Finished Aug 18 04:57:16 PM PDT 24
Peak memory 234700 kb
Host smart-fd01588a-4ce9-4093-bb31-52028fa3cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504572016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.504572016
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2222652242
Short name T661
Test name
Test status
Simulation time 361820439 ps
CPU time 5.92 seconds
Started Aug 18 04:56:14 PM PDT 24
Finished Aug 18 04:56:20 PM PDT 24
Peak memory 225308 kb
Host smart-e1f3d296-7289-47d2-84da-c4651b59d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222652242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2222652242
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.846218394
Short name T647
Test name
Test status
Simulation time 4107358170 ps
CPU time 7.39 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:19 PM PDT 24
Peak memory 225372 kb
Host smart-ba2ab2c6-f684-4f78-ad62-1ba62f6e4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846218394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.846218394
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.880115667
Short name T722
Test name
Test status
Simulation time 48575425764 ps
CPU time 39.09 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:51 PM PDT 24
Peak memory 249948 kb
Host smart-7dc8287b-c4fd-4494-a93b-9685ebd95bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880115667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.880115667
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.579691516
Short name T832
Test name
Test status
Simulation time 43737441 ps
CPU time 2.5 seconds
Started Aug 18 04:56:14 PM PDT 24
Finished Aug 18 04:56:17 PM PDT 24
Peak memory 233528 kb
Host smart-6b0afda6-7040-409a-aded-254158af0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579691516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.579691516
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3799182358
Short name T42
Test name
Test status
Simulation time 210289189869 ps
CPU time 463.64 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 05:03:56 PM PDT 24
Peak memory 269440 kb
Host smart-202f23e5-d4e5-4359-9297-93cd08897084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799182358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3799182358
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1275978055
Short name T943
Test name
Test status
Simulation time 4986306562 ps
CPU time 34.36 seconds
Started Aug 18 04:56:14 PM PDT 24
Finished Aug 18 04:56:48 PM PDT 24
Peak memory 217304 kb
Host smart-a0f66972-4284-48bc-9f2c-2bcf80052897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275978055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1275978055
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2850874840
Short name T623
Test name
Test status
Simulation time 5376102152 ps
CPU time 13.7 seconds
Started Aug 18 04:56:16 PM PDT 24
Finished Aug 18 04:56:30 PM PDT 24
Peak memory 217252 kb
Host smart-bcea351c-c697-48d2-ba41-d722bbe202e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850874840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2850874840
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1652645420
Short name T841
Test name
Test status
Simulation time 293620393 ps
CPU time 1.62 seconds
Started Aug 18 04:56:14 PM PDT 24
Finished Aug 18 04:56:16 PM PDT 24
Peak memory 217136 kb
Host smart-8c5c3202-9d54-42bd-906f-630c83cfdfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652645420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1652645420
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.624511593
Short name T597
Test name
Test status
Simulation time 152604126 ps
CPU time 1.09 seconds
Started Aug 18 04:56:13 PM PDT 24
Finished Aug 18 04:56:14 PM PDT 24
Peak memory 207220 kb
Host smart-010d9f16-50a9-437a-bd1a-55280dec7f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624511593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.624511593
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.291095893
Short name T421
Test name
Test status
Simulation time 1240570870 ps
CPU time 11.99 seconds
Started Aug 18 04:56:11 PM PDT 24
Finished Aug 18 04:56:23 PM PDT 24
Peak memory 233400 kb
Host smart-498201a6-e5cf-4d38-9a8d-89442c669f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291095893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.291095893
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4218152969
Short name T470
Test name
Test status
Simulation time 12471227 ps
CPU time 0.71 seconds
Started Aug 18 04:56:31 PM PDT 24
Finished Aug 18 04:56:32 PM PDT 24
Peak memory 205644 kb
Host smart-1dec94cf-47cb-4fb8-a9ad-039d800f92c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218152969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4218152969
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1930213933
Short name T353
Test name
Test status
Simulation time 1084414293 ps
CPU time 4.69 seconds
Started Aug 18 04:56:32 PM PDT 24
Finished Aug 18 04:56:37 PM PDT 24
Peak memory 225444 kb
Host smart-278b6961-0f12-4efc-aaa8-aec42e202124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930213933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1930213933
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1251200573
Short name T393
Test name
Test status
Simulation time 84414566 ps
CPU time 0.8 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:13 PM PDT 24
Peak memory 207432 kb
Host smart-cde2f193-a381-4674-9c41-ee00f9b80d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251200573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1251200573
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1610868198
Short name T905
Test name
Test status
Simulation time 22207699207 ps
CPU time 153.89 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:59:02 PM PDT 24
Peak memory 252620 kb
Host smart-89d10405-ad27-4b30-8091-079056e62d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610868198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1610868198
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4044748357
Short name T461
Test name
Test status
Simulation time 84231262897 ps
CPU time 198.27 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:59:49 PM PDT 24
Peak memory 250116 kb
Host smart-3b2a275a-0a18-4aa7-b20d-02af016335b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044748357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4044748357
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2068898722
Short name T43
Test name
Test status
Simulation time 23540948014 ps
CPU time 148.71 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:58:56 PM PDT 24
Peak memory 258412 kb
Host smart-15bf54a2-3793-4cdc-86ce-e7ec5d3618e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068898722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2068898722
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1084470892
Short name T996
Test name
Test status
Simulation time 3056267516 ps
CPU time 15.54 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:44 PM PDT 24
Peak memory 225404 kb
Host smart-f65fbeb8-83c1-4ee5-a2e4-ff4392849bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084470892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1084470892
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.747040833
Short name T409
Test name
Test status
Simulation time 10374557262 ps
CPU time 57.87 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 252264 kb
Host smart-b1212646-3693-40ca-ad06-9c2583862246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747040833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.747040833
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2700422625
Short name T933
Test name
Test status
Simulation time 515082111 ps
CPU time 2.32 seconds
Started Aug 18 04:56:26 PM PDT 24
Finished Aug 18 04:56:29 PM PDT 24
Peak memory 225224 kb
Host smart-47379b8b-ea84-4524-afa0-973a7f523b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700422625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2700422625
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1334211697
Short name T555
Test name
Test status
Simulation time 534491344 ps
CPU time 7.5 seconds
Started Aug 18 04:56:26 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 233520 kb
Host smart-d086f1f5-b0f0-4052-a109-3ebf0f0612a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334211697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1334211697
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1591350489
Short name T264
Test name
Test status
Simulation time 104550638927 ps
CPU time 28.96 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:56 PM PDT 24
Peak memory 249708 kb
Host smart-65f4f822-caae-4aa0-aa0c-6d39113032e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591350489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1591350489
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3916818075
Short name T72
Test name
Test status
Simulation time 7533395012 ps
CPU time 7.94 seconds
Started Aug 18 04:56:14 PM PDT 24
Finished Aug 18 04:56:22 PM PDT 24
Peak memory 233636 kb
Host smart-3a52b38b-ba39-4c57-a22b-e6b633aa7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916818075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3916818075
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2536754525
Short name T74
Test name
Test status
Simulation time 178503291 ps
CPU time 3.77 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:31 PM PDT 24
Peak memory 220644 kb
Host smart-fc3f78cf-f2ca-44b9-8b5c-39e027ee4f82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2536754525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2536754525
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1495981617
Short name T217
Test name
Test status
Simulation time 70852666627 ps
CPU time 401.35 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 05:03:09 PM PDT 24
Peak memory 273364 kb
Host smart-57d4635c-04f1-420f-9e30-1afeebe5b021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495981617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1495981617
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.304245227
Short name T453
Test name
Test status
Simulation time 1992888666 ps
CPU time 26.13 seconds
Started Aug 18 04:56:14 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 217360 kb
Host smart-0c5e5528-cb4d-43d9-b49a-668af844b97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304245227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.304245227
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1330428445
Short name T634
Test name
Test status
Simulation time 784516851 ps
CPU time 3.61 seconds
Started Aug 18 04:56:11 PM PDT 24
Finished Aug 18 04:56:15 PM PDT 24
Peak memory 216988 kb
Host smart-fd0b0607-2754-4d37-923f-1c3320d51930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330428445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1330428445
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1784803560
Short name T445
Test name
Test status
Simulation time 24400522 ps
CPU time 1.15 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:13 PM PDT 24
Peak memory 217024 kb
Host smart-22101481-3c1b-413f-b2d8-14eae325753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784803560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1784803560
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3291187999
Short name T532
Test name
Test status
Simulation time 65850704 ps
CPU time 0.94 seconds
Started Aug 18 04:56:12 PM PDT 24
Finished Aug 18 04:56:13 PM PDT 24
Peak memory 206716 kb
Host smart-bc64ebe5-b05a-4190-9c6d-edf6069ce3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291187999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3291187999
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.349664141
Short name T121
Test name
Test status
Simulation time 969450232 ps
CPU time 6.02 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 240612 kb
Host smart-41876a95-afef-4381-9c8d-b919011e2bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349664141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.349664141
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3105116306
Short name T392
Test name
Test status
Simulation time 16390082 ps
CPU time 0.71 seconds
Started Aug 18 04:56:26 PM PDT 24
Finished Aug 18 04:56:27 PM PDT 24
Peak memory 206200 kb
Host smart-3e6f95f7-6a4e-44f9-9409-a43492459ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105116306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3105116306
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1182457139
Short name T606
Test name
Test status
Simulation time 654798509 ps
CPU time 6.46 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 225316 kb
Host smart-19974430-0f5b-4d0c-8e2a-b7de583cb58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182457139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1182457139
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2763026373
Short name T347
Test name
Test status
Simulation time 120036704 ps
CPU time 0.76 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:28 PM PDT 24
Peak memory 206324 kb
Host smart-40e5739b-6a0c-4b44-8b76-099bf4436b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763026373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2763026373
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.980393697
Short name T946
Test name
Test status
Simulation time 73817761837 ps
CPU time 188.97 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:59:38 PM PDT 24
Peak memory 258256 kb
Host smart-aad691c5-301e-42e7-9a98-db251b2b3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980393697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.980393697
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3542361216
Short name T287
Test name
Test status
Simulation time 66760524001 ps
CPU time 659.27 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 05:07:28 PM PDT 24
Peak memory 266392 kb
Host smart-0888e1cc-d216-4887-b2e4-a0baaa06b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542361216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3542361216
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2447121198
Short name T411
Test name
Test status
Simulation time 274818043 ps
CPU time 4.37 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:32 PM PDT 24
Peak memory 233476 kb
Host smart-08d9f335-cf18-4c7a-932c-e4acb136cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447121198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2447121198
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.211814500
Short name T192
Test name
Test status
Simulation time 4398620620 ps
CPU time 31.1 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:57:01 PM PDT 24
Peak memory 252432 kb
Host smart-f277dc2b-5147-4f4f-8352-7db7179083e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211814500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.211814500
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2051860180
Short name T517
Test name
Test status
Simulation time 113131604 ps
CPU time 2.68 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:56:33 PM PDT 24
Peak memory 225240 kb
Host smart-36195ec9-ac8c-43e0-a9ee-07848bb43444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051860180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2051860180
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2946596956
Short name T451
Test name
Test status
Simulation time 21957036810 ps
CPU time 30.99 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:58 PM PDT 24
Peak memory 225536 kb
Host smart-6345ff1a-b20e-471f-b707-351068f158cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946596956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2946596956
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1660774233
Short name T794
Test name
Test status
Simulation time 401305535 ps
CPU time 7.21 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 234420 kb
Host smart-e3b37c86-71f6-43f6-a93c-e9e26e5d1ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660774233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1660774233
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2552354445
Short name T852
Test name
Test status
Simulation time 18677037931 ps
CPU time 28.79 seconds
Started Aug 18 04:56:31 PM PDT 24
Finished Aug 18 04:57:00 PM PDT 24
Peak memory 241728 kb
Host smart-46c37007-0c69-4f76-bfc6-cdf61715c12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552354445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2552354445
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1613397530
Short name T380
Test name
Test status
Simulation time 939748030 ps
CPU time 12.04 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:40 PM PDT 24
Peak memory 221264 kb
Host smart-154291d7-e600-4403-8fb6-d0fc82013d95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613397530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1613397530
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1415050545
Short name T16
Test name
Test status
Simulation time 4340437841 ps
CPU time 44.9 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:57:13 PM PDT 24
Peak memory 251132 kb
Host smart-615c9fcf-acc6-41ac-959c-7f47bb11493b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415050545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1415050545
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2469311557
Short name T729
Test name
Test status
Simulation time 7064395723 ps
CPU time 30.72 seconds
Started Aug 18 04:56:26 PM PDT 24
Finished Aug 18 04:56:57 PM PDT 24
Peak memory 217584 kb
Host smart-2525b8e6-bd99-46d3-a382-9b97bf9a6bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469311557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2469311557
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3044836732
Short name T886
Test name
Test status
Simulation time 986665908 ps
CPU time 6.65 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 217212 kb
Host smart-9bd3d161-f4b1-4f2a-b946-9b88bcfe41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044836732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3044836732
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1620641125
Short name T22
Test name
Test status
Simulation time 363498019 ps
CPU time 3.65 seconds
Started Aug 18 04:56:31 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 217068 kb
Host smart-8d75aa8e-25e4-473c-af4d-75a97a8db2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620641125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1620641125
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.226471848
Short name T394
Test name
Test status
Simulation time 38774950 ps
CPU time 0.88 seconds
Started Aug 18 04:56:26 PM PDT 24
Finished Aug 18 04:56:27 PM PDT 24
Peak memory 206688 kb
Host smart-5ba39806-a5e6-47d5-ab8b-d2cf34f6e7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226471848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.226471848
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1950952784
Short name T276
Test name
Test status
Simulation time 313228276 ps
CPU time 6.52 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 225264 kb
Host smart-816f2caf-2ae9-4809-a895-15044c0948c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950952784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1950952784
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.644667679
Short name T503
Test name
Test status
Simulation time 132340587 ps
CPU time 0.71 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:39 PM PDT 24
Peak memory 206244 kb
Host smart-2f111ffc-acb5-42e3-9608-5ef17bfeea32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644667679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.644667679
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4168570114
Short name T672
Test name
Test status
Simulation time 1590336567 ps
CPU time 6.05 seconds
Started Aug 18 04:56:31 PM PDT 24
Finished Aug 18 04:56:37 PM PDT 24
Peak memory 233376 kb
Host smart-4308c40e-b927-4c65-9dbb-6083782924af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168570114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4168570114
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1275733407
Short name T1006
Test name
Test status
Simulation time 23392625 ps
CPU time 0.81 seconds
Started Aug 18 04:56:28 PM PDT 24
Finished Aug 18 04:56:29 PM PDT 24
Peak memory 207340 kb
Host smart-d3776a69-1c15-4f76-aeb5-774d4571f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275733407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1275733407
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.260638695
Short name T985
Test name
Test status
Simulation time 35473404356 ps
CPU time 124.28 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:58:43 PM PDT 24
Peak memory 253972 kb
Host smart-b9174ebd-64d2-41f4-81ae-d097633c0a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260638695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.260638695
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3637256568
Short name T710
Test name
Test status
Simulation time 25451079499 ps
CPU time 123.07 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:58:41 PM PDT 24
Peak memory 255080 kb
Host smart-8e00d002-c62a-430c-8181-872137b30191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637256568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3637256568
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.344295867
Short name T280
Test name
Test status
Simulation time 65192002837 ps
CPU time 160.98 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:59:26 PM PDT 24
Peak memory 249968 kb
Host smart-2bae3515-f1be-4b4c-a562-668e544aaf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344295867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.344295867
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3984134088
Short name T452
Test name
Test status
Simulation time 35471766 ps
CPU time 2.62 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 233496 kb
Host smart-72951757-f22b-4c66-b5f0-3e7f25bd46b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984134088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3984134088
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.990862020
Short name T625
Test name
Test status
Simulation time 136218102 ps
CPU time 2.04 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:29 PM PDT 24
Peak memory 224772 kb
Host smart-c683be9c-8e93-46b2-83da-3682398965c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990862020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.990862020
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2170034605
Short name T455
Test name
Test status
Simulation time 824707837 ps
CPU time 11.57 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 237340 kb
Host smart-17a69907-69c2-484d-a2f7-59bac54430ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170034605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2170034605
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2731384830
Short name T493
Test name
Test status
Simulation time 7034450228 ps
CPU time 20.44 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 241644 kb
Host smart-b9ba270e-8eaf-4cd8-8a6b-00ecf011a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731384830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2731384830
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2241079167
Short name T827
Test name
Test status
Simulation time 3615702991 ps
CPU time 14.08 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:56:44 PM PDT 24
Peak memory 233656 kb
Host smart-59e4a93d-fde0-4c1d-a71c-5fab34c6d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241079167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2241079167
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3147422774
Short name T497
Test name
Test status
Simulation time 881618934 ps
CPU time 7.22 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 223872 kb
Host smart-b444e572-63ab-462e-a2ad-b672667a2372
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3147422774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3147422774
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3658572921
Short name T743
Test name
Test status
Simulation time 26857827344 ps
CPU time 38.43 seconds
Started Aug 18 04:56:33 PM PDT 24
Finished Aug 18 04:57:12 PM PDT 24
Peak memory 217368 kb
Host smart-a543ff67-baed-4018-9898-b33103502b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658572921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3658572921
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2598731483
Short name T399
Test name
Test status
Simulation time 44263553312 ps
CPU time 10.55 seconds
Started Aug 18 04:56:29 PM PDT 24
Finished Aug 18 04:56:39 PM PDT 24
Peak memory 217456 kb
Host smart-9bd6fe46-e05d-4f00-a5ca-4543307aabfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598731483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2598731483
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2658716236
Short name T628
Test name
Test status
Simulation time 200305066 ps
CPU time 5.3 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:56:35 PM PDT 24
Peak memory 217140 kb
Host smart-2069ffb2-fd8f-48cc-8c18-cb2856cb0326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658716236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2658716236
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.777129546
Short name T821
Test name
Test status
Simulation time 38652260 ps
CPU time 0.86 seconds
Started Aug 18 04:56:27 PM PDT 24
Finished Aug 18 04:56:28 PM PDT 24
Peak memory 207296 kb
Host smart-5c40e7e4-867c-4275-9dcd-cce7176a35ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777129546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.777129546
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.642646923
Short name T868
Test name
Test status
Simulation time 247421075 ps
CPU time 3.08 seconds
Started Aug 18 04:56:30 PM PDT 24
Finished Aug 18 04:56:34 PM PDT 24
Peak memory 233544 kb
Host smart-81427605-c6b9-4aea-b0bb-3b1d3cea28f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642646923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.642646923
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1832805727
Short name T345
Test name
Test status
Simulation time 47571141 ps
CPU time 0.7 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 206156 kb
Host smart-812866c7-b7bd-499d-aa4b-e7134bce55ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832805727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1832805727
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1526218992
Short name T86
Test name
Test status
Simulation time 86709084 ps
CPU time 2.88 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:56:42 PM PDT 24
Peak memory 233508 kb
Host smart-23561777-6f46-4e96-9612-89acd0d27889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526218992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1526218992
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.692614130
Short name T673
Test name
Test status
Simulation time 19724008 ps
CPU time 0.92 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:56:46 PM PDT 24
Peak memory 207916 kb
Host smart-512833dc-3ecd-4267-a8eb-087f60ea694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692614130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.692614130
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1375218033
Short name T761
Test name
Test status
Simulation time 7251320625 ps
CPU time 21.15 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:57:00 PM PDT 24
Peak memory 255188 kb
Host smart-eee4e417-2711-4091-af68-0e3ef6536684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375218033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1375218033
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.175448847
Short name T301
Test name
Test status
Simulation time 38001833971 ps
CPU time 245.72 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 05:00:46 PM PDT 24
Peak memory 253792 kb
Host smart-e4820701-8c4e-4030-a315-412025ded675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175448847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.175448847
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1262584170
Short name T316
Test name
Test status
Simulation time 3719394450 ps
CPU time 47.59 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:57:30 PM PDT 24
Peak memory 250132 kb
Host smart-e60a8127-2590-4824-a6fc-e629b4aa9bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262584170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1262584170
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.723625030
Short name T366
Test name
Test status
Simulation time 149908048 ps
CPU time 3.92 seconds
Started Aug 18 04:56:43 PM PDT 24
Finished Aug 18 04:56:47 PM PDT 24
Peak memory 234124 kb
Host smart-6774e74f-c525-437e-9bd2-5e84e373b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723625030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.723625030
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.4202111147
Short name T567
Test name
Test status
Simulation time 8085059700 ps
CPU time 46.58 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 252016 kb
Host smart-10ba3ba9-aeae-4b4b-b8f5-d16a3b775145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202111147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.4202111147
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2863060817
Short name T677
Test name
Test status
Simulation time 9278075539 ps
CPU time 24.85 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:57:05 PM PDT 24
Peak memory 233608 kb
Host smart-156d7422-516b-47e3-9cb1-15b6fd0f1065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863060817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2863060817
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1675638610
Short name T982
Test name
Test status
Simulation time 30500598103 ps
CPU time 56.5 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:57:36 PM PDT 24
Peak memory 241256 kb
Host smart-f8bec02d-7d15-4c6d-9dde-a0c6cbb67784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675638610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1675638610
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1395360976
Short name T633
Test name
Test status
Simulation time 1709760400 ps
CPU time 2.66 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 225260 kb
Host smart-6046ffbc-4039-4e3f-9802-4cd18fd54500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395360976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1395360976
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2329598699
Short name T531
Test name
Test status
Simulation time 3352535426 ps
CPU time 5.32 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 233660 kb
Host smart-148a139d-75c5-4ab0-8775-5abfa093998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329598699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2329598699
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1709333969
Short name T725
Test name
Test status
Simulation time 269899171 ps
CPU time 5.34 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:56:44 PM PDT 24
Peak memory 220956 kb
Host smart-c82f2422-801c-4a08-a277-0e65dc2b615a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709333969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1709333969
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.74521508
Short name T547
Test name
Test status
Simulation time 9335683353 ps
CPU time 27.12 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:57:12 PM PDT 24
Peak memory 217516 kb
Host smart-6b1f12d5-569c-40ae-9c54-92e045d907e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74521508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.74521508
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1435614110
Short name T765
Test name
Test status
Simulation time 584852513 ps
CPU time 4.35 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 217156 kb
Host smart-1e87c809-7308-4bde-80d4-7c893ca7fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435614110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1435614110
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.981245118
Short name T702
Test name
Test status
Simulation time 356988350 ps
CPU time 10.94 seconds
Started Aug 18 04:56:39 PM PDT 24
Finished Aug 18 04:56:50 PM PDT 24
Peak memory 217072 kb
Host smart-b4ba9fec-e6f7-4ead-918d-bb6c7092885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981245118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.981245118
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2739316272
Short name T556
Test name
Test status
Simulation time 610617461 ps
CPU time 0.98 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:56:43 PM PDT 24
Peak memory 207748 kb
Host smart-c42b9553-c20a-419a-91a5-d7fd2cdef34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739316272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2739316272
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1815233172
Short name T712
Test name
Test status
Simulation time 5867913329 ps
CPU time 24.44 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:57:04 PM PDT 24
Peak memory 233536 kb
Host smart-fc750184-b5b0-432f-824d-8e2a1da7ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815233172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1815233172
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.321152689
Short name T659
Test name
Test status
Simulation time 20714086 ps
CPU time 0.73 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 206204 kb
Host smart-dc9bceea-eec0-44b1-9a12-7abcc7412601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321152689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.321152689
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4187437097
Short name T419
Test name
Test status
Simulation time 1462332064 ps
CPU time 14.84 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:53 PM PDT 24
Peak memory 233480 kb
Host smart-d0ffa295-b72c-4207-add2-936b74c072ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187437097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4187437097
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2021177005
Short name T590
Test name
Test status
Simulation time 67845977 ps
CPU time 0.81 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 207644 kb
Host smart-e412819e-bee0-4a25-8c26-78fd7ecf2140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021177005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2021177005
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4122679130
Short name T188
Test name
Test status
Simulation time 115719724763 ps
CPU time 401.38 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 05:03:21 PM PDT 24
Peak memory 250072 kb
Host smart-1ba5a17f-c3ac-4b19-ae8a-bb91ae187346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122679130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4122679130
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.418397189
Short name T140
Test name
Test status
Simulation time 14405293949 ps
CPU time 108.92 seconds
Started Aug 18 04:56:46 PM PDT 24
Finished Aug 18 04:58:35 PM PDT 24
Peak memory 266328 kb
Host smart-416adc24-9d6e-44b0-b53f-a110e55c6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418397189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.418397189
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2668407955
Short name T863
Test name
Test status
Simulation time 1566915339 ps
CPU time 22.19 seconds
Started Aug 18 04:56:42 PM PDT 24
Finished Aug 18 04:57:04 PM PDT 24
Peak memory 225308 kb
Host smart-da9d921a-fc0c-48dd-8d77-6b29d8d3ac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668407955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2668407955
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4225950320
Short name T674
Test name
Test status
Simulation time 16437610676 ps
CPU time 30.78 seconds
Started Aug 18 04:56:41 PM PDT 24
Finished Aug 18 04:57:12 PM PDT 24
Peak memory 256868 kb
Host smart-e93865a5-d5e7-4c17-a593-7d78cf0ed7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225950320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4225950320
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.604208154
Short name T739
Test name
Test status
Simulation time 530169081 ps
CPU time 5.96 seconds
Started Aug 18 04:56:41 PM PDT 24
Finished Aug 18 04:56:47 PM PDT 24
Peak memory 233508 kb
Host smart-f8a151d7-0ee8-4f97-9219-191379ca7662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604208154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.604208154
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2575027116
Short name T442
Test name
Test status
Simulation time 13847362951 ps
CPU time 47.97 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:57:28 PM PDT 24
Peak memory 233516 kb
Host smart-909b28a5-cd01-4cd9-a864-cc2e353dc6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575027116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2575027116
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.265211988
Short name T270
Test name
Test status
Simulation time 4981841987 ps
CPU time 12.12 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:56:53 PM PDT 24
Peak memory 233088 kb
Host smart-a915fb72-9fb3-40bf-ab14-595a359ff589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265211988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.265211988
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.547139705
Short name T258
Test name
Test status
Simulation time 7196175375 ps
CPU time 7 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:56:47 PM PDT 24
Peak memory 225444 kb
Host smart-c91bfbf8-70d2-486a-83ff-e9e1ab51ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547139705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.547139705
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2241858887
Short name T875
Test name
Test status
Simulation time 496704195 ps
CPU time 5.02 seconds
Started Aug 18 04:56:44 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 224284 kb
Host smart-364a1e1b-d01b-4062-8b43-c6119e2097ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2241858887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2241858887
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3296798027
Short name T293
Test name
Test status
Simulation time 413844556791 ps
CPU time 1088.53 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 05:14:46 PM PDT 24
Peak memory 289764 kb
Host smart-e3b95215-705d-4d69-9a7b-ce5987e01e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296798027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3296798027
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.132683277
Short name T318
Test name
Test status
Simulation time 5441098955 ps
CPU time 14.58 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 217280 kb
Host smart-2f070139-1238-45a8-af1e-8909b38e1529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132683277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.132683277
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3795026615
Short name T488
Test name
Test status
Simulation time 5472898033 ps
CPU time 4.99 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:56:45 PM PDT 24
Peak memory 217164 kb
Host smart-74813dd5-a7eb-46ed-bd89-89f7d2a8da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795026615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3795026615
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.942798889
Short name T60
Test name
Test status
Simulation time 3357756621 ps
CPU time 2.68 seconds
Started Aug 18 04:56:40 PM PDT 24
Finished Aug 18 04:56:42 PM PDT 24
Peak memory 217152 kb
Host smart-b39342c3-2098-4562-8e8c-636bdb8ee862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942798889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.942798889
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1732666158
Short name T372
Test name
Test status
Simulation time 570234001 ps
CPU time 0.8 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:38 PM PDT 24
Peak memory 206848 kb
Host smart-b4be882c-387e-4922-a118-7eae1c431917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732666158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1732666158
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3132999365
Short name T902
Test name
Test status
Simulation time 2188115357 ps
CPU time 7.14 seconds
Started Aug 18 04:56:41 PM PDT 24
Finished Aug 18 04:56:48 PM PDT 24
Peak memory 249100 kb
Host smart-294b9c07-6b74-415e-bfb0-07821a9791b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132999365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3132999365
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2227204748
Short name T967
Test name
Test status
Simulation time 63217779 ps
CPU time 0.73 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:48 PM PDT 24
Peak memory 205512 kb
Host smart-b7127194-f7aa-48d4-917d-f844995c4383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227204748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2227204748
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2142184995
Short name T573
Test name
Test status
Simulation time 169970159 ps
CPU time 2.28 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 225436 kb
Host smart-2d6e950f-9500-4f9f-a037-9a63036e8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142184995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2142184995
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1479821394
Short name T615
Test name
Test status
Simulation time 23442413 ps
CPU time 0.76 seconds
Started Aug 18 04:56:41 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 207432 kb
Host smart-b7074f0e-fdc9-43a6-95a7-26e93ecb24b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479821394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1479821394
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.406518194
Short name T787
Test name
Test status
Simulation time 8255583158 ps
CPU time 29.3 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:57:19 PM PDT 24
Peak memory 254924 kb
Host smart-e183003c-16e8-44b5-a5cd-b2d498354422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406518194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.406518194
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1841412612
Short name T64
Test name
Test status
Simulation time 2534655294 ps
CPU time 69.87 seconds
Started Aug 18 04:56:50 PM PDT 24
Finished Aug 18 04:58:00 PM PDT 24
Peak memory 255868 kb
Host smart-4dda62ce-9adc-408e-a738-33d32dedfb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841412612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1841412612
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3347640264
Short name T714
Test name
Test status
Simulation time 124143155140 ps
CPU time 261.01 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 05:01:10 PM PDT 24
Peak memory 256476 kb
Host smart-4982e078-ba6d-460e-9161-37a0bd2f2d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347640264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3347640264
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3021976760
Short name T304
Test name
Test status
Simulation time 372654304 ps
CPU time 7.48 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:56 PM PDT 24
Peak memory 233544 kb
Host smart-04c9de40-18d6-49d8-bb46-3168bc936b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021976760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3021976760
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1437214152
Short name T288
Test name
Test status
Simulation time 85273509361 ps
CPU time 135.15 seconds
Started Aug 18 04:56:51 PM PDT 24
Finished Aug 18 04:59:06 PM PDT 24
Peak memory 255804 kb
Host smart-91bee9fd-4035-4636-a71a-10f97b0c32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437214152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1437214152
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3119942411
Short name T609
Test name
Test status
Simulation time 29464176 ps
CPU time 1.98 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:56:48 PM PDT 24
Peak memory 224948 kb
Host smart-35885385-d387-4a11-acd0-26b5475bd8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119942411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3119942411
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1439705243
Short name T585
Test name
Test status
Simulation time 19328148419 ps
CPU time 30.02 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:57:18 PM PDT 24
Peak memory 233732 kb
Host smart-18d99425-7928-451c-881b-6364b073f8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439705243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1439705243
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3911595844
Short name T260
Test name
Test status
Simulation time 16366032749 ps
CPU time 18.05 seconds
Started Aug 18 04:56:50 PM PDT 24
Finished Aug 18 04:57:08 PM PDT 24
Peak memory 241800 kb
Host smart-8b85d6ee-e408-497e-b827-88171012ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911595844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3911595844
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3810019558
Short name T788
Test name
Test status
Simulation time 800195937 ps
CPU time 3.1 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 225224 kb
Host smart-3307a58a-c9f2-4016-a20b-2c3c7b3fdc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810019558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3810019558
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.727194755
Short name T499
Test name
Test status
Simulation time 4298064232 ps
CPU time 9.84 seconds
Started Aug 18 04:56:51 PM PDT 24
Finished Aug 18 04:57:01 PM PDT 24
Peak memory 219812 kb
Host smart-351f7d2c-45bf-4a5e-b551-353f5e875ce0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=727194755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.727194755
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3596551556
Short name T775
Test name
Test status
Simulation time 4613582674 ps
CPU time 46.4 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:57:35 PM PDT 24
Peak memory 258148 kb
Host smart-d8f84b8a-fc4a-4d01-a6a1-4c7e05af48d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596551556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3596551556
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2251498448
Short name T543
Test name
Test status
Simulation time 559864922 ps
CPU time 3.68 seconds
Started Aug 18 04:56:37 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 217092 kb
Host smart-4275edfa-2a47-4360-8484-49f592f033fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251498448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2251498448
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1952660730
Short name T8
Test name
Test status
Simulation time 828794776 ps
CPU time 2.69 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:41 PM PDT 24
Peak memory 217200 kb
Host smart-e245e152-4ebd-424f-9965-a88f8dd59970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952660730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1952660730
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1363578914
Short name T995
Test name
Test status
Simulation time 332075386 ps
CPU time 2.28 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 217088 kb
Host smart-51c896f9-0198-4121-a4ff-cbcce92b8539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363578914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1363578914
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2251148966
Short name T454
Test name
Test status
Simulation time 111269064 ps
CPU time 0.82 seconds
Started Aug 18 04:56:38 PM PDT 24
Finished Aug 18 04:56:39 PM PDT 24
Peak memory 207908 kb
Host smart-bdcf651c-18fa-4db3-a56c-c6bc7e1b32ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251148966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2251148966
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4068103923
Short name T69
Test name
Test status
Simulation time 21319792555 ps
CPU time 18.04 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:57:07 PM PDT 24
Peak memory 233684 kb
Host smart-804400f2-790a-48f6-b2be-6a66dd7b5d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068103923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4068103923
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.98196913
Short name T354
Test name
Test status
Simulation time 32940875 ps
CPU time 0.75 seconds
Started Aug 18 04:56:51 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 206612 kb
Host smart-066037a0-5ba5-4473-8bf7-f5eaa3cc76da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98196913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.98196913
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2154877391
Short name T930
Test name
Test status
Simulation time 479560690 ps
CPU time 6.06 seconds
Started Aug 18 04:56:50 PM PDT 24
Finished Aug 18 04:56:56 PM PDT 24
Peak memory 225360 kb
Host smart-2aa0eeba-c52a-48b4-ab90-4bf4588edd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154877391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2154877391
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.855838091
Short name T805
Test name
Test status
Simulation time 21142636 ps
CPU time 0.78 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:48 PM PDT 24
Peak memory 207608 kb
Host smart-8567522b-48ea-4ccb-8738-0f492a093923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855838091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.855838091
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1224394352
Short name T300
Test name
Test status
Simulation time 4305976313 ps
CPU time 88.81 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:58:18 PM PDT 24
Peak memory 255716 kb
Host smart-1b8b43e7-baf7-4713-9fd5-ecc316fb45a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224394352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1224394352
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2336248927
Short name T507
Test name
Test status
Simulation time 2829189355 ps
CPU time 33.01 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:57:22 PM PDT 24
Peak memory 239228 kb
Host smart-1da56d80-27c4-4c06-a323-ae7a3dfa2582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336248927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2336248927
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4048407662
Short name T802
Test name
Test status
Simulation time 2156477572 ps
CPU time 36.29 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 241904 kb
Host smart-e5a49a25-b51b-40d7-b12a-05bd5ddba61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048407662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4048407662
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.101894389
Short name T303
Test name
Test status
Simulation time 758854959 ps
CPU time 8.28 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:56:56 PM PDT 24
Peak memory 225316 kb
Host smart-cb8164db-c5ca-4182-81bc-cd08d76ceda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101894389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.101894389
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1992139660
Short name T1002
Test name
Test status
Simulation time 18108283029 ps
CPU time 57.61 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:57:46 PM PDT 24
Peak memory 258268 kb
Host smart-bac2d04e-295f-4652-960a-370f7025b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992139660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1992139660
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2346672149
Short name T9
Test name
Test status
Simulation time 73526351 ps
CPU time 3.07 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:52 PM PDT 24
Peak memory 233508 kb
Host smart-c7030076-6ae3-4364-9b87-fa56f691518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346672149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2346672149
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3844694302
Short name T807
Test name
Test status
Simulation time 99072821802 ps
CPU time 117.7 seconds
Started Aug 18 04:56:46 PM PDT 24
Finished Aug 18 04:58:44 PM PDT 24
Peak memory 237420 kb
Host smart-c0c83e37-4084-4eee-b995-d8ec8183f871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844694302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3844694302
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3532702892
Short name T269
Test name
Test status
Simulation time 1196373116 ps
CPU time 5.77 seconds
Started Aug 18 04:56:50 PM PDT 24
Finished Aug 18 04:56:56 PM PDT 24
Peak memory 233612 kb
Host smart-87543960-2e65-499a-88df-57044fb30e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532702892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3532702892
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2129045615
Short name T962
Test name
Test status
Simulation time 21938002663 ps
CPU time 20.23 seconds
Started Aug 18 04:56:50 PM PDT 24
Finished Aug 18 04:57:11 PM PDT 24
Peak memory 241504 kb
Host smart-4c0029e7-a481-451e-9c57-afa68cdbbafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129045615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2129045615
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2206160305
Short name T49
Test name
Test status
Simulation time 365359244 ps
CPU time 3.93 seconds
Started Aug 18 04:56:51 PM PDT 24
Finished Aug 18 04:56:56 PM PDT 24
Peak memory 223836 kb
Host smart-ab94882e-0b24-4196-bac9-9480f5272c98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206160305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2206160305
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1310797061
Short name T855
Test name
Test status
Simulation time 96415822 ps
CPU time 0.73 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:47 PM PDT 24
Peak memory 206536 kb
Host smart-591bf6d7-d399-4645-977c-9cc9a6dbdcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310797061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1310797061
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.42255658
Short name T662
Test name
Test status
Simulation time 150514863 ps
CPU time 1.88 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 208700 kb
Host smart-9f9b9ce8-de5d-4baa-a8ab-bfafb639c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42255658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.42255658
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4277573338
Short name T24
Test name
Test status
Simulation time 118403724 ps
CPU time 0.72 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:50 PM PDT 24
Peak memory 206456 kb
Host smart-7ab98686-2599-4185-80ef-a576bb94fcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277573338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4277573338
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2673402463
Short name T806
Test name
Test status
Simulation time 112224578 ps
CPU time 0.83 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 206868 kb
Host smart-b7372fc8-939f-4347-8031-81be943f01b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673402463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2673402463
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.93566918
Short name T240
Test name
Test status
Simulation time 272189611 ps
CPU time 4.86 seconds
Started Aug 18 04:56:48 PM PDT 24
Finished Aug 18 04:56:53 PM PDT 24
Peak memory 241604 kb
Host smart-489fe3e5-bd0a-4ad5-b85d-0179a53ccd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93566918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.93566918
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.764810685
Short name T797
Test name
Test status
Simulation time 26952793 ps
CPU time 0.74 seconds
Started Aug 18 04:56:57 PM PDT 24
Finished Aug 18 04:56:58 PM PDT 24
Peak memory 205552 kb
Host smart-b88d3ae1-4d9e-4af4-8354-112a123f8415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764810685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.764810685
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3969755736
Short name T948
Test name
Test status
Simulation time 861274677 ps
CPU time 7.91 seconds
Started Aug 18 04:56:55 PM PDT 24
Finished Aug 18 04:57:03 PM PDT 24
Peak memory 225388 kb
Host smart-8b66a2e6-a61c-4368-bfea-5198e57146f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969755736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3969755736
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1793173534
Short name T449
Test name
Test status
Simulation time 328389466 ps
CPU time 0.79 seconds
Started Aug 18 04:56:46 PM PDT 24
Finished Aug 18 04:56:47 PM PDT 24
Peak memory 207264 kb
Host smart-60d01ff3-3f27-41f8-b92f-d9277966e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793173534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1793173534
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4094338923
Short name T823
Test name
Test status
Simulation time 18676023524 ps
CPU time 80.71 seconds
Started Aug 18 04:56:57 PM PDT 24
Finished Aug 18 04:58:18 PM PDT 24
Peak memory 249984 kb
Host smart-c05fb528-86ff-4af0-8ba4-39eb1ebe6c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094338923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4094338923
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.50968478
Short name T728
Test name
Test status
Simulation time 11931080803 ps
CPU time 36.29 seconds
Started Aug 18 04:56:57 PM PDT 24
Finished Aug 18 04:57:33 PM PDT 24
Peak memory 233704 kb
Host smart-2f411dbe-7b6f-4f62-b7b9-20732257f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50968478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.50968478
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3928855257
Short name T298
Test name
Test status
Simulation time 38063733295 ps
CPU time 135.77 seconds
Started Aug 18 04:56:55 PM PDT 24
Finished Aug 18 04:59:11 PM PDT 24
Peak memory 269572 kb
Host smart-afaea20a-0b8e-422b-9378-83a090406911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928855257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3928855257
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3601360834
Short name T918
Test name
Test status
Simulation time 3030097741 ps
CPU time 50.27 seconds
Started Aug 18 04:56:57 PM PDT 24
Finished Aug 18 04:57:47 PM PDT 24
Peak memory 241692 kb
Host smart-ff02028f-d416-4859-86c8-0fdca4cd55c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601360834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3601360834
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4096624376
Short name T91
Test name
Test status
Simulation time 17555803 ps
CPU time 0.77 seconds
Started Aug 18 04:56:58 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 216648 kb
Host smart-e8740b1f-decd-4b33-8486-f9cc3b932423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096624376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4096624376
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.386174301
Short name T396
Test name
Test status
Simulation time 1735806302 ps
CPU time 5.49 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:55 PM PDT 24
Peak memory 225388 kb
Host smart-908c7238-4092-403e-8f31-3d15949dd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386174301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.386174301
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3268221896
Short name T486
Test name
Test status
Simulation time 27127969375 ps
CPU time 45.02 seconds
Started Aug 18 04:56:59 PM PDT 24
Finished Aug 18 04:57:44 PM PDT 24
Peak memory 241804 kb
Host smart-c8093479-b121-4539-b908-353f4dd66449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268221896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3268221896
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1064318384
Short name T747
Test name
Test status
Simulation time 535585543 ps
CPU time 7.88 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:55 PM PDT 24
Peak memory 225340 kb
Host smart-f1204dc9-2c35-4705-8303-368f9001f01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064318384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1064318384
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3513605651
Short name T13
Test name
Test status
Simulation time 1861700600 ps
CPU time 4.53 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:56:50 PM PDT 24
Peak memory 233512 kb
Host smart-da97ccd5-6149-474c-b19d-2371199cc9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513605651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3513605651
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.297742811
Short name T697
Test name
Test status
Simulation time 6679381349 ps
CPU time 13.66 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:57:09 PM PDT 24
Peak memory 224224 kb
Host smart-ae5b324d-5e74-4bc9-9288-09bd9a211f45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=297742811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.297742811
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3551003693
Short name T157
Test name
Test status
Simulation time 225742400026 ps
CPU time 310.16 seconds
Started Aug 18 04:57:01 PM PDT 24
Finished Aug 18 05:02:11 PM PDT 24
Peak memory 250448 kb
Host smart-45920c26-503c-43cd-96f1-23f2f087a47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551003693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3551003693
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.841687541
Short name T314
Test name
Test status
Simulation time 1008050581 ps
CPU time 6 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:55 PM PDT 24
Peak memory 217136 kb
Host smart-e8f17a5e-8160-4556-bbfe-e1991c53d018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841687541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.841687541
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2408011959
Short name T581
Test name
Test status
Simulation time 1793376513 ps
CPU time 4.14 seconds
Started Aug 18 04:56:45 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 217116 kb
Host smart-91dc02d6-53cb-41fa-af06-79c152057424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408011959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2408011959
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2508607605
Short name T326
Test name
Test status
Simulation time 146456542 ps
CPU time 1.87 seconds
Started Aug 18 04:56:47 PM PDT 24
Finished Aug 18 04:56:49 PM PDT 24
Peak memory 217048 kb
Host smart-592323c6-163d-4d91-9e52-f2f6168e45cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508607605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2508607605
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2857590031
Short name T39
Test name
Test status
Simulation time 137012596 ps
CPU time 0.87 seconds
Started Aug 18 04:56:49 PM PDT 24
Finished Aug 18 04:56:50 PM PDT 24
Peak memory 207884 kb
Host smart-59ccce3e-fd19-4682-a389-9141da780d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857590031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2857590031
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.391052405
Short name T92
Test name
Test status
Simulation time 2816649834 ps
CPU time 14.73 seconds
Started Aug 18 04:56:55 PM PDT 24
Finished Aug 18 04:57:10 PM PDT 24
Peak memory 233668 kb
Host smart-34609e7e-96d7-40e9-a307-d75f5da698a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391052405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.391052405
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2271051554
Short name T638
Test name
Test status
Simulation time 12643915 ps
CPU time 0.73 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:09 PM PDT 24
Peak memory 206484 kb
Host smart-f83679f2-742c-41f5-b7f2-4a581fc73d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271051554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2271051554
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3610096350
Short name T772
Test name
Test status
Simulation time 91015445 ps
CPU time 2.23 seconds
Started Aug 18 04:56:57 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 224920 kb
Host smart-109114dc-d1a1-4b5a-9b9a-d315ceb49eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610096350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3610096350
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.760801174
Short name T593
Test name
Test status
Simulation time 22032360 ps
CPU time 0.82 seconds
Started Aug 18 04:56:59 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 207384 kb
Host smart-5e8bd248-839c-42fb-844e-d65776648d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760801174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.760801174
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1177807942
Short name T549
Test name
Test status
Simulation time 1031482563 ps
CPU time 12.41 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 239496 kb
Host smart-cfe70e34-4782-48d7-b20a-a6b5a0d3907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177807942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1177807942
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.848296812
Short name T221
Test name
Test status
Simulation time 193543904410 ps
CPU time 574.45 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 05:06:43 PM PDT 24
Peak memory 268316 kb
Host smart-9fcb4b11-4efd-4212-9c7b-f417bf66a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848296812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.848296812
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.630277073
Short name T476
Test name
Test status
Simulation time 28312850273 ps
CPU time 91.02 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 04:58:40 PM PDT 24
Peak memory 254972 kb
Host smart-594c5073-e8f9-417a-957c-b4caa380aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630277073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.630277073
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.904153321
Short name T799
Test name
Test status
Simulation time 392382777 ps
CPU time 7.86 seconds
Started Aug 18 04:57:06 PM PDT 24
Finished Aug 18 04:57:14 PM PDT 24
Peak memory 233536 kb
Host smart-2632608f-9ed0-4785-bad0-97018f03239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904153321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.904153321
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2842210916
Short name T100
Test name
Test status
Simulation time 13624051699 ps
CPU time 110.27 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:58:58 PM PDT 24
Peak memory 248384 kb
Host smart-4c0ae90f-cca2-47f3-b0fe-29e6f8f18f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842210916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2842210916
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3367010052
Short name T570
Test name
Test status
Simulation time 184882588 ps
CPU time 5.47 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:57:02 PM PDT 24
Peak memory 225392 kb
Host smart-b87ecf1d-8eb3-4350-a567-65b58b8e67f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367010052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3367010052
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.584465688
Short name T1001
Test name
Test status
Simulation time 29982501 ps
CPU time 2.35 seconds
Started Aug 18 04:56:55 PM PDT 24
Finished Aug 18 04:56:58 PM PDT 24
Peak memory 224608 kb
Host smart-9a78cb97-2b1c-4e8e-98de-04d00507f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584465688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.584465688
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3859495920
Short name T969
Test name
Test status
Simulation time 4971972684 ps
CPU time 4.83 seconds
Started Aug 18 04:57:00 PM PDT 24
Finished Aug 18 04:57:05 PM PDT 24
Peak memory 233696 kb
Host smart-02f91813-ae31-44c0-b224-7f71a256f7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859495920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3859495920
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4191197552
Short name T431
Test name
Test status
Simulation time 151273877 ps
CPU time 2.25 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 233508 kb
Host smart-503bb481-c331-4bc9-acba-548a6e835113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191197552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4191197552
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3880246871
Short name T480
Test name
Test status
Simulation time 908011141 ps
CPU time 12.35 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 222936 kb
Host smart-078254d3-df1d-4aac-98a9-f2d943700658
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3880246871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3880246871
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.674449234
Short name T206
Test name
Test status
Simulation time 21059081722 ps
CPU time 69.5 seconds
Started Aug 18 04:57:10 PM PDT 24
Finished Aug 18 04:58:20 PM PDT 24
Peak memory 254104 kb
Host smart-c8ef1f00-2381-4d35-87a0-45ae86a130af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674449234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.674449234
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1356390630
Short name T998
Test name
Test status
Simulation time 15896464672 ps
CPU time 23.33 seconds
Started Aug 18 04:56:58 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 217364 kb
Host smart-6ab8bcad-ebde-47ed-b257-f312460acabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356390630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1356390630
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3475376211
Short name T637
Test name
Test status
Simulation time 751872508 ps
CPU time 1.29 seconds
Started Aug 18 04:56:57 PM PDT 24
Finished Aug 18 04:56:58 PM PDT 24
Peak memory 208752 kb
Host smart-20c47219-2415-4071-9bc8-e3717631af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475376211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3475376211
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1325114415
Short name T635
Test name
Test status
Simulation time 21039984 ps
CPU time 0.71 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:56:57 PM PDT 24
Peak memory 206452 kb
Host smart-94ab3c92-8022-4de0-8d1f-e711c6d2a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325114415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1325114415
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3588623259
Short name T938
Test name
Test status
Simulation time 42495620 ps
CPU time 0.82 seconds
Started Aug 18 04:56:58 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 206792 kb
Host smart-d6f0550e-c5d3-407c-a82b-f5fd1711dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588623259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3588623259
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.661165283
Short name T122
Test name
Test status
Simulation time 8332531501 ps
CPU time 9.9 seconds
Started Aug 18 04:56:56 PM PDT 24
Finished Aug 18 04:57:06 PM PDT 24
Peak memory 233648 kb
Host smart-75347e5d-76aa-450a-a645-12c995084f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661165283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.661165283
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3629437902
Short name T895
Test name
Test status
Simulation time 48877817 ps
CPU time 0.75 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:53:57 PM PDT 24
Peak memory 206476 kb
Host smart-662c5334-4e86-4041-98d8-19c30cdb689a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629437902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
629437902
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.824327941
Short name T876
Test name
Test status
Simulation time 98037436 ps
CPU time 3.91 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:54:00 PM PDT 24
Peak memory 233520 kb
Host smart-fce24cb7-2c80-47cd-81db-f45976794e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824327941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.824327941
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.738158291
Short name T398
Test name
Test status
Simulation time 15394125 ps
CPU time 0.79 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:45 PM PDT 24
Peak memory 207348 kb
Host smart-d7b3126b-c3b2-4012-ab49-b8c37ed15551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738158291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.738158291
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1420359307
Short name T717
Test name
Test status
Simulation time 15061049832 ps
CPU time 51.16 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:54:47 PM PDT 24
Peak memory 252324 kb
Host smart-8f84083d-5839-476d-8782-f30f3bb5a4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420359307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1420359307
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.40899640
Short name T207
Test name
Test status
Simulation time 258365374831 ps
CPU time 616.43 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 05:04:11 PM PDT 24
Peak memory 266296 kb
Host smart-3ff50c90-a0f9-486e-a626-212f0a8991b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40899640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.40899640
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3351501268
Short name T974
Test name
Test status
Simulation time 84095656645 ps
CPU time 75.77 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:55:11 PM PDT 24
Peak memory 257276 kb
Host smart-f09506ff-ba60-4b4d-9a6c-11a91ff4800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351501268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3351501268
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1667767132
Short name T909
Test name
Test status
Simulation time 684060220 ps
CPU time 12.76 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:54:09 PM PDT 24
Peak memory 233548 kb
Host smart-c429228a-4578-4d6a-bced-9172da714584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667767132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1667767132
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.217199370
Short name T956
Test name
Test status
Simulation time 16318881032 ps
CPU time 81.81 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:55:15 PM PDT 24
Peak memory 256760 kb
Host smart-1ee33e2c-7959-4a1a-ba7a-62e09d4606e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217199370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
217199370
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.524426068
Short name T668
Test name
Test status
Simulation time 335587891 ps
CPU time 3.56 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:53:49 PM PDT 24
Peak memory 225376 kb
Host smart-8dfdf05a-6ac5-4fba-8721-ebc23064bcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524426068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.524426068
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1411487503
Short name T973
Test name
Test status
Simulation time 171498307 ps
CPU time 2.44 seconds
Started Aug 18 04:53:46 PM PDT 24
Finished Aug 18 04:53:48 PM PDT 24
Peak memory 225372 kb
Host smart-2ed007c0-78ca-45d7-aaee-c52b1807f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411487503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1411487503
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3462538496
Short name T839
Test name
Test status
Simulation time 24031319639 ps
CPU time 18.44 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:54:04 PM PDT 24
Peak memory 238652 kb
Host smart-40add1ef-501c-40c0-8dac-c4a1d28a4098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462538496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3462538496
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3460610191
Short name T37
Test name
Test status
Simulation time 1797595539 ps
CPU time 9.96 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:54 PM PDT 24
Peak memory 250636 kb
Host smart-0a710091-2c64-4079-9799-331654ff9973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460610191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3460610191
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2476645550
Short name T994
Test name
Test status
Simulation time 92561932 ps
CPU time 3.89 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:53:58 PM PDT 24
Peak memory 223436 kb
Host smart-dba0c217-f477-453b-b2f4-26c9673d9565
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2476645550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2476645550
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3819062570
Short name T85
Test name
Test status
Simulation time 518824356 ps
CPU time 1.01 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:53:54 PM PDT 24
Peak memory 236476 kb
Host smart-985eecbe-4442-4250-a85d-b94db9fbf7fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819062570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3819062570
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.373543099
Short name T785
Test name
Test status
Simulation time 35996355724 ps
CPU time 179.1 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:56:53 PM PDT 24
Peak memory 253536 kb
Host smart-8c08ff84-9e91-4577-b3f5-526828297cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373543099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.373543099
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1435469316
Short name T774
Test name
Test status
Simulation time 271442038 ps
CPU time 6.2 seconds
Started Aug 18 04:53:43 PM PDT 24
Finished Aug 18 04:53:49 PM PDT 24
Peak memory 220044 kb
Host smart-ed88264a-fb1f-44a5-aac0-3cbfd2eac447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435469316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1435469316
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2353432630
Short name T735
Test name
Test status
Simulation time 3148233823 ps
CPU time 5.92 seconds
Started Aug 18 04:53:46 PM PDT 24
Finished Aug 18 04:53:52 PM PDT 24
Peak memory 217200 kb
Host smart-182410e5-e2b0-4fac-9a4b-e0ea6cfa8792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353432630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2353432630
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2704875451
Short name T579
Test name
Test status
Simulation time 183471486 ps
CPU time 0.92 seconds
Started Aug 18 04:53:45 PM PDT 24
Finished Aug 18 04:53:46 PM PDT 24
Peak memory 207756 kb
Host smart-6a2efee0-d43e-49ba-b71a-42df3bd584a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704875451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2704875451
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.973391407
Short name T578
Test name
Test status
Simulation time 40537433 ps
CPU time 0.82 seconds
Started Aug 18 04:53:44 PM PDT 24
Finished Aug 18 04:53:45 PM PDT 24
Peak memory 206700 kb
Host smart-a4ffe871-9f95-4a51-b10c-628abd8358f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973391407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.973391407
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1491231099
Short name T604
Test name
Test status
Simulation time 3300802673 ps
CPU time 7.02 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:54:01 PM PDT 24
Peak memory 225380 kb
Host smart-e3c2f638-2c0f-430c-97dc-9a1f2bcfdb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491231099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1491231099
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1698694947
Short name T404
Test name
Test status
Simulation time 12594471 ps
CPU time 0.73 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:20 PM PDT 24
Peak memory 206244 kb
Host smart-1f44e05a-ed91-4986-933c-eb90415338ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698694947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1698694947
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3954911344
Short name T282
Test name
Test status
Simulation time 337039375 ps
CPU time 2.78 seconds
Started Aug 18 04:57:10 PM PDT 24
Finished Aug 18 04:57:13 PM PDT 24
Peak memory 233556 kb
Host smart-5dab5493-8639-49af-8cb0-662a555c8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954911344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3954911344
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3709893603
Short name T755
Test name
Test status
Simulation time 16624020 ps
CPU time 0.76 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 04:57:10 PM PDT 24
Peak memory 207736 kb
Host smart-ce92422f-5047-42ce-a7ac-7410062903a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709893603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3709893603
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3207782220
Short name T291
Test name
Test status
Simulation time 2086399278 ps
CPU time 25.96 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:34 PM PDT 24
Peak memory 252220 kb
Host smart-e35e4a3a-5432-46b8-96d4-f0b60a766d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207782220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3207782220
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4017484919
Short name T925
Test name
Test status
Simulation time 29076386303 ps
CPU time 267.12 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 05:01:36 PM PDT 24
Peak memory 249996 kb
Host smart-d727694b-39ae-46f2-a941-bd5496593e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017484919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4017484919
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1901687088
Short name T643
Test name
Test status
Simulation time 29498112022 ps
CPU time 266.06 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 05:01:34 PM PDT 24
Peak memory 255528 kb
Host smart-96b3f1f9-cd0b-45d8-b0b9-a167c5d42d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901687088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1901687088
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3481836877
Short name T726
Test name
Test status
Simulation time 65814808 ps
CPU time 2.22 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 04:57:11 PM PDT 24
Peak memory 225388 kb
Host smart-67d26b97-c49a-4f75-8e2a-0d30f266bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481836877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3481836877
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1972749364
Short name T793
Test name
Test status
Simulation time 167008738284 ps
CPU time 322.92 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 05:02:31 PM PDT 24
Peak memory 250248 kb
Host smart-7bce52ba-ccd9-4efc-8006-8500cb6c51b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972749364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1972749364
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.519911663
Short name T901
Test name
Test status
Simulation time 1445478105 ps
CPU time 9.68 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:57:17 PM PDT 24
Peak memory 233488 kb
Host smart-6079350a-ecc7-480f-8933-4299a5dda4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519911663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.519911663
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3514449861
Short name T595
Test name
Test status
Simulation time 757523810 ps
CPU time 7.78 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:57:15 PM PDT 24
Peak memory 228860 kb
Host smart-61f29979-faf8-41fc-afec-20862ff6be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514449861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3514449861
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3226989602
Short name T297
Test name
Test status
Simulation time 546561759 ps
CPU time 3.42 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:57:11 PM PDT 24
Peak memory 225300 kb
Host smart-04ed0d48-84ab-410d-9799-1e8965d748da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226989602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3226989602
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1172950427
Short name T564
Test name
Test status
Simulation time 1350186885 ps
CPU time 5.95 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:14 PM PDT 24
Peak memory 233536 kb
Host smart-8c7b83a0-77ea-4fc3-83be-353fe6748fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172950427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1172950427
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1982371881
Short name T473
Test name
Test status
Simulation time 1957391942 ps
CPU time 20.86 seconds
Started Aug 18 04:57:10 PM PDT 24
Finished Aug 18 04:57:31 PM PDT 24
Peak memory 220692 kb
Host smart-b35badc6-a749-41f4-a514-cdefd50cc956
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1982371881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1982371881
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2573239668
Short name T162
Test name
Test status
Simulation time 110205332416 ps
CPU time 268.96 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 05:01:37 PM PDT 24
Peak memory 258308 kb
Host smart-0295ed40-56a4-4ad9-b97d-090034e14de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573239668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2573239668
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.52084217
Short name T866
Test name
Test status
Simulation time 11732974586 ps
CPU time 29.92 seconds
Started Aug 18 04:57:10 PM PDT 24
Finished Aug 18 04:57:40 PM PDT 24
Peak memory 217496 kb
Host smart-f2e2c11f-e411-475b-b462-ff6236b21165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52084217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.52084217
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2982619569
Short name T333
Test name
Test status
Simulation time 2052297488 ps
CPU time 7.29 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 04:57:17 PM PDT 24
Peak memory 217216 kb
Host smart-6eb03673-acfa-4b00-8ec4-ca4753ad87c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982619569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2982619569
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1600931169
Short name T587
Test name
Test status
Simulation time 84813958 ps
CPU time 1.35 seconds
Started Aug 18 04:57:08 PM PDT 24
Finished Aug 18 04:57:09 PM PDT 24
Peak memory 217080 kb
Host smart-05e026d9-a41a-4e7d-ad54-72487542b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600931169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1600931169
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.12288707
Short name T341
Test name
Test status
Simulation time 157067414 ps
CPU time 0.74 seconds
Started Aug 18 04:57:07 PM PDT 24
Finished Aug 18 04:57:08 PM PDT 24
Peak memory 206768 kb
Host smart-63d43a2e-5567-469f-af60-9b92d7386653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12288707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.12288707
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2022968465
Short name T639
Test name
Test status
Simulation time 26367389891 ps
CPU time 19.48 seconds
Started Aug 18 04:57:09 PM PDT 24
Finished Aug 18 04:57:28 PM PDT 24
Peak memory 233636 kb
Host smart-3a0954b7-fc24-4791-a5cb-b92c3214a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022968465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2022968465
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2028217068
Short name T414
Test name
Test status
Simulation time 14685662 ps
CPU time 0.7 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 04:57:18 PM PDT 24
Peak memory 206176 kb
Host smart-4ebbba22-9623-460b-ab4e-c070d0eb249e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028217068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2028217068
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.672279989
Short name T251
Test name
Test status
Simulation time 246300425 ps
CPU time 4.11 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:23 PM PDT 24
Peak memory 233512 kb
Host smart-44d3204c-b02c-45e9-8fab-cff49bf983df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672279989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.672279989
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1909094220
Short name T779
Test name
Test status
Simulation time 23563411 ps
CPU time 0.75 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 206320 kb
Host smart-2cb2103b-9ed3-4f0e-8e9e-280af81b3375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909094220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1909094220
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3646528549
Short name T520
Test name
Test status
Simulation time 60213328 ps
CPU time 1.06 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:22 PM PDT 24
Peak memory 216900 kb
Host smart-4e978a05-aff7-435b-a49b-446c2b1b2e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646528549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3646528549
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3833343730
Short name T753
Test name
Test status
Simulation time 19826791182 ps
CPU time 112.65 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:59:14 PM PDT 24
Peak memory 251844 kb
Host smart-865e4021-90ed-4cbf-9109-f8c42a6dde39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833343730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3833343730
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2586736745
Short name T603
Test name
Test status
Simulation time 82963345456 ps
CPU time 189.44 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 05:00:28 PM PDT 24
Peak memory 250124 kb
Host smart-3c3d0e5d-5a3a-4065-9efe-ecbb8fd875d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586736745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2586736745
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.638874805
Short name T859
Test name
Test status
Simulation time 15569108993 ps
CPU time 54.15 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:58:16 PM PDT 24
Peak memory 241916 kb
Host smart-8d558d45-2c3b-4b2a-aa00-65d24b023ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638874805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.638874805
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2309025231
Short name T850
Test name
Test status
Simulation time 12077705809 ps
CPU time 75.32 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:58:36 PM PDT 24
Peak memory 251152 kb
Host smart-0fd2a232-38f5-4046-9d11-9a309768450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309025231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2309025231
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2643373552
Short name T935
Test name
Test status
Simulation time 1164064123 ps
CPU time 7.19 seconds
Started Aug 18 04:57:22 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 233540 kb
Host smart-7f3e9556-42ea-4b71-b869-b5a317b9dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643373552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2643373552
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1229149731
Short name T764
Test name
Test status
Simulation time 958927040 ps
CPU time 10.83 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 234484 kb
Host smart-afbb67dd-0117-4b70-b8be-c25b3338d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229149731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1229149731
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2247390675
Short name T296
Test name
Test status
Simulation time 4836995996 ps
CPU time 14.49 seconds
Started Aug 18 04:57:22 PM PDT 24
Finished Aug 18 04:57:36 PM PDT 24
Peak memory 233660 kb
Host smart-9fe86a1b-d4df-4c5f-ad04-2b30e174fd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247390675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2247390675
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1419589393
Short name T966
Test name
Test status
Simulation time 142092591 ps
CPU time 2.3 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 233492 kb
Host smart-563e43bf-f40a-460b-8b17-9b5387100eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419589393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1419589393
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2107441570
Short name T650
Test name
Test status
Simulation time 215701638 ps
CPU time 4.55 seconds
Started Aug 18 04:57:22 PM PDT 24
Finished Aug 18 04:57:26 PM PDT 24
Peak memory 223604 kb
Host smart-a74b28c1-6310-4852-bcbd-401663492e15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2107441570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2107441570
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1371797119
Short name T849
Test name
Test status
Simulation time 73152579616 ps
CPU time 194.43 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 05:00:33 PM PDT 24
Peak memory 256540 kb
Host smart-f126b08f-d2e7-4f42-a5b2-7fcb7b3fc8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371797119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1371797119
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2806700878
Short name T681
Test name
Test status
Simulation time 2306176265 ps
CPU time 13.12 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:33 PM PDT 24
Peak memory 217048 kb
Host smart-fbe07c4a-caae-477a-bc99-4d81659bb33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806700878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2806700878
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1495542290
Short name T355
Test name
Test status
Simulation time 765066369 ps
CPU time 2.27 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:23 PM PDT 24
Peak memory 217148 kb
Host smart-b7ef46cd-3aac-42ce-b5e6-3f00e460faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495542290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1495542290
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.844498539
Short name T937
Test name
Test status
Simulation time 72004445 ps
CPU time 1.03 seconds
Started Aug 18 04:57:23 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 208068 kb
Host smart-b66f7780-b804-4542-addb-4ecdd1b89f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844498539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.844498539
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.685687188
Short name T552
Test name
Test status
Simulation time 22887435 ps
CPU time 0.79 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:20 PM PDT 24
Peak memory 206884 kb
Host smart-c9252d4b-0001-4685-81a8-37f28f7e387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685687188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.685687188
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1449824806
Short name T641
Test name
Test status
Simulation time 867621363 ps
CPU time 10.77 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:31 PM PDT 24
Peak memory 241744 kb
Host smart-9904f1d2-4c99-4bae-bede-2e9f1526c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449824806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1449824806
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3311653958
Short name T811
Test name
Test status
Simulation time 40344842 ps
CPU time 0.72 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:22 PM PDT 24
Peak memory 206216 kb
Host smart-17063822-d6a4-4374-a69a-392b4f66e22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311653958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3311653958
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2478128288
Short name T975
Test name
Test status
Simulation time 414066041 ps
CPU time 3.61 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 225132 kb
Host smart-04c48735-8149-42fd-8399-2c6d531c5781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478128288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2478128288
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2680665885
Short name T397
Test name
Test status
Simulation time 19505391 ps
CPU time 0.79 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 206396 kb
Host smart-d15b5791-8638-471c-8c31-8cb93d6d190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680665885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2680665885
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3510118604
Short name T583
Test name
Test status
Simulation time 7525573257 ps
CPU time 75.79 seconds
Started Aug 18 04:57:24 PM PDT 24
Finished Aug 18 04:58:40 PM PDT 24
Peak memory 250264 kb
Host smart-d74d37d7-3af7-4cb5-abd7-4b36e6bf10d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510118604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3510118604
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.693617150
Short name T509
Test name
Test status
Simulation time 22931353461 ps
CPU time 114.87 seconds
Started Aug 18 04:57:22 PM PDT 24
Finished Aug 18 04:59:17 PM PDT 24
Peak memory 250492 kb
Host smart-b9e8d4b5-b9bf-4837-8a2f-36e7efeca269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693617150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.693617150
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4213258167
Short name T648
Test name
Test status
Simulation time 207157784 ps
CPU time 7.69 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:28 PM PDT 24
Peak memory 240564 kb
Host smart-4e6c16a9-5d71-43f3-960e-73b22f92d5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213258167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4213258167
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2965029440
Short name T835
Test name
Test status
Simulation time 2287917508 ps
CPU time 18.13 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 225392 kb
Host smart-7a3244db-a22a-4f7a-a580-f824ba77b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965029440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2965029440
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2403557177
Short name T168
Test name
Test status
Simulation time 3578226617 ps
CPU time 23.22 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 04:57:42 PM PDT 24
Peak memory 233576 kb
Host smart-ce9073ee-0ae1-4b76-84a5-504cef8eb944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403557177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2403557177
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3804434342
Short name T792
Test name
Test status
Simulation time 1560235293 ps
CPU time 4.05 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 225360 kb
Host smart-bb7ab8cc-0bce-4575-85ef-db4b59fc629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804434342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3804434342
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2357625148
Short name T533
Test name
Test status
Simulation time 282778054 ps
CPU time 4.7 seconds
Started Aug 18 04:57:24 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 225356 kb
Host smart-0d1c76a6-15d6-4df3-bf92-6cd820d97621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357625148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2357625148
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3785991692
Short name T688
Test name
Test status
Simulation time 1428977077 ps
CPU time 7.4 seconds
Started Aug 18 04:57:18 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 233600 kb
Host smart-8971d0c4-697b-4eab-8d32-6528807d7614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785991692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3785991692
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3638814410
Short name T960
Test name
Test status
Simulation time 808549784 ps
CPU time 5.24 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 223848 kb
Host smart-a6489cb2-dc4b-4739-b6b6-e9ac85dd02cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3638814410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3638814410
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2279988628
Short name T161
Test name
Test status
Simulation time 112930185 ps
CPU time 1.12 seconds
Started Aug 18 04:57:22 PM PDT 24
Finished Aug 18 04:57:23 PM PDT 24
Peak memory 207972 kb
Host smart-638ab4b6-5567-451f-9c77-b56fa43b1e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279988628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2279988628
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4262509345
Short name T653
Test name
Test status
Simulation time 21333810418 ps
CPU time 52.98 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:58:13 PM PDT 24
Peak memory 217240 kb
Host smart-d75d8f66-065c-430d-ae44-e37776cfc7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262509345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4262509345
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.235349316
Short name T344
Test name
Test status
Simulation time 14604405455 ps
CPU time 17.31 seconds
Started Aug 18 04:57:23 PM PDT 24
Finished Aug 18 04:57:40 PM PDT 24
Peak memory 217192 kb
Host smart-7f30ab00-0f82-4538-ab9d-4f115017ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235349316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.235349316
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.935708039
Short name T613
Test name
Test status
Simulation time 33872390 ps
CPU time 1.06 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:20 PM PDT 24
Peak memory 208216 kb
Host smart-94d7ca37-b3e0-4abb-9db6-ac9d520f072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935708039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.935708039
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.22539766
Short name T346
Test name
Test status
Simulation time 75038907 ps
CPU time 0.89 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:21 PM PDT 24
Peak memory 207812 kb
Host smart-6e6bea71-732d-4ea8-990f-a827856206ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22539766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.22539766
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.603185202
Short name T525
Test name
Test status
Simulation time 6312945388 ps
CPU time 7.23 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:28 PM PDT 24
Peak memory 233748 kb
Host smart-f3e14ab6-12f9-4737-ae33-d36e82ac1abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603185202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.603185202
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2045162038
Short name T528
Test name
Test status
Simulation time 37530118 ps
CPU time 0.74 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:33 PM PDT 24
Peak memory 206284 kb
Host smart-ed642154-f0b0-4939-87f8-c65b7465d263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045162038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2045162038
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.398882661
Short name T242
Test name
Test status
Simulation time 1180749481 ps
CPU time 6.39 seconds
Started Aug 18 04:57:25 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 233536 kb
Host smart-e436c7e1-28ab-4640-bbae-24a362897db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398882661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.398882661
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1872864406
Short name T571
Test name
Test status
Simulation time 68052975 ps
CPU time 0.8 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:20 PM PDT 24
Peak memory 207740 kb
Host smart-7eed2813-2f5f-414d-9397-65a0e305cd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872864406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1872864406
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1029092274
Short name T869
Test name
Test status
Simulation time 34138075432 ps
CPU time 137.96 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:59:49 PM PDT 24
Peak memory 258200 kb
Host smart-e3a9d0f4-0a48-4839-bb6c-b3f3883def38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029092274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1029092274
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1117734711
Short name T248
Test name
Test status
Simulation time 4278128658 ps
CPU time 33.42 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:58:02 PM PDT 24
Peak memory 241500 kb
Host smart-6cbba8a9-1e24-4405-b38a-26e2f9a32ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117734711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1117734711
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1489687227
Short name T137
Test name
Test status
Simulation time 7680266183 ps
CPU time 98.69 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:59:07 PM PDT 24
Peak memory 257900 kb
Host smart-20dcf6e7-24c6-4eac-981e-7f34770de615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489687227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1489687227
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2445567755
Short name T527
Test name
Test status
Simulation time 301164755 ps
CPU time 4.48 seconds
Started Aug 18 04:57:20 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 225388 kb
Host smart-ccb16985-4bd8-412b-bdf2-09aef34ba396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445567755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2445567755
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.883690906
Short name T860
Test name
Test status
Simulation time 37096363079 ps
CPU time 71.32 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:58:32 PM PDT 24
Peak memory 241944 kb
Host smart-5edb1e2f-75b9-48b2-ab27-99a11f6857fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883690906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.883690906
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.891281907
Short name T664
Test name
Test status
Simulation time 589670645 ps
CPU time 2.85 seconds
Started Aug 18 04:57:22 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 233540 kb
Host smart-65d06076-dff3-4a5a-b25e-32ba33fca4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891281907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.891281907
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3739718394
Short name T523
Test name
Test status
Simulation time 482494822 ps
CPU time 2.66 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 225252 kb
Host smart-6264bdce-1695-4e25-929c-39b8f900ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739718394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3739718394
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.826694078
Short name T586
Test name
Test status
Simulation time 6176393414 ps
CPU time 18.13 seconds
Started Aug 18 04:57:26 PM PDT 24
Finished Aug 18 04:57:44 PM PDT 24
Peak memory 233740 kb
Host smart-20a89ef8-52c8-4da5-bba4-4f9a4feac4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826694078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.826694078
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1908875842
Short name T106
Test name
Test status
Simulation time 631413600 ps
CPU time 2.85 seconds
Started Aug 18 04:57:24 PM PDT 24
Finished Aug 18 04:57:27 PM PDT 24
Peak memory 225400 kb
Host smart-180ecdae-3790-4834-8989-5cbefc7ca466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908875842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1908875842
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1711863441
Short name T932
Test name
Test status
Simulation time 239434154 ps
CPU time 4.88 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:34 PM PDT 24
Peak memory 223700 kb
Host smart-933b4901-fffa-4f41-a5e3-05931ce4f16e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1711863441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1711863441
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2215883818
Short name T17
Test name
Test status
Simulation time 155885140 ps
CPU time 0.91 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:31 PM PDT 24
Peak memory 207308 kb
Host smart-c62da420-9312-4203-a2b9-496669f4823c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215883818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2215883818
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.148824174
Short name T744
Test name
Test status
Simulation time 11761633237 ps
CPU time 21.98 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 217328 kb
Host smart-380305ea-596a-4d15-b858-a04e0bd6ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148824174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.148824174
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1638737779
Short name T682
Test name
Test status
Simulation time 257538706 ps
CPU time 3.51 seconds
Started Aug 18 04:57:21 PM PDT 24
Finished Aug 18 04:57:25 PM PDT 24
Peak memory 217128 kb
Host smart-5ab08cdc-0450-41a1-9ebe-ea18c10c6c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638737779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1638737779
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2984846225
Short name T696
Test name
Test status
Simulation time 62757894 ps
CPU time 0.79 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:20 PM PDT 24
Peak memory 206736 kb
Host smart-2c7b6315-ec7b-4fdf-9e58-f07fb2265ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984846225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2984846225
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2065251588
Short name T229
Test name
Test status
Simulation time 94604417 ps
CPU time 2.35 seconds
Started Aug 18 04:57:19 PM PDT 24
Finished Aug 18 04:57:22 PM PDT 24
Peak memory 233460 kb
Host smart-8373bb70-0d66-478b-b532-f10aab9420b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065251588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2065251588
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3960020888
Short name T78
Test name
Test status
Simulation time 14442129 ps
CPU time 0.73 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 205644 kb
Host smart-d8cf40a2-7826-40e7-a0eb-40885b50f722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960020888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3960020888
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2053066498
Short name T968
Test name
Test status
Simulation time 2535269326 ps
CPU time 9.37 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:40 PM PDT 24
Peak memory 233908 kb
Host smart-f1836d28-456c-42d5-a972-7b19d9dff9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053066498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2053066498
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3347588905
Short name T342
Test name
Test status
Simulation time 15997144 ps
CPU time 0.75 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 206692 kb
Host smart-150903f4-3951-426f-900c-a303f5465866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347588905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3347588905
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3984482299
Short name T261
Test name
Test status
Simulation time 1143446748 ps
CPU time 23.33 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:53 PM PDT 24
Peak memory 235520 kb
Host smart-6ad04c59-b2f0-4670-a412-d10d702de06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984482299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3984482299
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3861791084
Short name T167
Test name
Test status
Simulation time 4712730016 ps
CPU time 34.42 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:58:02 PM PDT 24
Peak memory 238768 kb
Host smart-b1e6549d-fd84-44f3-a3a7-79d714ce7e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861791084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3861791084
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2689683788
Short name T724
Test name
Test status
Simulation time 183653230 ps
CPU time 3.9 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 219648 kb
Host smart-78ea550c-d4ff-429d-a2a5-d9ef45b9fcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689683788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2689683788
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3298484908
Short name T102
Test name
Test status
Simulation time 6016781387 ps
CPU time 11.86 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 241780 kb
Host smart-6232e33b-d797-4ba1-a4c6-7f0432974664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298484908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3298484908
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.742199713
Short name T843
Test name
Test status
Simulation time 11264577724 ps
CPU time 22.06 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:52 PM PDT 24
Peak memory 225492 kb
Host smart-4bd1287b-1fda-41cc-87ca-939e28e17b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742199713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.742199713
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3070398138
Short name T407
Test name
Test status
Simulation time 413485586 ps
CPU time 6.44 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:37 PM PDT 24
Peak memory 238796 kb
Host smart-95aa9bf3-3a7c-44a6-9c2e-eee020673459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070398138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3070398138
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3473377639
Short name T877
Test name
Test status
Simulation time 2053315329 ps
CPU time 3.27 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:35 PM PDT 24
Peak memory 225328 kb
Host smart-4c528494-57f0-457b-a521-595473611f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473377639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3473377639
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4212089566
Short name T949
Test name
Test status
Simulation time 1331836042 ps
CPU time 4.92 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:38 PM PDT 24
Peak memory 225248 kb
Host smart-04607ecb-50bb-4005-826a-815e66973a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212089566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4212089566
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2815464409
Short name T418
Test name
Test status
Simulation time 1639592042 ps
CPU time 3.96 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:36 PM PDT 24
Peak memory 221008 kb
Host smart-128da618-8882-43a8-8d3f-241f80994a99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2815464409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2815464409
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4127665051
Short name T723
Test name
Test status
Simulation time 158390866 ps
CPU time 0.93 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 207360 kb
Host smart-4bbd0cdc-681d-4583-9946-2c7da0cf6919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127665051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4127665051
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3556469695
Short name T522
Test name
Test status
Simulation time 2346559598 ps
CPU time 12.49 seconds
Started Aug 18 04:57:36 PM PDT 24
Finished Aug 18 04:57:48 PM PDT 24
Peak memory 217324 kb
Host smart-3222524c-61ab-40e5-b021-bd67602a94dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556469695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3556469695
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2326404974
Short name T29
Test name
Test status
Simulation time 783774236 ps
CPU time 4.09 seconds
Started Aug 18 04:57:28 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 217136 kb
Host smart-12233b77-97d1-4924-b84f-24d0405c116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326404974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2326404974
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3839674967
Short name T383
Test name
Test status
Simulation time 91793190 ps
CPU time 1.18 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 217156 kb
Host smart-d44746d1-243d-432b-aeab-b119746a934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839674967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3839674967
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.678345969
Short name T529
Test name
Test status
Simulation time 37275508 ps
CPU time 0.72 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:29 PM PDT 24
Peak memory 206828 kb
Host smart-7e529688-c0b3-4277-988c-d6dd0076d92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678345969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.678345969
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2837118200
Short name T277
Test name
Test status
Simulation time 7670602192 ps
CPU time 9.72 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 225316 kb
Host smart-b8598aab-ae10-41e5-9e0f-c6d8d198a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837118200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2837118200
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1487250699
Short name T412
Test name
Test status
Simulation time 21385665 ps
CPU time 0.73 seconds
Started Aug 18 04:57:36 PM PDT 24
Finished Aug 18 04:57:37 PM PDT 24
Peak memory 206272 kb
Host smart-fdb77696-089f-417e-905e-4d19c9c66825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487250699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1487250699
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3127423641
Short name T750
Test name
Test status
Simulation time 4490717759 ps
CPU time 19.99 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:50 PM PDT 24
Peak memory 225452 kb
Host smart-f232a9db-bbf7-452d-9903-5991be53a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127423641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3127423641
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1443669965
Short name T695
Test name
Test status
Simulation time 33678103 ps
CPU time 0.79 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 207628 kb
Host smart-abb0a12e-6acc-4980-a99a-9883ade48004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443669965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1443669965
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1869399456
Short name T958
Test name
Test status
Simulation time 17671168 ps
CPU time 0.76 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:31 PM PDT 24
Peak memory 216608 kb
Host smart-2215965b-1e54-4384-a0ae-3ce0809d5096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869399456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1869399456
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1630266193
Short name T320
Test name
Test status
Simulation time 4204976217 ps
CPU time 30.17 seconds
Started Aug 18 04:57:33 PM PDT 24
Finished Aug 18 04:58:03 PM PDT 24
Peak memory 240372 kb
Host smart-0f7374a3-1e4c-4298-bd81-a882a692753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630266193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1630266193
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2429078019
Short name T939
Test name
Test status
Simulation time 602174743 ps
CPU time 9.13 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 238612 kb
Host smart-6df1bb9a-988b-4cab-972a-0edca9c9ff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429078019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2429078019
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.4042207401
Short name T508
Test name
Test status
Simulation time 3913991865 ps
CPU time 31.8 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:58:03 PM PDT 24
Peak memory 233716 kb
Host smart-c29be992-2df3-4d25-b194-1bc46b299505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042207401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.4042207401
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.212336655
Short name T745
Test name
Test status
Simulation time 325312400 ps
CPU time 4.42 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:37 PM PDT 24
Peak memory 233792 kb
Host smart-b362f067-a281-4c8b-8d6a-8145c85ed886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212336655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.212336655
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1657984540
Short name T707
Test name
Test status
Simulation time 6673674567 ps
CPU time 29.02 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:59 PM PDT 24
Peak memory 233568 kb
Host smart-d2d360aa-df0f-4870-a9a7-0a3cf8cc144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657984540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1657984540
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1637527877
Short name T56
Test name
Test status
Simulation time 203985839721 ps
CPU time 56.46 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:58:26 PM PDT 24
Peak memory 251544 kb
Host smart-a9d61986-ca77-4c6c-b4d6-2ff9ea1cc32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637527877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1637527877
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2299362353
Short name T247
Test name
Test status
Simulation time 12319596939 ps
CPU time 9.46 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:40 PM PDT 24
Peak memory 225208 kb
Host smart-1fda8fb0-911f-4c4b-92b9-6d96274ab65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299362353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2299362353
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4284062296
Short name T148
Test name
Test status
Simulation time 5764708776 ps
CPU time 8.79 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:38 PM PDT 24
Peak memory 220140 kb
Host smart-2ebdea7d-4209-4321-92f8-dd383d0dd662
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284062296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4284062296
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1195933674
Short name T159
Test name
Test status
Simulation time 7383917054 ps
CPU time 31.48 seconds
Started Aug 18 04:57:36 PM PDT 24
Finished Aug 18 04:58:07 PM PDT 24
Peak memory 225592 kb
Host smart-8a721595-586d-4eb8-820d-7f43b4e45cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195933674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1195933674
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1659430590
Short name T324
Test name
Test status
Simulation time 9429446018 ps
CPU time 15.01 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:47 PM PDT 24
Peak memory 217356 kb
Host smart-7b7a73c9-b2ce-4640-859d-813b8352d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659430590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1659430590
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3013028286
Short name T721
Test name
Test status
Simulation time 1658588288 ps
CPU time 5.02 seconds
Started Aug 18 04:57:27 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 217092 kb
Host smart-42adde1f-4828-4f13-91f0-efe939da5ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013028286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3013028286
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1189067876
Short name T813
Test name
Test status
Simulation time 430604947 ps
CPU time 2.41 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:35 PM PDT 24
Peak memory 217160 kb
Host smart-e571507d-5d90-47d5-9da6-98b017d96d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189067876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1189067876
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3571063041
Short name T820
Test name
Test status
Simulation time 128877899 ps
CPU time 0.87 seconds
Started Aug 18 04:57:29 PM PDT 24
Finished Aug 18 04:57:30 PM PDT 24
Peak memory 206788 kb
Host smart-16ab2498-5fe8-491e-baf8-376780329066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571063041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3571063041
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.593636249
Short name T3
Test name
Test status
Simulation time 370295079 ps
CPU time 3.1 seconds
Started Aug 18 04:57:30 PM PDT 24
Finished Aug 18 04:57:33 PM PDT 24
Peak memory 233420 kb
Host smart-70c6c937-5275-4f67-b07d-52367f605c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593636249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.593636249
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2867523092
Short name T622
Test name
Test status
Simulation time 10912078 ps
CPU time 0.69 seconds
Started Aug 18 04:57:38 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 206180 kb
Host smart-856eee62-27ca-4831-ad9d-6ab5f309e171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867523092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2867523092
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3640457756
Short name T358
Test name
Test status
Simulation time 64114082 ps
CPU time 2.76 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 233596 kb
Host smart-55f3a677-da8c-4ffc-8e19-45233ffab49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640457756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3640457756
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3261633456
Short name T986
Test name
Test status
Simulation time 17620229 ps
CPU time 0.75 seconds
Started Aug 18 04:57:31 PM PDT 24
Finished Aug 18 04:57:32 PM PDT 24
Peak memory 206716 kb
Host smart-55b2a5e9-f870-49ee-9bbd-c188d7315d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261633456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3261633456
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1852695995
Short name T295
Test name
Test status
Simulation time 33683877038 ps
CPU time 289.11 seconds
Started Aug 18 04:57:38 PM PDT 24
Finished Aug 18 05:02:27 PM PDT 24
Peak memory 253084 kb
Host smart-2a4da777-4f41-4420-bc12-99b382180686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852695995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1852695995
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2801680808
Short name T657
Test name
Test status
Simulation time 2756216528 ps
CPU time 68.27 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 266528 kb
Host smart-1efce3b4-8f42-45f4-931f-8ddbbbd8c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801680808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2801680808
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3384113794
Short name T733
Test name
Test status
Simulation time 435774773 ps
CPU time 9.11 seconds
Started Aug 18 04:57:41 PM PDT 24
Finished Aug 18 04:57:51 PM PDT 24
Peak memory 233492 kb
Host smart-3fc69aaf-cadf-4fda-8ec9-ce5a6388a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384113794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3384113794
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3952068769
Short name T57
Test name
Test status
Simulation time 2898322555 ps
CPU time 31.99 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:58:12 PM PDT 24
Peak memory 255520 kb
Host smart-2d6df124-3d99-4390-a86b-1ceb17f8787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952068769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3952068769
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1605821745
Short name T699
Test name
Test status
Simulation time 602172174 ps
CPU time 3.71 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 233384 kb
Host smart-8f45f20a-9712-4431-a6d7-7cd768178174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605821745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1605821745
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2729355228
Short name T38
Test name
Test status
Simulation time 544500206 ps
CPU time 14.33 seconds
Started Aug 18 04:57:47 PM PDT 24
Finished Aug 18 04:58:02 PM PDT 24
Peak memory 233560 kb
Host smart-80589e63-964a-497d-a013-6385b60e218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729355228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2729355228
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4166125635
Short name T667
Test name
Test status
Simulation time 2414359811 ps
CPU time 3.49 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 225452 kb
Host smart-249042f9-7fb6-471f-b805-9d5e0ef707d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166125635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4166125635
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2305989695
Short name T245
Test name
Test status
Simulation time 1383819375 ps
CPU time 7.53 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:48 PM PDT 24
Peak memory 225268 kb
Host smart-e5dd9382-a46f-4b82-8dfb-334ac2c79494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305989695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2305989695
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4100942146
Short name T385
Test name
Test status
Simulation time 631264892 ps
CPU time 8.23 seconds
Started Aug 18 04:57:41 PM PDT 24
Finished Aug 18 04:57:50 PM PDT 24
Peak memory 221024 kb
Host smart-ee0370e6-da26-4c26-8b6f-f9a1af73714e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4100942146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4100942146
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1333993276
Short name T299
Test name
Test status
Simulation time 33176801835 ps
CPU time 68.32 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:58:48 PM PDT 24
Peak memory 250108 kb
Host smart-0385fd82-9c11-4e88-a953-67269aa2f17a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333993276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1333993276
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4033617812
Short name T25
Test name
Test status
Simulation time 905024864 ps
CPU time 13.84 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:47 PM PDT 24
Peak memory 217224 kb
Host smart-6949f020-49e9-4ac9-ae2f-2593a696b182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033617812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4033617812
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3942974309
Short name T482
Test name
Test status
Simulation time 8645390675 ps
CPU time 4.24 seconds
Started Aug 18 04:57:32 PM PDT 24
Finished Aug 18 04:57:36 PM PDT 24
Peak memory 217348 kb
Host smart-121eb331-1533-43a4-9168-f4677dde05c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942974309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3942974309
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3626636592
Short name T711
Test name
Test status
Simulation time 76051728 ps
CPU time 1.21 seconds
Started Aug 18 04:57:38 PM PDT 24
Finished Aug 18 04:57:39 PM PDT 24
Peak memory 217052 kb
Host smart-f5481572-b3bc-421a-93b6-b13648a3e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626636592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3626636592
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2224656176
Short name T846
Test name
Test status
Simulation time 129762280 ps
CPU time 0.84 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 206688 kb
Host smart-6600a57e-ee89-4424-a370-13a4eded21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224656176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2224656176
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3808550348
Short name T254
Test name
Test status
Simulation time 31509050032 ps
CPU time 28.22 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:58:08 PM PDT 24
Peak memory 225424 kb
Host smart-dc456469-2482-4621-a479-fbe3bf863fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808550348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3808550348
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1428373458
Short name T915
Test name
Test status
Simulation time 47862452 ps
CPU time 0.71 seconds
Started Aug 18 04:57:47 PM PDT 24
Finished Aug 18 04:57:48 PM PDT 24
Peak memory 206588 kb
Host smart-bee728a2-8209-4c64-b857-4eeba943b17b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428373458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1428373458
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.536875189
Short name T334
Test name
Test status
Simulation time 1215783385 ps
CPU time 3.05 seconds
Started Aug 18 04:57:42 PM PDT 24
Finished Aug 18 04:57:46 PM PDT 24
Peak memory 225292 kb
Host smart-277f7ebd-069a-47f9-9495-ff1a78326eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536875189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.536875189
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3416071335
Short name T663
Test name
Test status
Simulation time 14368081 ps
CPU time 0.77 seconds
Started Aug 18 04:57:47 PM PDT 24
Finished Aug 18 04:57:47 PM PDT 24
Peak memory 207416 kb
Host smart-20814740-4cd1-4a53-b5dd-08d1b1808a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416071335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3416071335
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3744567546
Short name T462
Test name
Test status
Simulation time 1087976519 ps
CPU time 16.15 seconds
Started Aug 18 04:57:39 PM PDT 24
Finished Aug 18 04:57:55 PM PDT 24
Peak memory 241688 kb
Host smart-a088cebe-a69b-4109-9136-bd26a21e8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744567546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3744567546
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1303142510
Short name T1004
Test name
Test status
Simulation time 58879523085 ps
CPU time 275.15 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 05:02:15 PM PDT 24
Peak memory 267264 kb
Host smart-2d35c989-810c-4dab-a313-9977ea8d480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303142510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1303142510
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4134951901
Short name T93
Test name
Test status
Simulation time 16419087591 ps
CPU time 114.53 seconds
Started Aug 18 04:57:44 PM PDT 24
Finished Aug 18 04:59:38 PM PDT 24
Peak memory 266796 kb
Host smart-7e98fa69-35cb-48c4-9c55-65bfdea1afad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134951901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4134951901
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2447686863
Short name T483
Test name
Test status
Simulation time 157575182 ps
CPU time 4.31 seconds
Started Aug 18 04:57:42 PM PDT 24
Finished Aug 18 04:57:46 PM PDT 24
Peak memory 225404 kb
Host smart-80203818-f1ef-4449-ae8b-669d711a90b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447686863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2447686863
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1415028290
Short name T645
Test name
Test status
Simulation time 6302943906 ps
CPU time 20.7 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:58:01 PM PDT 24
Peak memory 225396 kb
Host smart-cfcd9c92-ec8e-4df2-9778-58499fbbffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415028290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1415028290
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2111488485
Short name T781
Test name
Test status
Simulation time 277672085 ps
CPU time 3.48 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 225324 kb
Host smart-697c14a1-0c0a-453b-b144-40614b149856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111488485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2111488485
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3958562066
Short name T976
Test name
Test status
Simulation time 3710836943 ps
CPU time 18.36 seconds
Started Aug 18 04:57:43 PM PDT 24
Finished Aug 18 04:58:02 PM PDT 24
Peak memory 250084 kb
Host smart-afe6e940-d2c3-4b40-a8a2-aff53391f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958562066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3958562066
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2525375580
Short name T919
Test name
Test status
Simulation time 172484899 ps
CPU time 2.83 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:43 PM PDT 24
Peak memory 225276 kb
Host smart-fb78d471-dc1b-48b5-a671-8198966d72aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525375580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2525375580
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.759591296
Short name T505
Test name
Test status
Simulation time 10997456335 ps
CPU time 24.13 seconds
Started Aug 18 04:57:38 PM PDT 24
Finished Aug 18 04:58:03 PM PDT 24
Peak memory 249960 kb
Host smart-60d8830f-af97-4b23-9046-f7261fe3a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759591296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.759591296
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.653726303
Short name T468
Test name
Test status
Simulation time 80956900 ps
CPU time 3.66 seconds
Started Aug 18 04:57:42 PM PDT 24
Finished Aug 18 04:57:46 PM PDT 24
Peak memory 219800 kb
Host smart-514d3959-81f5-4f7a-a2d7-afb24ab2a786
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=653726303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.653726303
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2731509787
Short name T963
Test name
Test status
Simulation time 643017258 ps
CPU time 1.17 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 208416 kb
Host smart-b3b332a3-0fb9-4d03-8c3a-adce8dc43ab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731509787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2731509787
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1486948504
Short name T984
Test name
Test status
Simulation time 3671104929 ps
CPU time 10.6 seconds
Started Aug 18 04:57:43 PM PDT 24
Finished Aug 18 04:57:53 PM PDT 24
Peak memory 217264 kb
Host smart-4b6e536f-51b2-487d-a081-cb959aee1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486948504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1486948504
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.217658815
Short name T30
Test name
Test status
Simulation time 381785448 ps
CPU time 3.12 seconds
Started Aug 18 04:57:41 PM PDT 24
Finished Aug 18 04:57:45 PM PDT 24
Peak memory 217240 kb
Host smart-2045b4ec-b014-454c-b779-f766ddc50791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217658815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.217658815
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1715702408
Short name T441
Test name
Test status
Simulation time 349572155 ps
CPU time 1.02 seconds
Started Aug 18 04:57:47 PM PDT 24
Finished Aug 18 04:57:48 PM PDT 24
Peak memory 208564 kb
Host smart-212b94b0-c003-4dbc-83d1-26c128b86fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715702408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1715702408
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1924027311
Short name T988
Test name
Test status
Simulation time 73979232 ps
CPU time 0.85 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 206812 kb
Host smart-49250138-1434-4491-b3ec-8df11fcd5040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924027311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1924027311
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2174572177
Short name T636
Test name
Test status
Simulation time 587021297 ps
CPU time 2.53 seconds
Started Aug 18 04:57:38 PM PDT 24
Finished Aug 18 04:57:41 PM PDT 24
Peak memory 225092 kb
Host smart-aca1170e-8c96-45d9-9a26-1cec66f9b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174572177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2174572177
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3430556032
Short name T492
Test name
Test status
Simulation time 32072491 ps
CPU time 0.69 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:50 PM PDT 24
Peak memory 206116 kb
Host smart-68e530db-38ec-459e-b5c8-3b62ff5b662e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430556032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3430556032
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1028559305
Short name T433
Test name
Test status
Simulation time 655911744 ps
CPU time 6.8 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:57 PM PDT 24
Peak memory 225336 kb
Host smart-f4dff869-4c27-475d-b6d1-9d92a3c289cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028559305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1028559305
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.432185792
Short name T554
Test name
Test status
Simulation time 94885527 ps
CPU time 0.75 seconds
Started Aug 18 04:57:41 PM PDT 24
Finished Aug 18 04:57:42 PM PDT 24
Peak memory 207432 kb
Host smart-32843684-278d-4887-a8c4-a1d6570aec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432185792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.432185792
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4257208190
Short name T440
Test name
Test status
Simulation time 9186724715 ps
CPU time 70.33 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:58:59 PM PDT 24
Peak memory 238268 kb
Host smart-1e68d411-565f-4b04-8741-04def1670afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257208190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4257208190
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.40288864
Short name T961
Test name
Test status
Simulation time 264882527024 ps
CPU time 118.8 seconds
Started Aug 18 04:57:51 PM PDT 24
Finished Aug 18 04:59:50 PM PDT 24
Peak memory 240664 kb
Host smart-1e0f30d9-cde8-4145-8d62-7b8395b488c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40288864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.40288864
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4182134777
Short name T233
Test name
Test status
Simulation time 40718191341 ps
CPU time 113.73 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:59:44 PM PDT 24
Peak memory 250428 kb
Host smart-e309a9e4-bc26-459b-896b-a4d3ad8da0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182134777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4182134777
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.859501278
Short name T349
Test name
Test status
Simulation time 1084204239 ps
CPU time 9.12 seconds
Started Aug 18 04:57:56 PM PDT 24
Finished Aug 18 04:58:05 PM PDT 24
Peak memory 225184 kb
Host smart-84ea89e3-4326-40a3-b8fd-a32db3328f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859501278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.859501278
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2882318513
Short name T292
Test name
Test status
Simulation time 10008358763 ps
CPU time 68.71 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:58:58 PM PDT 24
Peak memory 255804 kb
Host smart-221c950d-6157-4a12-8be9-3fc77ab1d039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882318513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2882318513
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4271239339
Short name T777
Test name
Test status
Simulation time 354127270 ps
CPU time 5.68 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:57:55 PM PDT 24
Peak memory 233540 kb
Host smart-024a5899-e341-474e-ba35-cfcc8771d26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271239339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4271239339
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.241038699
Short name T874
Test name
Test status
Simulation time 23088935957 ps
CPU time 57.21 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:58:47 PM PDT 24
Peak memory 238776 kb
Host smart-ed61c241-d15e-4be4-9481-48e651eeec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241038699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.241038699
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2946501975
Short name T856
Test name
Test status
Simulation time 84788046 ps
CPU time 2.68 seconds
Started Aug 18 04:57:51 PM PDT 24
Finished Aug 18 04:57:53 PM PDT 24
Peak memory 233596 kb
Host smart-b4389c92-623b-4df4-b01b-716178260b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946501975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2946501975
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3743518446
Short name T560
Test name
Test status
Simulation time 21301367348 ps
CPU time 11.07 seconds
Started Aug 18 04:57:56 PM PDT 24
Finished Aug 18 04:58:07 PM PDT 24
Peak memory 233572 kb
Host smart-92fd076d-71fa-44fc-a7e0-eac7d400d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743518446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3743518446
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4074861758
Short name T602
Test name
Test status
Simulation time 488817076 ps
CPU time 8.07 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:57:57 PM PDT 24
Peak memory 221196 kb
Host smart-73ee1598-cbd5-4633-bb96-f10bb989d34a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4074861758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4074861758
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2647884715
Short name T235
Test name
Test status
Simulation time 33360812148 ps
CPU time 338.97 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 05:03:29 PM PDT 24
Peak memory 266476 kb
Host smart-645e450f-db4e-45c7-8746-b89d987cbc6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647884715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2647884715
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1834914304
Short name T460
Test name
Test status
Simulation time 1420831159 ps
CPU time 15.01 seconds
Started Aug 18 04:57:42 PM PDT 24
Finished Aug 18 04:57:58 PM PDT 24
Peak memory 217268 kb
Host smart-1d85b306-a475-482c-a33a-621f2d5acec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834914304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1834914304
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1102143408
Short name T944
Test name
Test status
Simulation time 694856877 ps
CPU time 4.54 seconds
Started Aug 18 04:57:40 PM PDT 24
Finished Aug 18 04:57:45 PM PDT 24
Peak memory 217144 kb
Host smart-eb0dbe8d-8587-4b41-ae3d-83860dfd65b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102143408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1102143408
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.362923287
Short name T644
Test name
Test status
Simulation time 92727384 ps
CPU time 1.85 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:52 PM PDT 24
Peak memory 217044 kb
Host smart-986ddb37-fe9f-4164-9cd6-4a061350dd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362923287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.362923287
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4076285053
Short name T338
Test name
Test status
Simulation time 27023249 ps
CPU time 0.77 seconds
Started Aug 18 04:57:57 PM PDT 24
Finished Aug 18 04:57:58 PM PDT 24
Peak memory 206808 kb
Host smart-827067a1-287b-48bd-991f-3a3ae9371b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076285053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4076285053
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.519805719
Short name T844
Test name
Test status
Simulation time 950269319 ps
CPU time 7.76 seconds
Started Aug 18 04:57:48 PM PDT 24
Finished Aug 18 04:57:56 PM PDT 24
Peak memory 225304 kb
Host smart-1afd16a4-bf1d-40f4-ac1c-a3aea2063b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519805719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.519805719
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3471789379
Short name T77
Test name
Test status
Simulation time 42443410 ps
CPU time 0.74 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:57:58 PM PDT 24
Peak memory 206200 kb
Host smart-fbf1a565-a944-415c-8e9f-6dd5b986394c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471789379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3471789379
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2063055115
Short name T1007
Test name
Test status
Simulation time 59294294 ps
CPU time 2.22 seconds
Started Aug 18 04:57:52 PM PDT 24
Finished Aug 18 04:57:54 PM PDT 24
Peak memory 225396 kb
Host smart-d6b4ff87-43ac-4fa7-ba4b-46cc52acad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063055115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2063055115
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2076116948
Short name T912
Test name
Test status
Simulation time 19472857 ps
CPU time 0.73 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:57:49 PM PDT 24
Peak memory 207320 kb
Host smart-a3cd8c72-596d-4dfd-a0c7-a3160653b18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076116948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2076116948
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.808050519
Short name T599
Test name
Test status
Simulation time 68437669769 ps
CPU time 210.6 seconds
Started Aug 18 04:58:02 PM PDT 24
Finished Aug 18 05:01:33 PM PDT 24
Peak memory 258304 kb
Host smart-4b97c84e-4215-40e6-a388-c420022af692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808050519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.808050519
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2065053507
Short name T671
Test name
Test status
Simulation time 12929627580 ps
CPU time 51.84 seconds
Started Aug 18 04:57:58 PM PDT 24
Finished Aug 18 04:58:50 PM PDT 24
Peak memory 249944 kb
Host smart-7e5a045a-b76d-48da-b101-b0f80572f8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065053507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2065053507
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1281139272
Short name T551
Test name
Test status
Simulation time 660322093 ps
CPU time 4.31 seconds
Started Aug 18 04:57:52 PM PDT 24
Finished Aug 18 04:57:56 PM PDT 24
Peak memory 225308 kb
Host smart-99e0771e-781e-46ef-908b-9d57766abaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281139272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1281139272
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1518812651
Short name T582
Test name
Test status
Simulation time 330811239 ps
CPU time 6.18 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:57:55 PM PDT 24
Peak memory 235764 kb
Host smart-7452a9d1-b529-4e0d-aea1-d43c321bf49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518812651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1518812651
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.927563678
Short name T945
Test name
Test status
Simulation time 1332158807 ps
CPU time 13.93 seconds
Started Aug 18 04:57:51 PM PDT 24
Finished Aug 18 04:58:05 PM PDT 24
Peak memory 221672 kb
Host smart-fb84b5c7-5a33-4264-b480-12d83d0aab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927563678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.927563678
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.291760394
Short name T983
Test name
Test status
Simulation time 8028707176 ps
CPU time 68.89 seconds
Started Aug 18 04:57:56 PM PDT 24
Finished Aug 18 04:59:05 PM PDT 24
Peak memory 233596 kb
Host smart-75966b8a-8d89-4e85-943f-568026a0cd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291760394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.291760394
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.11155327
Short name T379
Test name
Test status
Simulation time 2659331389 ps
CPU time 4.66 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:55 PM PDT 24
Peak memory 225348 kb
Host smart-69601cb5-82ca-4d7c-81d3-7a4244835d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11155327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.11155327
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1157189487
Short name T950
Test name
Test status
Simulation time 5470332905 ps
CPU time 16.42 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:58:06 PM PDT 24
Peak memory 225396 kb
Host smart-005557df-c091-4272-9635-f3cd66f2a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157189487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1157189487
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3081408186
Short name T144
Test name
Test status
Simulation time 1337193273 ps
CPU time 4.85 seconds
Started Aug 18 04:57:51 PM PDT 24
Finished Aug 18 04:57:56 PM PDT 24
Peak memory 219420 kb
Host smart-4e269bff-85a1-44bf-9c94-182db24efca9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3081408186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3081408186
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1978718059
Short name T18
Test name
Test status
Simulation time 168974120149 ps
CPU time 335.98 seconds
Started Aug 18 04:58:01 PM PDT 24
Finished Aug 18 05:03:37 PM PDT 24
Peak memory 274664 kb
Host smart-dbdd97bb-386d-4aa3-983e-2ed4f3dcd02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978718059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1978718059
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3728264128
Short name T700
Test name
Test status
Simulation time 3631789492 ps
CPU time 17.99 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:58:07 PM PDT 24
Peak memory 217416 kb
Host smart-711d5e53-a16f-4211-80ee-dd103bf7eef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728264128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3728264128
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2130880277
Short name T472
Test name
Test status
Simulation time 350967557 ps
CPU time 1.65 seconds
Started Aug 18 04:57:48 PM PDT 24
Finished Aug 18 04:57:50 PM PDT 24
Peak memory 208688 kb
Host smart-7fa3a24e-4839-4b19-97eb-742b16bf8e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130880277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2130880277
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1745921403
Short name T323
Test name
Test status
Simulation time 48636019 ps
CPU time 1.1 seconds
Started Aug 18 04:57:50 PM PDT 24
Finished Aug 18 04:57:51 PM PDT 24
Peak memory 217092 kb
Host smart-ebdf6d36-30fe-49c1-aba4-681bbeb13ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745921403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1745921403
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4232359176
Short name T959
Test name
Test status
Simulation time 75619606 ps
CPU time 0.75 seconds
Started Aug 18 04:57:56 PM PDT 24
Finished Aug 18 04:57:57 PM PDT 24
Peak memory 206684 kb
Host smart-eb89b51d-151a-4ccf-879b-94d755ec447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232359176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4232359176
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2601907540
Short name T690
Test name
Test status
Simulation time 338630314 ps
CPU time 4.26 seconds
Started Aug 18 04:57:49 PM PDT 24
Finished Aug 18 04:57:54 PM PDT 24
Peak memory 241624 kb
Host smart-ef676be5-2e03-46ea-81d0-9fabe7473cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601907540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2601907540
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1278989865
Short name T537
Test name
Test status
Simulation time 25167476 ps
CPU time 0.75 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:53:55 PM PDT 24
Peak memory 206304 kb
Host smart-0600ed86-1cdb-44b8-802e-56a1f7f46537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278989865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
278989865
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3880236764
Short name T854
Test name
Test status
Simulation time 1069290160 ps
CPU time 5.7 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:54:01 PM PDT 24
Peak memory 225292 kb
Host smart-2302a3fc-31cd-4729-ac2e-afebe106b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880236764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3880236764
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.271453718
Short name T913
Test name
Test status
Simulation time 39607084 ps
CPU time 0.81 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:53:57 PM PDT 24
Peak memory 207748 kb
Host smart-2cd7f490-eb12-485e-9a59-de50dc749e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271453718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.271453718
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3042930472
Short name T738
Test name
Test status
Simulation time 75207496305 ps
CPU time 65.68 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:54:59 PM PDT 24
Peak memory 241820 kb
Host smart-cea2e7b5-637f-47fa-b7c5-68a7e1839e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042930472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3042930472
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2871328487
Short name T312
Test name
Test status
Simulation time 22606314633 ps
CPU time 220.71 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:57:36 PM PDT 24
Peak memory 242008 kb
Host smart-a006d13b-73b3-42e2-a007-5e5c24d4b1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871328487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2871328487
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4095509013
Short name T208
Test name
Test status
Simulation time 153125284924 ps
CPU time 229.62 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:57:42 PM PDT 24
Peak memory 252036 kb
Host smart-acf0f680-7a35-4111-af72-c73b5f9c275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095509013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4095509013
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.486865541
Short name T179
Test name
Test status
Simulation time 110315759768 ps
CPU time 113.74 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:55:49 PM PDT 24
Peak memory 250076 kb
Host smart-94863387-79e9-4ba5-a37b-674bd19205c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486865541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
486865541
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.884372073
Short name T203
Test name
Test status
Simulation time 1734005614 ps
CPU time 7.11 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:54:02 PM PDT 24
Peak memory 233468 kb
Host smart-d7469c03-d47d-4a0a-93d5-55f302bb60f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884372073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.884372073
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3844946041
Short name T685
Test name
Test status
Simulation time 34585271642 ps
CPU time 29.13 seconds
Started Aug 18 04:53:57 PM PDT 24
Finished Aug 18 04:54:27 PM PDT 24
Peak memory 225444 kb
Host smart-d5966897-eb5a-42dc-b008-e18ac5f9c7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844946041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3844946041
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2602866074
Short name T511
Test name
Test status
Simulation time 15575824301 ps
CPU time 12.96 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:54:08 PM PDT 24
Peak memory 225340 kb
Host smart-17f2978f-4dac-4425-9524-bc9b0244ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602866074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2602866074
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4177908130
Short name T534
Test name
Test status
Simulation time 1600263873 ps
CPU time 3.24 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:53:55 PM PDT 24
Peak memory 225332 kb
Host smart-e322a8d9-2289-4b32-acec-729a17890892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177908130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4177908130
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2760706569
Short name T795
Test name
Test status
Simulation time 1661216269 ps
CPU time 16.55 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:54:13 PM PDT 24
Peak memory 224076 kb
Host smart-aa251b85-6fa3-4dcf-9db0-85899495f770
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760706569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2760706569
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3951411784
Short name T621
Test name
Test status
Simulation time 6493920389 ps
CPU time 25.07 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:54:20 PM PDT 24
Peak memory 217256 kb
Host smart-7c2fbd00-1604-4aec-8bdd-bcb2e6a4058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951411784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3951411784
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3957156621
Short name T400
Test name
Test status
Simulation time 1568744920 ps
CPU time 5.09 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:53:57 PM PDT 24
Peak memory 217212 kb
Host smart-cc639f94-5b2b-4374-bebd-c13927bfd361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957156621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3957156621
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3766876580
Short name T360
Test name
Test status
Simulation time 177539985 ps
CPU time 2.2 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:53:55 PM PDT 24
Peak memory 217240 kb
Host smart-881b45dc-e89c-4552-8178-c644b5431932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766876580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3766876580
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3513168083
Short name T516
Test name
Test status
Simulation time 55427464 ps
CPU time 0.71 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:53:57 PM PDT 24
Peak memory 206884 kb
Host smart-eda461f8-458a-4383-8697-b66252e48a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513168083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3513168083
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3209402926
Short name T620
Test name
Test status
Simulation time 3836933401 ps
CPU time 13.13 seconds
Started Aug 18 04:53:52 PM PDT 24
Finished Aug 18 04:54:05 PM PDT 24
Peak memory 225340 kb
Host smart-b383fac6-137a-4419-8a12-14529393193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209402926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3209402926
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1436242310
Short name T629
Test name
Test status
Simulation time 13543153 ps
CPU time 0.71 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:06 PM PDT 24
Peak memory 205696 kb
Host smart-279d1f24-00d5-4481-9da7-3771572b23c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436242310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
436242310
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2953762818
Short name T652
Test name
Test status
Simulation time 2411341208 ps
CPU time 3.59 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:09 PM PDT 24
Peak memory 225472 kb
Host smart-055545b4-8a40-40da-914f-208a140bfd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953762818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2953762818
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2927398417
Short name T352
Test name
Test status
Simulation time 24588845 ps
CPU time 0.8 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:53:55 PM PDT 24
Peak memory 207508 kb
Host smart-4ac07dd1-261b-4ce4-abbb-acc1877ccb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927398417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2927398417
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1095923180
Short name T1005
Test name
Test status
Simulation time 1609868390 ps
CPU time 28.73 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:35 PM PDT 24
Peak memory 249984 kb
Host smart-cbfecb2d-ffd0-4ac6-826f-2755cb19d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095923180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1095923180
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1241993298
Short name T62
Test name
Test status
Simulation time 64325138928 ps
CPU time 255.6 seconds
Started Aug 18 04:54:03 PM PDT 24
Finished Aug 18 04:58:19 PM PDT 24
Peak memory 257520 kb
Host smart-563fbe27-5e43-4dbc-93cd-339ec1333422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241993298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1241993298
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2516104703
Short name T210
Test name
Test status
Simulation time 35762050406 ps
CPU time 166.71 seconds
Started Aug 18 04:54:07 PM PDT 24
Finished Aug 18 04:56:54 PM PDT 24
Peak memory 265212 kb
Host smart-1b8761e2-2998-4d44-9a2b-4d4ec25e5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516104703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2516104703
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2266690543
Short name T818
Test name
Test status
Simulation time 3711582492 ps
CPU time 48.04 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:54 PM PDT 24
Peak memory 250680 kb
Host smart-92e14961-8703-465b-ba1c-0d2e1a11a241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266690543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2266690543
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4023767983
Short name T892
Test name
Test status
Simulation time 16334007681 ps
CPU time 110.95 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:55:55 PM PDT 24
Peak memory 249980 kb
Host smart-64bf52ab-9909-4540-8074-1eec2a765068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023767983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4023767983
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3079122534
Short name T566
Test name
Test status
Simulation time 83761694 ps
CPU time 3.2 seconds
Started Aug 18 04:54:07 PM PDT 24
Finished Aug 18 04:54:10 PM PDT 24
Peak memory 233776 kb
Host smart-dd171f6a-5be5-4712-9c14-ef0e8f7469db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079122534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3079122534
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2224415370
Short name T917
Test name
Test status
Simulation time 5797683712 ps
CPU time 18.72 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:24 PM PDT 24
Peak memory 241652 kb
Host smart-5c930a5f-2f6f-448d-97c0-c456ac4c5709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224415370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2224415370
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.686637253
Short name T425
Test name
Test status
Simulation time 12172889170 ps
CPU time 18.53 seconds
Started Aug 18 04:53:56 PM PDT 24
Finished Aug 18 04:54:15 PM PDT 24
Peak memory 233672 kb
Host smart-38fd8c9c-e6af-4490-9705-97195536bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686637253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
686637253
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1163638986
Short name T430
Test name
Test status
Simulation time 3092431307 ps
CPU time 6.77 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:54:00 PM PDT 24
Peak memory 233716 kb
Host smart-cbaebe8b-4a66-48ee-9dcd-68a4d041c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163638986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1163638986
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.749199864
Short name T907
Test name
Test status
Simulation time 1115630974 ps
CPU time 13.93 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 221056 kb
Host smart-095b592a-985a-4d99-a124-42d8cda50142
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749199864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.749199864
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3904420037
Short name T701
Test name
Test status
Simulation time 242065675 ps
CPU time 1.06 seconds
Started Aug 18 04:54:10 PM PDT 24
Finished Aug 18 04:54:11 PM PDT 24
Peak memory 216656 kb
Host smart-92e4821f-15e3-4017-88c9-cf9a31e6f7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904420037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3904420037
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.415683391
Short name T718
Test name
Test status
Simulation time 1069356803 ps
CPU time 3.67 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:53:58 PM PDT 24
Peak memory 217116 kb
Host smart-31597715-bcc1-44b1-97f0-8b899a1a40ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415683391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.415683391
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.642349019
Short name T698
Test name
Test status
Simulation time 20763443547 ps
CPU time 12.2 seconds
Started Aug 18 04:53:54 PM PDT 24
Finished Aug 18 04:54:07 PM PDT 24
Peak memory 217236 kb
Host smart-9e288af8-b28f-48ca-a501-6d95db7ab66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642349019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.642349019
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1803125547
Short name T789
Test name
Test status
Simulation time 41484386 ps
CPU time 0.99 seconds
Started Aug 18 04:53:55 PM PDT 24
Finished Aug 18 04:53:56 PM PDT 24
Peak memory 207812 kb
Host smart-f6cfa254-1c34-4725-b0a3-4c256ac79d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803125547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1803125547
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2096012062
Short name T32
Test name
Test status
Simulation time 78667207 ps
CPU time 1.01 seconds
Started Aug 18 04:53:53 PM PDT 24
Finished Aug 18 04:53:54 PM PDT 24
Peak memory 207732 kb
Host smart-c2ac7027-e0ba-4c69-9b6f-2a6a49ed4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096012062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2096012062
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2665338345
Short name T611
Test name
Test status
Simulation time 502826598 ps
CPU time 4.63 seconds
Started Aug 18 04:54:07 PM PDT 24
Finished Aug 18 04:54:11 PM PDT 24
Peak memory 225408 kb
Host smart-aab515c3-f76d-4724-bd7f-d51aa7a25187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665338345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2665338345
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3023819323
Short name T955
Test name
Test status
Simulation time 52172850 ps
CPU time 0.71 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:07 PM PDT 24
Peak memory 206292 kb
Host smart-72b06ef0-587d-48c4-8a61-ee0992c26df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023819323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
023819323
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3942925915
Short name T890
Test name
Test status
Simulation time 1556312647 ps
CPU time 10.54 seconds
Started Aug 18 04:54:10 PM PDT 24
Finished Aug 18 04:54:21 PM PDT 24
Peak memory 233516 kb
Host smart-9303c27e-9b90-4de8-9cde-7ca2caec8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942925915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3942925915
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.302036034
Short name T953
Test name
Test status
Simulation time 28480436 ps
CPU time 0.79 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:05 PM PDT 24
Peak memory 207760 kb
Host smart-15ae5f82-50c8-44f8-8fc0-6c5fd86c6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302036034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.302036034
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3901814841
Short name T605
Test name
Test status
Simulation time 58404112098 ps
CPU time 117.98 seconds
Started Aug 18 04:54:12 PM PDT 24
Finished Aug 18 04:56:10 PM PDT 24
Peak memory 250204 kb
Host smart-d2810315-9476-49e2-b994-3b429bc657df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901814841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3901814841
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1162412994
Short name T236
Test name
Test status
Simulation time 20332586012 ps
CPU time 192.39 seconds
Started Aug 18 04:54:12 PM PDT 24
Finished Aug 18 04:57:24 PM PDT 24
Peak memory 257728 kb
Host smart-371ec49a-d321-4f3d-b5ba-a0ccecc21b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162412994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1162412994
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.432619439
Short name T873
Test name
Test status
Simulation time 2551152755 ps
CPU time 11.61 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:17 PM PDT 24
Peak memory 241900 kb
Host smart-a196bd5e-c8d7-4415-8cf8-c315f31c33de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432619439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.432619439
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3660950507
Short name T658
Test name
Test status
Simulation time 67603821559 ps
CPU time 52.89 seconds
Started Aug 18 04:54:12 PM PDT 24
Finished Aug 18 04:55:05 PM PDT 24
Peak memory 250512 kb
Host smart-8b1f86cf-c115-4223-9de6-66e16c1f792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660950507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3660950507
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4131856663
Short name T908
Test name
Test status
Simulation time 1091290215 ps
CPU time 10.97 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:16 PM PDT 24
Peak memory 225232 kb
Host smart-f04bd75b-3410-49ae-b028-149259276e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131856663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4131856663
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.81270145
Short name T225
Test name
Test status
Simulation time 9201864789 ps
CPU time 42.59 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:48 PM PDT 24
Peak memory 225500 kb
Host smart-a10db298-3721-4a31-8fa1-3abf866d374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81270145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.81270145
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3482985608
Short name T759
Test name
Test status
Simulation time 3099423724 ps
CPU time 10.47 seconds
Started Aug 18 04:54:07 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 225504 kb
Host smart-4944b9c0-9926-45b9-acbe-df01e397caf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482985608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3482985608
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1024587618
Short name T256
Test name
Test status
Simulation time 329100210 ps
CPU time 3.93 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:09 PM PDT 24
Peak memory 233440 kb
Host smart-d3e8aa73-82c6-4e00-bddd-b1daf4fbc084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024587618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1024587618
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2440668221
Short name T752
Test name
Test status
Simulation time 1277300484 ps
CPU time 5.77 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:10 PM PDT 24
Peak memory 222152 kb
Host smart-c8bf7e46-1fb5-482d-8ff5-fa41bbea4f8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2440668221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2440668221
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.173784790
Short name T36
Test name
Test status
Simulation time 28834159421 ps
CPU time 106.47 seconds
Started Aug 18 04:54:10 PM PDT 24
Finished Aug 18 04:55:57 PM PDT 24
Peak memory 250152 kb
Host smart-b87fa5d3-ef25-4496-8812-8b2c5a15ef1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173784790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.173784790
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3614729239
Short name T800
Test name
Test status
Simulation time 776717507 ps
CPU time 7.11 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:12 PM PDT 24
Peak memory 217236 kb
Host smart-46dd4751-d145-4e84-9828-728a99e79411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614729239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3614729239
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3855508875
Short name T388
Test name
Test status
Simulation time 2570813364 ps
CPU time 3.89 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:08 PM PDT 24
Peak memory 217164 kb
Host smart-69a5910e-0887-43eb-b486-06a53c4189c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855508875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3855508875
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.90915907
Short name T438
Test name
Test status
Simulation time 187804197 ps
CPU time 0.99 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:06 PM PDT 24
Peak memory 207828 kb
Host smart-d6f01e67-b505-4ddd-85e1-b0a44df5d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90915907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.90915907
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2762914212
Short name T467
Test name
Test status
Simulation time 188279472 ps
CPU time 1.03 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:05 PM PDT 24
Peak memory 207864 kb
Host smart-22a7d0c9-eddb-4120-9f69-61397d4604af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762914212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2762914212
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3869928155
Short name T278
Test name
Test status
Simulation time 4562602760 ps
CPU time 9.23 seconds
Started Aug 18 04:54:05 PM PDT 24
Finished Aug 18 04:54:14 PM PDT 24
Peak memory 233696 kb
Host smart-e0911b68-3f68-4caa-be07-f8896fdb968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869928155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3869928155
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2132848022
Short name T780
Test name
Test status
Simulation time 15225469 ps
CPU time 0.74 seconds
Started Aug 18 04:54:20 PM PDT 24
Finished Aug 18 04:54:21 PM PDT 24
Peak memory 205604 kb
Host smart-c4ad119c-3f07-4871-9710-7f8a1b322b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132848022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
132848022
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1280791982
Short name T67
Test name
Test status
Simulation time 56531330 ps
CPU time 2.76 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:54:22 PM PDT 24
Peak memory 233512 kb
Host smart-4345d462-4e3c-49e7-af56-8573dbd065c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280791982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1280791982
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1857362524
Short name T339
Test name
Test status
Simulation time 26489967 ps
CPU time 0.76 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:07 PM PDT 24
Peak memory 207680 kb
Host smart-3f3cae9b-ec26-42d4-b0af-1dfe72fb1e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857362524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1857362524
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2067120074
Short name T769
Test name
Test status
Simulation time 456644220 ps
CPU time 0.82 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 216864 kb
Host smart-20d82759-9dff-41e2-ae15-38c3034867a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067120074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2067120074
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3408302351
Short name T782
Test name
Test status
Simulation time 5928736253 ps
CPU time 15.43 seconds
Started Aug 18 04:54:16 PM PDT 24
Finished Aug 18 04:54:31 PM PDT 24
Peak memory 218812 kb
Host smart-8f7443e0-31b0-4718-97aa-e2c9462c49c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408302351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3408302351
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2231453775
Short name T771
Test name
Test status
Simulation time 122494402027 ps
CPU time 355.98 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 05:00:13 PM PDT 24
Peak memory 258172 kb
Host smart-4de89715-cc29-451c-8bc3-9e3470eecd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231453775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2231453775
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1720200451
Short name T310
Test name
Test status
Simulation time 2263077226 ps
CPU time 16.86 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:34 PM PDT 24
Peak memory 234632 kb
Host smart-dd28d87d-cb40-428b-9d18-9275d8040142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720200451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1720200451
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1492562294
Short name T165
Test name
Test status
Simulation time 771148884 ps
CPU time 17.89 seconds
Started Aug 18 04:54:16 PM PDT 24
Finished Aug 18 04:54:34 PM PDT 24
Peak memory 236872 kb
Host smart-77369c10-0acf-4fdb-b8ba-33dc6c468dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492562294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1492562294
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1084270835
Short name T228
Test name
Test status
Simulation time 2230114282 ps
CPU time 7.78 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:25 PM PDT 24
Peak memory 233724 kb
Host smart-3ee81287-ec32-4f55-a64b-f4ec73e6eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084270835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1084270835
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3292375660
Short name T563
Test name
Test status
Simulation time 1776776383 ps
CPU time 23.72 seconds
Started Aug 18 04:54:20 PM PDT 24
Finished Aug 18 04:54:44 PM PDT 24
Peak memory 239064 kb
Host smart-9885f7bd-d19b-4754-80b6-1ebdf9d82a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292375660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3292375660
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.923875045
Short name T267
Test name
Test status
Simulation time 1052871107 ps
CPU time 10.02 seconds
Started Aug 18 04:54:18 PM PDT 24
Finished Aug 18 04:54:28 PM PDT 24
Peak memory 241568 kb
Host smart-df955473-4200-4c54-868b-dd37505004ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923875045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
923875045
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.984701702
Short name T617
Test name
Test status
Simulation time 7167808389 ps
CPU time 12 seconds
Started Aug 18 04:54:16 PM PDT 24
Finished Aug 18 04:54:28 PM PDT 24
Peak memory 233568 kb
Host smart-29c3b1fc-b599-4577-937e-f98544d80de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984701702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.984701702
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4128344811
Short name T592
Test name
Test status
Simulation time 2132356581 ps
CPU time 8.02 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:25 PM PDT 24
Peak memory 219944 kb
Host smart-ae703b1d-8617-404a-b8c2-81d7ee65891c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4128344811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4128344811
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4102375801
Short name T607
Test name
Test status
Simulation time 57824419195 ps
CPU time 160.33 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:56:59 PM PDT 24
Peak memory 254588 kb
Host smart-faa21fc9-0fff-4291-ae2e-a9294665ff3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102375801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4102375801
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1001353258
Short name T315
Test name
Test status
Simulation time 8009161700 ps
CPU time 16.75 seconds
Started Aug 18 04:54:04 PM PDT 24
Finished Aug 18 04:54:21 PM PDT 24
Peak memory 217384 kb
Host smart-5fda48e4-fc86-4a94-aaaf-9d24fd36bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001353258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1001353258
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2878769790
Short name T377
Test name
Test status
Simulation time 2124974306 ps
CPU time 4.42 seconds
Started Aug 18 04:54:06 PM PDT 24
Finished Aug 18 04:54:11 PM PDT 24
Peak memory 217204 kb
Host smart-34976c20-7ba8-4f5d-8f21-926a1bce63d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878769790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2878769790
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3417086121
Short name T484
Test name
Test status
Simulation time 122339849 ps
CPU time 1.35 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:54:21 PM PDT 24
Peak memory 217116 kb
Host smart-02942d2d-8aec-4fa0-971b-9e2afe2233bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417086121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3417086121
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.281329299
Short name T2
Test name
Test status
Simulation time 49646281 ps
CPU time 0.84 seconds
Started Aug 18 04:54:16 PM PDT 24
Finished Aug 18 04:54:17 PM PDT 24
Peak memory 206840 kb
Host smart-163c7966-76cf-4eee-8d7a-6e5bb142612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281329299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.281329299
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4140281942
Short name T914
Test name
Test status
Simulation time 18445409476 ps
CPU time 14.75 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 225432 kb
Host smart-df025c1d-82f8-4fbf-b07f-ee7ce3d20cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140281942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4140281942
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4128839245
Short name T767
Test name
Test status
Simulation time 11967239 ps
CPU time 0.71 seconds
Started Aug 18 04:54:28 PM PDT 24
Finished Aug 18 04:54:29 PM PDT 24
Peak memory 205596 kb
Host smart-bb72e6a7-5549-41f7-b793-b3343b267f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128839245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
128839245
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4195834104
Short name T182
Test name
Test status
Simulation time 65354181 ps
CPU time 2.26 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:54:28 PM PDT 24
Peak memory 225236 kb
Host smart-d2b95ec4-781b-4329-820b-f83498d20b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195834104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4195834104
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1359611255
Short name T459
Test name
Test status
Simulation time 14913331 ps
CPU time 0.84 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 206332 kb
Host smart-95ed3616-e5fb-48e2-8cb7-35c655a66923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359611255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1359611255
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2563438729
Short name T651
Test name
Test status
Simulation time 54630622633 ps
CPU time 98.06 seconds
Started Aug 18 04:54:26 PM PDT 24
Finished Aug 18 04:56:04 PM PDT 24
Peak memory 257040 kb
Host smart-72710949-d6b9-4169-9bf8-d59c058e6798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563438729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2563438729
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2950699455
Short name T931
Test name
Test status
Simulation time 203677858181 ps
CPU time 388.31 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 05:00:53 PM PDT 24
Peak memory 250584 kb
Host smart-0e798eaf-98d3-455f-8e5b-cded105191d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950699455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2950699455
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3237397710
Short name T936
Test name
Test status
Simulation time 613648369 ps
CPU time 12.96 seconds
Started Aug 18 04:54:33 PM PDT 24
Finished Aug 18 04:54:46 PM PDT 24
Peak memory 239576 kb
Host smart-4533bf8e-5417-4a2e-8502-0730eb716a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237397710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3237397710
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2938919708
Short name T198
Test name
Test status
Simulation time 197698445363 ps
CPU time 310.46 seconds
Started Aug 18 04:54:32 PM PDT 24
Finished Aug 18 04:59:43 PM PDT 24
Peak memory 267524 kb
Host smart-3b0174a8-df91-4b4f-8dc9-72ec012fc6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938919708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2938919708
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2919575146
Short name T491
Test name
Test status
Simulation time 3149437059 ps
CPU time 6.85 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:24 PM PDT 24
Peak memory 219788 kb
Host smart-4853fd35-0ccb-4767-8089-7052c8611cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919575146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2919575146
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.818133037
Short name T215
Test name
Test status
Simulation time 22294104983 ps
CPU time 129.26 seconds
Started Aug 18 04:54:15 PM PDT 24
Finished Aug 18 04:56:25 PM PDT 24
Peak memory 237508 kb
Host smart-ea10d376-6882-45a9-a7c9-8256f4c04c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818133037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.818133037
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2147998261
Short name T284
Test name
Test status
Simulation time 4744741776 ps
CPU time 16.16 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 234900 kb
Host smart-e95575ed-1550-4003-862b-8a6b565c27b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147998261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2147998261
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1201023030
Short name T405
Test name
Test status
Simulation time 3065542213 ps
CPU time 3.95 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:54:23 PM PDT 24
Peak memory 225348 kb
Host smart-7c996684-abf2-43a5-b8cf-fe2bf31c557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201023030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1201023030
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3038164685
Short name T751
Test name
Test status
Simulation time 172146099 ps
CPU time 4.11 seconds
Started Aug 18 04:54:33 PM PDT 24
Finished Aug 18 04:54:37 PM PDT 24
Peak memory 223944 kb
Host smart-1b61c08a-90a4-41a4-aba1-26c61d31de9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3038164685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3038164685
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.913266270
Short name T947
Test name
Test status
Simulation time 47757224 ps
CPU time 1.05 seconds
Started Aug 18 04:54:25 PM PDT 24
Finished Aug 18 04:54:26 PM PDT 24
Peak memory 207804 kb
Host smart-6246c8f4-77bc-42c0-aad4-bd4af207b804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913266270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.913266270
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4034955338
Short name T475
Test name
Test status
Simulation time 26490049100 ps
CPU time 17.18 seconds
Started Aug 18 04:54:15 PM PDT 24
Finished Aug 18 04:54:33 PM PDT 24
Peak memory 217200 kb
Host smart-25ffa402-7bda-465b-825f-db126e54ef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034955338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4034955338
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2520208417
Short name T136
Test name
Test status
Simulation time 5638937049 ps
CPU time 6.63 seconds
Started Aug 18 04:54:18 PM PDT 24
Finished Aug 18 04:54:25 PM PDT 24
Peak memory 217172 kb
Host smart-e99d9cc1-d225-494e-bff4-166859668f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520208417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2520208417
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3951495212
Short name T321
Test name
Test status
Simulation time 37584146 ps
CPU time 1.16 seconds
Started Aug 18 04:54:15 PM PDT 24
Finished Aug 18 04:54:17 PM PDT 24
Peak memory 207952 kb
Host smart-7ef613c0-13b5-4067-8709-df9bbefe7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951495212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3951495212
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3377796643
Short name T558
Test name
Test status
Simulation time 17265233 ps
CPU time 0.71 seconds
Started Aug 18 04:54:17 PM PDT 24
Finished Aug 18 04:54:18 PM PDT 24
Peak memory 206336 kb
Host smart-20572302-7a40-45c0-8a06-c2b470ebd233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377796643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3377796643
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2963126705
Short name T386
Test name
Test status
Simulation time 7609979677 ps
CPU time 30.28 seconds
Started Aug 18 04:54:19 PM PDT 24
Finished Aug 18 04:54:50 PM PDT 24
Peak memory 240388 kb
Host smart-9184ee4e-3332-46d5-b0b1-8fe9d1b70340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963126705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2963126705
Directory /workspace/9.spi_device_upload/latest
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