Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2927997	1			T2	144		T3	1		T4	1677
all_values[1]	2927997	1			T2	144		T3	1		T4	1677
all_values[2]	2927997	1			T2	144		T3	1		T4	1677
all_values[3]	2927997	1			T2	144		T3	1		T4	1677
all_values[4]	2927997	1			T2	144		T3	1		T4	1677
all_values[5]	2927997	1			T2	144		T3	1		T4	1677
all_values[6]	2927997	1			T2	144		T3	1		T4	1677
all_values[7]	2927997	1			T2	144		T3	1		T4	1677

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22367193

1

T2

1152

T3

8

T4

13416

auto[1]

1056783

1

T6

80

T16

30

T17

23584

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23396878

1

T2

1152

T3

8

T4

13416

auto[1]

27098

1

T6

69

T15

401

T16

801

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2855371	1			T2	144		T3	1		T4	1677
all_values[0]	auto[0]	auto[1]	12901	1			T6	5		T15	235		T16	401
all_values[0]	auto[1]	auto[0]	59274	1			T6	4		T16	5		T17	3285
all_values[0]	auto[1]	auto[1]	451	1			T6	8		T17	85		T20	2
all_values[1]	auto[0]	auto[0]	2794593	1			T2	144		T3	1		T4	1677
all_values[1]	auto[0]	auto[1]	7978	1			T6	5		T15	111		T16	316
all_values[1]	auto[1]	auto[0]	124840	1			T6	6		T16	4		T17	3312
all_values[1]	auto[1]	auto[1]	586	1			T6	5		T17	58		T19	6
all_values[2]	auto[0]	auto[0]	2752442	1			T2	144		T3	1		T4	1677
all_values[2]	auto[0]	auto[1]	2874	1			T6	2		T15	55		T16	77
all_values[2]	auto[1]	auto[0]	172325	1			T6	3		T16	5		T17	3345
all_values[2]	auto[1]	auto[1]	356	1			T6	7		T17	24		T19	2
all_values[3]	auto[0]	auto[0]	2831433	1			T2	144		T3	1		T4	1677
all_values[3]	auto[0]	auto[1]	213	1			T6	7		T17	1		T91	4
all_values[3]	auto[1]	auto[0]	96144	1			T6	4		T16	5		T17	3366
all_values[3]	auto[1]	auto[1]	207	1			T6	4		T17	3		T19	4
all_values[4]	auto[0]	auto[0]	2796111	1			T2	144		T3	1		T4	1677
all_values[4]	auto[0]	auto[1]	213	1			T6	2		T19	2		T21	7
all_values[4]	auto[1]	auto[0]	131475	1			T6	1		T16	2		T17	3369
all_values[4]	auto[1]	auto[1]	198	1			T6	5		T16	2		T19	4
all_values[5]	auto[0]	auto[0]	2717632	1			T2	144		T3	1		T4	1677
all_values[5]	auto[0]	auto[1]	201	1			T16	2		T17	2		T19	5
all_values[5]	auto[1]	auto[0]	209987	1			T6	11		T19	11790		T20	7
all_values[5]	auto[1]	auto[1]	177	1			T6	5		T16	1		T19	2
all_values[6]	auto[0]	auto[0]	2807000	1			T2	144		T3	1		T4	1677
all_values[6]	auto[0]	auto[1]	194	1			T6	1		T17	1		T19	1
all_values[6]	auto[1]	auto[0]	120624	1			T6	6		T16	6		T17	3368
all_values[6]	auto[1]	auto[1]	179	1			T6	4		T19	2		T21	5
all_values[7]	auto[0]	auto[0]	2787865	1			T2	144		T3	1		T4	1677
all_values[7]	auto[0]	auto[1]	172	1			T6	6		T16	2		T17	1
all_values[7]	auto[1]	auto[0]	139762	1			T6	4		T17	3368		T19	3
all_values[7]	auto[1]	auto[1]	198	1			T6	3		T17	1		T19	7