Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33298	1			T3	2		T9	16		T11	165
auto[SpiFlashAddrCfg]	7998	1			T3	2		T9	9		T11	31
auto[SpiFlashAddr3b]	9415	1			T3	8		T9	5		T11	25
auto[SpiFlashAddr4b]	7951	1			T3	2		T9	10		T11	38

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33679

1

T3

14

T9

23

T11

118

auto[1]

24983

1

T9

17

T11

141

T12

64

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30840

1

T3

4

T9

27

T11

163

auto[1]

27822

1

T3

10

T9

13

T11

96

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38015	1			T3	2		T9	14		T11	190
values[1]	1189	1			T9	5		T11	3		T12	1
values[2]	1569	1			T9	1		T11	2		T12	2
values[3]	1510	1			T9	4		T11	3		T12	8
values[4]	1479	1			T3	2		T9	5		T11	4
values[5]	1535	1			T9	3		T11	5		T12	4
values[6]	1556	1			T9	2		T11	5		T12	8
values[7]	1432	1			T9	2		T11	6		T12	8
values[8]	10377	1			T3	10		T9	4		T11	41

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36887

1

T3

14

T13

160

T14

2

auto[1]

21775

1

T9

40

T11

259

T12

160

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55417

1

T3

14

T9

40

T11

238

write

3245

1

T11

21

T12

11

T13

5

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19936

1

T3

10

T9

22

T11

67

valids[0x1]

38726

1

T3

4

T9

18

T11

192

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1660	1			T9	1		T11	6		T12	7
internal_process_ops[0x5a]	1609	1			T9	1		T11	8		T12	9
internal_process_ops[0x05]	18866	1			T3	2		T11	108		T12	3
internal_process_ops[0x35]	1700	1			T9	4		T11	11		T12	2
internal_process_ops[0x15]	1624	1			T11	2		T12	5		T13	6
internal_process_ops[0x03]	1201	1			T9	1		T11	1		T13	4
internal_process_ops[0x0b]	1107	1			T11	3		T13	7		T15	6
internal_process_ops[0x3b]	1223	1			T3	2		T9	1		T12	1
internal_process_ops[0x6b]	1152	1			T9	1		T11	2		T13	3
internal_process_ops[0xbb]	1169	1			T11	1		T13	5		T15	6
internal_process_ops[0xeb]	1134	1			T9	1		T11	3		T12	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57107

1

T3

14

T9

40

T11

250

auto[1]

1555

1

T11

9

T12

8

T13

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56238

1

T3

14

T9

40

T11

246

auto[1]

2424

1

T11

13

T12

13

T13

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12432

1

T3

2

T13

35

T14

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7841

1

T13

21

T15

71

T16

32

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2447

1

T3

2

T13

15

T15

31

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2158

1

T13

18

T15

26

T16

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2934

1

T3

8

T13

18

T15

31

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2550

1

T13

15

T15

26

T16

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2478

1

T3

2

T13

20

T15

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2169

1

T13

13

T15

18

T16

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

152

1

T15

2

T16

2

T17

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T16

4

T17

1

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

119

1

T16

3

T34

1

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T15

4

T16

1

T17

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

135

1

T13

1

T15

1

T34

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

117

1

T16

2

T17

2

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

121

1

T13

3

T16

1

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T15

2

T17

4

T37

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

140

1

T15

2

T16

1

T17

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

125

1

T13

1

T16

1

T17

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

95

1

T15

2

T17

2

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

125

1

T15

2

T17

3

T35

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

115

1

T15

1

T34

3

T35

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

124

1

T16

4

T17

2

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T16

1

T34

1

T35

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

109

1

T15

2

T16

1

T17

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7548

1

T9

12

T11

65

T12

40

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4674

1

T9

4

T11

98

T12

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1314

1

T9

2

T11

14

T12

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1233

1

T9

7

T11

7

T12

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1598

1

T9

4

T11

14

T12

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1513

1

T9

1

T11

9

T12

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1283

1

T9

5

T11

14

T12

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1245

1

T9

5

T11

17

T12

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

85

1

T146

1

T147

1

T148

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T11

2

T149

1

T66

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T16

2

T24

2

T149

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

85

1

T12

1

T16

3

T149

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

73

1

T11

1

T149

1

T66

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

67

1

T11

3

T149

1

T76

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

123

1

T11

6

T12

2

T24

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T12

1

T66

1

T28

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

80

1

T12

1

T66

2

T76

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T11

1

T12

2

T16

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

95

1

T11

1

T149

1

T67

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

75

1

T149

1

T66

2

T76

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T11

1

T66

1

T76

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T11

3

T16

3

T66

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

71

1

T11

3

T16

1

T76

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T12

4

T149

1

T66

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4498	1			T13	27		T14	2		T15	50
auto[0]	values[0]	valids[0x1]	19188	1			T3	2		T13	46		T15	135
auto[0]	values[1]	valids[0x1]	712	1			T13	4		T15	6		T16	3
auto[0]	values[2]	valids[0x0]	593	1			T13	10		T15	5		T16	7
auto[0]	values[2]	valids[0x1]	419	1			T13	3		T15	3		T16	4
auto[0]	values[3]	valids[0x0]	653	1			T15	8		T16	2		T17	17
auto[0]	values[3]	valids[0x1]	357	1			T13	1		T15	2		T16	1
auto[0]	values[4]	valids[0x0]	567	1			T3	2		T13	2		T15	5
auto[0]	values[4]	valids[0x1]	365	1			T13	1		T15	4		T16	5
auto[0]	values[5]	valids[0x0]	633	1			T13	1		T15	3		T16	3
auto[0]	values[5]	valids[0x1]	348	1			T13	4		T15	7		T16	3
auto[0]	values[6]	valids[0x0]	653	1			T13	1		T15	12		T16	4
auto[0]	values[6]	valids[0x1]	371	1			T15	5		T16	7		T17	4
auto[0]	values[7]	valids[0x0]	593	1			T13	5		T15	10		T16	3
auto[0]	values[7]	valids[0x1]	304	1			T13	10		T16	6		T17	8
auto[0]	values[8]	valids[0x0]	4148	1			T3	8		T13	31		T15	53
auto[0]	values[8]	valids[0x1]	2485	1			T3	2		T13	14		T15	14
auto[1]	values[0]	valids[0x0]	3433	1			T9	7		T11	30		T12	45
auto[1]	values[0]	valids[0x1]	10896	1			T9	7		T11	160		T12	38
auto[1]	values[1]	valids[0x1]	477	1			T9	5		T11	3		T12	1
auto[1]	values[2]	valids[0x0]	324	1			T9	1		T11	2		T12	1
auto[1]	values[2]	valids[0x1]	233	1			T12	1		T16	1		T149	1
auto[1]	values[3]	valids[0x0]	286	1			T9	4		T11	1		T12	2
auto[1]	values[3]	valids[0x1]	214	1			T11	2		T12	6		T16	1
auto[1]	values[4]	valids[0x0]	321	1			T9	3		T11	4		T12	7
auto[1]	values[4]	valids[0x1]	226	1			T9	2		T149	2		T66	3
auto[1]	values[5]	valids[0x0]	348	1			T9	3		T11	2		T12	3
auto[1]	values[5]	valids[0x1]	206	1			T11	3		T12	1		T16	7
auto[1]	values[6]	valids[0x0]	351	1			T9	2		T11	3		T12	4
auto[1]	values[6]	valids[0x1]	181	1			T11	2		T12	4		T16	1
auto[1]	values[7]	valids[0x0]	291	1			T9	1		T11	3		T12	2
auto[1]	values[7]	valids[0x1]	244	1			T9	1		T11	3		T12	6
auto[1]	values[8]	valids[0x0]	2244	1			T9	1		T11	22		T12	27
auto[1]	values[8]	valids[0x1]	1500	1			T9	3		T11	19		T12	12