Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3591919

1

T3

1

T9

1106

T11

5419

auto[1]

33048

1

T11

99

T12

146

T13

54

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

901316

1

T3

1

T9

92

T11

59

auto[1]

2723651

1

T9

1014

T11

5459

T12

5075

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	634881	1			T3	1		T9	6		T11	1443
auto[524288:1048575]	409302	1			T9	27		T11	1062		T12	299
auto[1048576:1572863]	454002	1			T9	803		T11	9		T12	282
auto[1572864:2097151]	455723	1			T11	270		T12	16		T13	3149
auto[2097152:2621439]	406688	1			T11	134		T12	833		T13	196
auto[2621440:3145727]	406633	1			T11	1543		T12	864		T13	16
auto[3145728:3670015]	439633	1			T11	348		T12	37		T13	2867
auto[3670016:4194303]	418105	1			T9	270		T11	709		T12	298

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2761781

1

T3

1

T9

1106

T11

5503

auto[1]

863186

1

T11

15

T12

7

T13

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3136665

1

T3

1

T9

839

T11

4697

auto[1]

488302

1

T9

267

T11

821

T12

300

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	171530	1			T3	1		T9	6		T11	10
auto[0]	auto[0]	auto[0:524287]	auto[1]	397856	1			T11	1433		T12	2765		T13	8294
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	85493	1			T9	25		T11	8		T12	15
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	262818	1			T11	200		T12	256		T13	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	107345	1			T9	26		T11	1		T12	13
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	274254	1			T9	512		T11	1		T12	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	120326	1			T11	3		T12	16		T13	58
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	267040	1			T11	257		T13	2677		T16	1027
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	109219	1			T11	2		T12	46		T13	59
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	242010	1			T11	129		T12	696		T13	134
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	88066	1			T11	7		T12	54		T13	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	259886	1			T11	1536		T12	512		T13	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	98824	1			T11	5		T12	21		T13	28
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	261478	1			T11	338		T12	6		T13	2836
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105440	1			T9	26		T11	2		T12	36
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	255995	1			T9	244		T11	707		T12	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	2789	1			T13	10		T15	2		T16	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	58593	1			T13	256		T15	2		T16	4
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	494	1			T9	2		T11	8		T12	25
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56634	1			T11	772		T16	514		T38	2042
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	560	1			T9	7		T34	5		T31	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	68026	1			T9	258		T34	2		T31	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	650	1			T13	18		T17	3		T38	8
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	64677	1			T13	384		T17	2		T34	1018
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2371	1			T12	2		T13	3		T17	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48847	1			T17	550		T34	256		T38	2349
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1630	1			T12	11		T15	2		T16	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52844	1			T12	256		T15	2461		T16	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1062	1			T13	3		T15	1		T16	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	74537	1			T15	256		T16	257		T31	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1003	1			T12	6		T15	1		T17	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49622	1			T35	3098		T149	4		T76	1024
auto[1]	auto[0]	auto[0:524287]	auto[0]	525	1			T13	4		T15	5		T16	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	2935	1			T13	38		T15	11		T16	18
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	399	1			T11	5		T12	3		T15	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3135	1			T11	28		T15	1		T17	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	552	1			T11	1		T12	13		T15	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2611	1			T11	6		T15	5		T16	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	437	1			T11	1		T13	7		T16	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2116	1			T11	9		T16	1		T17	16
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	462	1			T11	1		T12	17		T15	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3456	1			T11	2		T12	72		T15	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	465	1			T12	31		T15	1		T17	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3260	1			T15	3		T17	10		T34	63
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	544	1			T11	1		T12	10		T16	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2743	1			T11	4		T16	4		T17	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	398	1			T15	2		T16	1		T17	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	5047	1			T15	5		T16	2		T17	9
auto[1]	auto[1]	auto[0:524287]	auto[0]	99	1			T15	2		T16	4		T17	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	554	1			T15	5		T16	10		T34	20
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	61	1			T11	4		T16	2		T35	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	268	1			T11	37		T66	10		T184	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	78	1			T34	2		T31	1		T38	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	576	1			T34	10		T31	3		T38	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	138	1			T13	5		T17	2		T38	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	339	1			T17	7		T38	5		T182	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	85	1			T35	8		T149	1		T182	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	238	1			T35	31		T182	23		T196	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	85	1			T16	1		T35	4		T67	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	397	1			T67	2		T70	28		T22	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T16	1		T31	1		T35	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	355	1			T16	3		T31	6		T18	40
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	96	1			T149	1		T28	1		T67	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	504	1			T28	7		T67	1		T70	17

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2250375	1			T3	1		T9	839		T11	4634
auto[0]	auto[0]	auto[1]	857205	1			T11	5		T14	368		T17	3
auto[0]	auto[1]	auto[0]	479074	1			T9	267		T11	778		T12	300
auto[0]	auto[1]	auto[1]	5265	1			T11	2		T34	2		T66	1
auto[1]	auto[0]	auto[0]	28496	1			T11	54		T12	139		T13	47
auto[1]	auto[0]	auto[1]	589	1			T11	4		T12	7		T13	2
auto[1]	auto[1]	auto[0]	3836	1			T11	37		T13	4		T15	7
auto[1]	auto[1]	auto[1]	127	1			T11	4		T13	1		T34	2