Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2927997	1			T2	144		T3	1		T4	1677
all_pins[1]	2927997	1			T2	144		T3	1		T4	1677
all_pins[2]	2927997	1			T2	144		T3	1		T4	1677
all_pins[3]	2927997	1			T2	144		T3	1		T4	1677
all_pins[4]	2927997	1			T2	144		T3	1		T4	1677
all_pins[5]	2927997	1			T2	144		T3	1		T4	1677
all_pins[6]	2927997	1			T2	144		T3	1		T4	1677
all_pins[7]	2927997	1			T2	144		T3	1		T4	1677

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23298805	1			T2	1152		T3	8		T4	13416
values[0x1]	125171	1			T6	41		T16	3		T17	3548
transitions[0x0=>0x1]	123185	1			T6	30		T16	3		T17	3457
transitions[0x1=>0x0]	123196	1			T6	30		T16	3		T17	3457

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2927502	1			T2	144		T3	1		T4	1677
all_pins[0]	values[0x1]	495	1			T6	8		T17	100		T20	2
all_pins[0]	transitions[0x0=>0x1]	385	1			T6	7		T17	37		T20	2
all_pins[0]	transitions[0x1=>0x0]	506	1			T6	4		T19	7		T20	1
all_pins[1]	values[0x0]	2927381	1			T2	144		T3	1		T4	1677
all_pins[1]	values[0x1]	616	1			T6	5		T17	63		T19	7
all_pins[1]	transitions[0x0=>0x1]	525	1			T6	2		T17	39		T19	7
all_pins[1]	transitions[0x1=>0x0]	280	1			T6	4		T17	3		T19	2
all_pins[2]	values[0x0]	2927626	1			T2	144		T3	1		T4	1677
all_pins[2]	values[0x1]	371	1			T6	7		T17	27		T19	2
all_pins[2]	transitions[0x0=>0x1]	316	1			T6	6		T17	24		T19	1
all_pins[2]	transitions[0x1=>0x0]	152	1			T6	3		T19	3		T20	1
all_pins[3]	values[0x0]	2927790	1			T2	144		T3	1		T4	1677
all_pins[3]	values[0x1]	207	1			T6	4		T17	3		T19	4
all_pins[3]	transitions[0x0=>0x1]	160	1			T6	3		T17	3		T19	2
all_pins[3]	transitions[0x1=>0x0]	151	1			T6	4		T16	2		T19	2
all_pins[4]	values[0x0]	2927799	1			T2	144		T3	1		T4	1677
all_pins[4]	values[0x1]	198	1			T6	5		T16	2		T19	4
all_pins[4]	transitions[0x0=>0x1]	151	1			T6	3		T16	2		T19	2
all_pins[4]	transitions[0x1=>0x0]	2656	1			T6	3		T16	1		T19	469
all_pins[5]	values[0x0]	2925294	1			T2	144		T3	1		T4	1677
all_pins[5]	values[0x1]	2703	1			T6	5		T16	1		T19	471
all_pins[5]	transitions[0x0=>0x1]	1170	1			T6	5		T16	1		T19	4
all_pins[5]	transitions[0x1=>0x0]	118850	1			T6	4		T17	3354		T19	11296
all_pins[6]	values[0x0]	2807614	1			T2	144		T3	1		T4	1677
all_pins[6]	values[0x1]	120383	1			T6	4		T17	3354		T19	11763
all_pins[6]	transitions[0x0=>0x1]	120342	1			T6	2		T17	3354		T19	11763
all_pins[6]	transitions[0x1=>0x0]	157	1			T6	1		T17	1		T19	7
all_pins[7]	values[0x0]	2927799	1			T2	144		T3	1		T4	1677
all_pins[7]	values[0x1]	198	1			T6	3		T17	1		T19	7
all_pins[7]	transitions[0x0=>0x1]	136	1			T6	2		T19	6		T21	3
all_pins[7]	transitions[0x1=>0x0]	444	1			T6	7		T17	99		T20	2