Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21293

1

T3

14

T13

90

T14

2

auto[1]

15594

1

T13

70

T15

153

T16

85

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4010	1			T15	101		T17	64		T45	6
values[1]	4539	1			T13	40		T14	2		T15	51
values[2]	4498	1			T13	20		T15	24		T16	21
values[3]	5242	1			T3	14		T15	68		T17	20
values[4]	4462	1			T13	20		T15	24		T17	90
values[5]	5169	1			T13	40		T15	30		T16	24
values[6]	4376	1			T13	40		T16	46		T17	84
values[7]	4591	1			T15	24		T16	48		T17	41

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4339	1			T13	20		T15	24		T16	24
values[1]	4391	1			T14	2		T15	42		T16	27
values[2]	4827	1			T15	43		T16	22		T17	58
values[3]	4075	1			T3	14		T17	25		T45	6
values[4]	5365	1			T13	80		T15	24		T17	196
values[5]	4840	1			T15	60		T16	67		T17	97
values[6]	4282	1			T13	40		T15	81		T17	149
values[7]	4768	1			T13	20		T15	48		T16	43

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	373	1			T15	13		T201	13		T160	25
auto[0]	values[0]	values[1]	258	1			T15	10		T18	10		T157	11
auto[0]	values[0]	values[2]	235	1			T15	13		T18	14		T186	11
auto[0]	values[0]	values[3]	206	1			T45	6		T159	13		T18	31
auto[0]	values[0]	values[4]	336	1			T17	8		T34	14		T192	9
auto[0]	values[0]	values[5]	351	1			T15	26		T17	29		T27	13
auto[0]	values[0]	values[6]	176	1			T212	4		T18	14		T127	5
auto[0]	values[0]	values[7]	461	1			T182	8		T213	10		T196	24
auto[0]	values[1]	values[0]	444	1			T214	6		T201	12		T193	14
auto[0]	values[1]	values[1]	355	1			T14	2		T70	4		T162	11
auto[0]	values[1]	values[2]	374	1			T16	16		T39	18		T160	12
auto[0]	values[1]	values[3]	259	1			T38	16		T36	13		T69	12
auto[0]	values[1]	values[4]	298	1			T13	23		T17	5		T80	16
auto[0]	values[1]	values[5]	232	1			T35	12		T18	22		T196	12
auto[0]	values[1]	values[6]	255	1			T15	28		T182	97		T26	12
auto[0]	values[1]	values[7]	390	1			T16	11		T160	10		T183	18
auto[0]	values[2]	values[0]	238	1			T13	11		T17	43		T34	48
auto[0]	values[2]	values[1]	263	1			T18	13		T215	6		T187	24
auto[0]	values[2]	values[2]	560	1			T17	14		T92	8		T38	11
auto[0]	values[2]	values[3]	469	1			T34	13		T216	8		T185	15
auto[0]	values[2]	values[4]	360	1			T34	15		T159	11		T217	14
auto[0]	values[2]	values[5]	434	1			T16	10		T34	53		T157	11
auto[0]	values[2]	values[6]	196	1			T17	7		T142	16		T218	11
auto[0]	values[2]	values[7]	265	1			T15	19		T219	16		T36	27
auto[0]	values[3]	values[0]	401	1			T82	14		T181	20		T157	9
auto[0]	values[3]	values[1]	553	1			T15	8		T17	11		T35	6
auto[0]	values[3]	values[2]	275	1			T15	10		T35	11		T201	13
auto[0]	values[3]	values[3]	245	1			T3	14		T160	12		T163	9
auto[0]	values[3]	values[4]	497	1			T197	14		T38	17		T163	10
auto[0]	values[3]	values[5]	447	1			T163	10		T157	11		T220	46
auto[0]	values[3]	values[6]	217	1			T34	15		T35	11		T142	19
auto[0]	values[3]	values[7]	298	1			T15	14		T160	12		T163	11
auto[0]	values[4]	values[0]	301	1			T17	14		T38	12		T221	8
auto[0]	values[4]	values[1]	332	1			T38	9		T196	31		T43	12
auto[0]	values[4]	values[2]	418	1			T35	13		T159	11		T162	14
auto[0]	values[4]	values[3]	326	1			T17	19		T29	17		T190	13
auto[0]	values[4]	values[4]	474	1			T182	16		T222	8		T157	13
auto[0]	values[4]	values[5]	293	1			T15	9		T35	12		T70	9
auto[0]	values[4]	values[6]	338	1			T13	11		T17	23		T38	7
auto[0]	values[4]	values[7]	247	1			T70	68		T185	13		T168	11
auto[0]	values[5]	values[0]	338	1			T16	8		T17	6		T70	81
auto[0]	values[5]	values[1]	190	1			T38	18		T223	11		T224	18
auto[0]	values[5]	values[2]	436	1			T17	22		T41	2		T38	11
auto[0]	values[5]	values[3]	239	1			T35	10		T181	13		T157	10
auto[0]	values[5]	values[4]	429	1			T208	22		T177	10		T182	9
auto[0]	values[5]	values[5]	363	1			T17	9		T38	14		T35	13
auto[0]	values[5]	values[6]	318	1			T13	6		T15	7		T17	10
auto[0]	values[5]	values[7]	339	1			T13	13		T38	7		T36	11
auto[0]	values[6]	values[0]	221	1			T160	15		T225	10		T196	15
auto[0]	values[6]	values[1]	376	1			T35	10		T226	4		T70	10
auto[0]	values[6]	values[2]	293	1			T35	7		T163	20		T182	24
auto[0]	values[6]	values[3]	291	1			T31	31		T178	6		T227	6
auto[0]	values[6]	values[4]	263	1			T13	26		T182	15		T228	56
auto[0]	values[6]	values[5]	190	1			T16	28		T17	11		T38	7
auto[0]	values[6]	values[6]	520	1			T17	35		T70	14		T182	8
auto[0]	values[6]	values[7]	416	1			T229	4		T230	4		T26	12
auto[0]	values[7]	values[0]	373	1			T231	14		T18	12		T232	2
auto[0]	values[7]	values[1]	322	1			T16	12		T179	34		T163	15
auto[0]	values[7]	values[2]	327	1			T35	12		T233	82		T36	15
auto[0]	values[7]	values[3]	381	1			T160	14		T18	13		T69	13
auto[0]	values[7]	values[4]	310	1			T15	12		T17	14		T34	14
auto[0]	values[7]	values[5]	372	1			T17	14		T38	14		T70	116
auto[0]	values[7]	values[6]	257	1			T210	8		T209	8		T234	15
auto[0]	values[7]	values[7]	279	1			T16	13		T169	10		T157	13
auto[1]	values[0]	values[0]	242	1			T15	11		T201	7		T160	1
auto[1]	values[0]	values[1]	103	1			T15	11		T18	10		T157	9
auto[1]	values[0]	values[2]	125	1			T15	7		T18	6		T186	11
auto[1]	values[0]	values[3]	125	1			T159	7		T18	7		T196	7
auto[1]	values[0]	values[4]	232	1			T17	24		T34	64		T205	10
auto[1]	values[0]	values[5]	91	1			T15	10		T17	3		T27	7
auto[1]	values[0]	values[6]	273	1			T18	6		T127	80		T223	42
auto[1]	values[0]	values[7]	423	1			T182	12		T196	5		T190	9
auto[1]	values[1]	values[0]	184	1			T201	8		T185	23		T26	9
auto[1]	values[1]	values[1]	255	1			T33	18		T70	16		T162	9
auto[1]	values[1]	values[2]	131	1			T16	6		T39	2		T160	8
auto[1]	values[1]	values[3]	151	1			T38	8		T36	14		T69	8
auto[1]	values[1]	values[4]	315	1			T13	17		T17	138		T228	13
auto[1]	values[1]	values[5]	190	1			T35	8		T18	5		T196	11
auto[1]	values[1]	values[6]	220	1			T15	23		T182	8		T26	8
auto[1]	values[1]	values[7]	486	1			T16	11		T160	14		T127	12
auto[1]	values[2]	values[0]	124	1			T13	9		T17	7		T34	5
auto[1]	values[2]	values[1]	112	1			T18	7		T234	9		T171	12
auto[1]	values[2]	values[2]	449	1			T17	17		T38	11		T163	13
auto[1]	values[2]	values[3]	308	1			T34	7		T185	5		T26	10
auto[1]	values[2]	values[4]	233	1			T34	5		T195	14		T159	9
auto[1]	values[2]	values[5]	208	1			T16	11		T34	9		T157	9
auto[1]	values[2]	values[6]	96	1			T17	13		T142	10		T218	9
auto[1]	values[2]	values[7]	183	1			T15	5		T36	8		T168	10
auto[1]	values[3]	values[0]	213	1			T40	20		T181	5		T157	11
auto[1]	values[3]	values[1]	297	1			T15	13		T17	9		T35	14
auto[1]	values[3]	values[2]	271	1			T15	13		T35	9		T201	7
auto[1]	values[3]	values[3]	227	1			T160	8		T163	17		T157	10
auto[1]	values[3]	values[4]	414	1			T38	8		T163	10		T69	37
auto[1]	values[3]	values[5]	349	1			T163	10		T157	9		T192	2
auto[1]	values[3]	values[6]	223	1			T34	47		T35	9		T142	25
auto[1]	values[3]	values[7]	315	1			T15	10		T160	8		T163	9
auto[1]	values[4]	values[0]	157	1			T17	9		T38	9		T157	8
auto[1]	values[4]	values[1]	216	1			T38	11		T196	9		T43	10
auto[1]	values[4]	values[2]	215	1			T35	7		T159	9		T162	6
auto[1]	values[4]	values[3]	183	1			T17	6		T29	5		T190	7
auto[1]	values[4]	values[4]	207	1			T175	10		T182	11		T157	7
auto[1]	values[4]	values[5]	335	1			T15	15		T35	8		T70	99
auto[1]	values[4]	values[6]	259	1			T13	9		T17	19		T38	22
auto[1]	values[4]	values[7]	161	1			T70	5		T185	7		T168	32
auto[1]	values[5]	values[0]	339	1			T16	16		T17	14		T70	102
auto[1]	values[5]	values[1]	269	1			T38	23		T223	9		T235	5
auto[1]	values[5]	values[2]	356	1			T17	5		T38	9		T70	7
auto[1]	values[5]	values[3]	279	1			T35	10		T181	7		T157	10
auto[1]	values[5]	values[4]	399	1			T182	11		T29	9		T192	8
auto[1]	values[5]	values[5]	453	1			T17	16		T38	6		T35	7
auto[1]	values[5]	values[6]	200	1			T13	14		T15	23		T17	13
auto[1]	values[5]	values[7]	222	1			T13	7		T38	13		T36	9
auto[1]	values[6]	values[0]	155	1			T160	5		T196	12		T236	6
auto[1]	values[6]	values[1]	134	1			T35	10		T70	10		T192	9
auto[1]	values[6]	values[2]	148	1			T35	13		T163	13		T182	12
auto[1]	values[6]	values[3]	112	1			T31	6		T157	8		T126	9
auto[1]	values[6]	values[4]	324	1			T13	14		T182	111		T228	11
auto[1]	values[6]	values[5]	270	1			T16	18		T17	9		T38	13
auto[1]	values[6]	values[6]	489	1			T17	29		T70	32		T182	67
auto[1]	values[6]	values[7]	174	1			T37	22		T26	49		T142	10
auto[1]	values[7]	values[0]	236	1			T18	8		T190	7		T69	16
auto[1]	values[7]	values[1]	356	1			T16	15		T237	10		T179	3
auto[1]	values[7]	values[2]	214	1			T35	8		T36	6		T238	7
auto[1]	values[7]	values[3]	274	1			T160	6		T18	68		T69	7
auto[1]	values[7]	values[4]	274	1			T15	12		T17	7		T34	6
auto[1]	values[7]	values[5]	262	1			T17	6		T38	6		T70	10
auto[1]	values[7]	values[6]	245	1			T200	6		T209	12		T234	37
auto[1]	values[7]	values[7]	109	1			T16	8		T157	7		T26	20