Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	460	1			T13	4		T15	3		T16	3
auto[ReadAddrCrossIntoMailbox]	323	1			T13	1		T15	5		T16	2
auto[ReadAddrCrossOutOfMailbox]	405	1			T13	2		T15	5		T16	2
auto[ReadAddrCrossAllMailbox]	239	1			T13	3		T15	4		T16	3
auto[ReadAddrOutsideMailbox]	4223	1			T3	2		T13	20		T15	37

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2790

1

T3

1

T13

18

T15

21

auto[1]

2860

1

T3

1

T13

12

T15

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	962	1			T13	4		T15	8		T16	7
read_ops[0x0b]	904	1			T13	7		T15	6		T16	8
read_ops[0x3b]	983	1			T3	2		T13	5		T15	10
read_ops[0x6b]	947	1			T13	3		T15	13		T16	11
read_ops[0xbb]	937	1			T13	5		T15	6		T16	4
read_ops[0xeb]	917	1			T13	6		T15	11		T16	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T92	1		T38	1		T39	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T34	1		T92	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T35	1		T190	3		T168	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T15	3		T157	2		T126	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T17	3		T38	1		T159	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T15	1		T160	1		T231	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T16	1		T17	2		T43	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T13	2		T15	1		T70	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T15	2		T16	2		T17	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	412	1			T13	2		T15	1		T16	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T17	1		T70	1		T162	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T182	1		T228	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T36	1		T194	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T194	1		T26	1		T27	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T13	1		T15	1		T160	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T15	1		T35	1		T182	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T13	1		T15	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T16	1		T228	1		T69	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	328	1			T13	4		T15	1		T16	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T13	1		T15	2		T16	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T15	1		T17	4		T178	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T13	1		T15	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T159	1		T70	1		T182	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T13	1		T70	2		T182	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T160	2		T182	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T31	1		T27	1		T236	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T15	1		T16	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T38	1		T160	1		T182	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	376	1			T3	1		T13	1		T15	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	378	1			T3	1		T13	2		T15	6
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T13	1		T16	1		T17	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T15	1		T70	1		T160	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T15	1		T16	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T17	1		T35	1		T163	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T35	1		T194	1		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T16	1		T201	1		T194	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T182	1		T126	1		T26	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T17	1		T159	1		T201	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	369	1			T13	2		T15	4		T16	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	342	1			T15	7		T16	3		T17	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T13	1		T17	1		T38	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T38	1		T35	1		T160	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T159	1		T163	1		T69	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T16	1		T38	1		T35	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T35	1		T194	2		T18	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	48	1			T15	1		T16	1		T17	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T159	1		T36	1		T201	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T26	1		T145	1		T64	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T13	3		T15	4		T33	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	365	1			T13	1		T15	1		T16	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T13	1		T17	2		T35	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T16	1		T35	2		T39	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T15	1		T31	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T34	1		T70	2		T194	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	41	1			T13	1		T240	1		T160	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T15	1		T17	1		T240	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T194	1		T160	1		T231	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T15	1		T194	1		T231	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	340	1			T13	2		T15	3		T16	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	344	1			T13	2		T15	5		T16	1