Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4858	1			T3	14		T13	40		T15	48
values[1]	4031	1			T16	73		T17	52		T38	102
values[2]	4013	1			T13	40		T15	54		T16	21
values[3]	4186	1			T15	23		T16	41		T17	105
values[4]	5261	1			T13	20		T15	21		T33	18
values[5]	5427	1			T13	40		T15	24		T17	207
values[6]	4216	1			T15	71		T16	26		T17	20
values[7]	4895	1			T13	20		T14	2		T15	81

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4711	1			T15	21		T17	46		T34	73
values[1]	5298	1			T13	40		T15	128		T33	18
values[2]	4375	1			T3	14		T13	20		T15	98
values[3]	4696	1			T13	60		T15	27		T16	48
values[4]	3424	1			T16	46		T17	65		T31	37
values[5]	5241	1			T13	20		T15	24		T16	42
values[6]	4488	1			T13	20		T14	2		T16	21
values[7]	4654	1			T15	24		T37	22		T34	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35987

1

T3

14

T13

159

T14

2

auto[1]

900

1

T13

1

T15

10

T16

13

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	560	1			T163	23		T69	36		T185	20
auto[0]	values[0]	values[1]	384	1			T13	20		T39	20		T157	19
auto[0]	values[0]	values[2]	623	1			T3	14		T15	23		T163	20
auto[0]	values[0]	values[3]	709	1			T13	20		T38	20		T18	69
auto[0]	values[0]	values[4]	560	1			T17	25		T205	10		T26	20
auto[0]	values[0]	values[5]	844	1			T17	50		T34	19		T160	25
auto[0]	values[0]	values[6]	354	1			T41	2		T163	33		T157	20
auto[0]	values[0]	values[7]	734	1			T15	24		T200	6		T36	35
auto[0]	values[1]	values[0]	340	1			T35	40		T162	18		T126	24
auto[0]	values[1]	values[1]	595	1			T17	19		T208	22		T179	37
auto[0]	values[1]	values[2]	405	1			T17	29		T18	40		T142	20
auto[0]	values[1]	values[3]	347	1			T16	24		T38	20		T160	22
auto[0]	values[1]	values[4]	367	1			T16	23		T237	8		T201	20
auto[0]	values[1]	values[5]	766	1			T16	20		T38	22		T159	15
auto[0]	values[1]	values[6]	502	1			T38	40		T36	27		T230	4
auto[0]	values[1]	values[7]	606	1			T38	20		T216	8		T81	14
auto[0]	values[2]	values[0]	544	1			T34	51		T35	20		T241	6
auto[0]	values[2]	values[1]	634	1			T15	24		T17	50		T38	28
auto[0]	values[2]	values[2]	420	1			T15	30		T35	18		T18	79
auto[0]	values[2]	values[3]	562	1			T13	39		T16	19		T34	62
auto[0]	values[2]	values[4]	336	1			T31	36		T163	21		T27	20
auto[0]	values[2]	values[5]	385	1			T17	18		T239	4		T163	20
auto[0]	values[2]	values[6]	531	1			T45	6		T240	4		T18	26
auto[0]	values[2]	values[7]	492	1			T34	20		T242	4		T204	24
auto[0]	values[3]	values[0]	636	1			T34	20		T243	2		T126	22
auto[0]	values[3]	values[1]	698	1			T15	23		T168	55		T191	26
auto[0]	values[3]	values[2]	377	1			T70	20		T160	50		T192	39
auto[0]	values[3]	values[3]	416	1			T17	32		T92	8		T70	44
auto[0]	values[3]	values[4]	370	1			T182	42		T27	20		T209	43
auto[0]	values[3]	values[5]	660	1			T16	20		T17	39		T219	16
auto[0]	values[3]	values[6]	475	1			T16	18		T17	31		T70	70
auto[0]	values[3]	values[7]	445	1			T35	20		T159	19		T163	22
auto[0]	values[4]	values[0]	763	1			T15	21		T17	25		T38	20
auto[0]	values[4]	values[1]	745	1			T33	18		T17	20		T39	19
auto[0]	values[4]	values[2]	714	1			T34	62		T182	20		T190	20
auto[0]	values[4]	values[3]	737	1			T17	36		T195	14		T70	108
auto[0]	values[4]	values[4]	410	1			T40	18		T160	20		T18	20
auto[0]	values[4]	values[5]	483	1			T13	20		T197	14		T157	20
auto[0]	values[4]	values[6]	763	1			T163	20		T244	48		T69	28
auto[0]	values[4]	values[7]	517	1			T37	16		T160	23		T192	18
auto[0]	values[5]	values[0]	645	1			T17	19		T214	6		T233	82
auto[0]	values[5]	values[1]	621	1			T15	24		T35	36		T36	20
auto[0]	values[5]	values[2]	780	1			T13	20		T35	19		T80	16
auto[0]	values[5]	values[3]	611	1			T70	19		T225	10		T245	16
auto[0]	values[5]	values[4]	508	1			T17	19		T38	22		T29	20
auto[0]	values[5]	values[5]	696	1			T17	21		T38	20		T36	20
auto[0]	values[5]	values[6]	830	1			T13	20		T17	143		T69	24
auto[0]	values[5]	values[7]	606	1			T159	20		T201	20		T157	17
auto[0]	values[6]	values[0]	624	1			T181	20		T196	25		T246	44
auto[0]	values[6]	values[1]	668	1			T182	20		T247	2		T126	19
auto[0]	values[6]	values[2]	401	1			T15	42		T16	24		T248	4
auto[0]	values[6]	values[3]	385	1			T15	25		T126	19		T192	17
auto[0]	values[6]	values[4]	463	1			T17	20		T160	20		T157	20
auto[0]	values[6]	values[5]	656	1			T39	58		T180	41		T249	2
auto[0]	values[6]	values[6]	308	1			T35	20		T226	4		T250	6
auto[0]	values[6]	values[7]	601	1			T160	45		T29	24		T27	21
auto[0]	values[7]	values[0]	495	1			T38	21		T182	27		T69	71
auto[0]	values[7]	values[1]	822	1			T13	20		T15	53		T34	77
auto[0]	values[7]	values[2]	558	1			T194	18		T251	4		T252	16
auto[0]	values[7]	values[3]	788	1			T38	20		T210	8		T178	6
auto[0]	values[7]	values[4]	330	1			T16	22		T157	20		T168	19
auto[0]	values[7]	values[5]	635	1			T15	23		T17	21		T38	18
auto[0]	values[7]	values[6]	620	1			T14	2		T35	40		T169	10
auto[0]	values[7]	values[7]	527	1			T160	18		T29	21		T26	23
auto[1]	values[0]	values[0]	15	1			T253	1		T254	2		T255	3
auto[1]	values[0]	values[1]	7	1			T157	1		T30	1		T218	1
auto[1]	values[0]	values[2]	11	1			T15	1		T26	2		T246	1
auto[1]	values[0]	values[3]	19	1			T18	2		T127	1		T64	2
auto[1]	values[0]	values[4]	11	1			T64	4		T256	3		T257	2
auto[1]	values[0]	values[5]	8	1			T17	1		T34	1		T69	1
auto[1]	values[0]	values[6]	10	1			T258	4		T145	2		T259	1
auto[1]	values[0]	values[7]	9	1			T26	3		T145	1		T223	1
auto[1]	values[1]	values[0]	8	1			T162	2		T126	2		T57	2
auto[1]	values[1]	values[1]	19	1			T17	1		T182	2		T196	2
auto[1]	values[1]	values[2]	7	1			T17	3		T260	1		T261	2
auto[1]	values[1]	values[3]	27	1			T16	3		T160	2		T26	2
auto[1]	values[1]	values[4]	7	1			T16	1		T237	2		T157	2
auto[1]	values[1]	values[5]	16	1			T16	2		T159	5		T262	1
auto[1]	values[1]	values[6]	8	1			T196	1		T142	1		T127	1
auto[1]	values[1]	values[7]	11	1			T26	2		T127	1		T263	2
auto[1]	values[2]	values[0]	21	1			T34	2		T144	7		T129	1
auto[1]	values[2]	values[1]	11	1			T38	1		T264	1		T265	4
auto[1]	values[2]	values[2]	6	1			T35	2		T142	2		T223	1
auto[1]	values[2]	values[3]	20	1			T13	1		T16	2		T38	3
auto[1]	values[2]	values[4]	15	1			T31	1		T163	1		T129	6
auto[1]	values[2]	values[5]	10	1			T17	2		T157	2		T266	2
auto[1]	values[2]	values[6]	14	1			T182	2		T64	1		T267	4
auto[1]	values[2]	values[7]	12	1			T168	1		T236	2		T129	6
auto[1]	values[3]	values[0]	13	1			T126	2		T209	1		T43	2
auto[1]	values[3]	values[1]	16	1			T168	3		T127	3		T259	1
auto[1]	values[3]	values[2]	12	1			T160	4		T192	1		T43	1
auto[1]	values[3]	values[3]	9	1			T70	2		T268	5		T269	1
auto[1]	values[3]	values[4]	9	1			T209	1		T127	1		T253	1
auto[1]	values[3]	values[5]	14	1			T17	3		T228	1		T185	1
auto[1]	values[3]	values[6]	20	1			T16	3		T64	1		T235	1
auto[1]	values[3]	values[7]	16	1			T159	1		T192	1		T209	2
auto[1]	values[4]	values[0]	16	1			T38	1		T192	1		T43	3
auto[1]	values[4]	values[1]	20	1			T39	1		T162	2		T168	1
auto[1]	values[4]	values[2]	13	1			T142	3		T30	3		T270	2
auto[1]	values[4]	values[3]	18	1			T17	4		T70	1		T209	3
auto[1]	values[4]	values[4]	9	1			T40	2		T168	2		T271	2
auto[1]	values[4]	values[5]	7	1			T26	2		T130	1		T235	1
auto[1]	values[4]	values[6]	18	1			T69	4		T43	2		T246	1
auto[1]	values[4]	values[7]	28	1			T37	6		T160	1		T192	2
auto[1]	values[5]	values[0]	6	1			T17	2		T262	1		T272	2
auto[1]	values[5]	values[1]	17	1			T35	4		T36	1		T70	2
auto[1]	values[5]	values[2]	24	1			T35	1		T26	1		T218	2
auto[1]	values[5]	values[3]	16	1			T70	1		T245	2		T126	1
auto[1]	values[5]	values[4]	12	1			T17	1		T38	3		T69	1
auto[1]	values[5]	values[5]	23	1			T17	2		T201	3		T190	4
auto[1]	values[5]	values[6]	11	1			T69	2		T43	1		T223	1
auto[1]	values[5]	values[7]	21	1			T157	3		T218	1		T64	1
auto[1]	values[6]	values[0]	17	1			T196	2		T246	1		T273	1
auto[1]	values[6]	values[1]	18	1			T126	1		T274	2		T246	4
auto[1]	values[6]	values[2]	11	1			T15	2		T16	2		T142	1
auto[1]	values[6]	values[3]	15	1			T15	2		T126	1		T192	3
auto[1]	values[6]	values[4]	9	1			T275	1		T130	1		T273	1
auto[1]	values[6]	values[5]	14	1			T39	1		T26	1		T267	2
auto[1]	values[6]	values[6]	10	1			T196	5		T63	2		T130	1
auto[1]	values[6]	values[7]	16	1			T160	1		T29	3		T218	1
auto[1]	values[7]	values[0]	8	1			T69	2		T276	1		T277	1
auto[1]	values[7]	values[1]	23	1			T15	4		T34	1		T70	3
auto[1]	values[7]	values[2]	13	1			T209	1		T30	2		T263	1
auto[1]	values[7]	values[3]	17	1			T196	2		T142	2		T278	3
auto[1]	values[7]	values[4]	8	1			T168	1		T209	1		T279	1
auto[1]	values[7]	values[5]	24	1			T15	1		T17	2		T38	2
auto[1]	values[7]	values[6]	14	1			T190	2		T168	1		T246	2
auto[1]	values[7]	values[7]	13	1			T160	2		T29	1		T253	1