| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 0 | 8 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
| cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 87 | 1 | T91 | 6 | T136 | 3 | T125 | 1 | ||||
| auto[1] | 32 | 1 | T91 | 2 | T136 | 1 | T125 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| read_ops[0x03] | 28 | 1 | T280 | 6 | T281 | 4 | T62 | 4 | ||||
| read_ops[0x0b] | 16 | 1 | T206 | 4 | T281 | 2 | T282 | 6 | ||||
| read_ops[0x3b] | 18 | 1 | T283 | 3 | T284 | 2 | T62 | 6 | ||||
| read_ops[0x6b] | 27 | 1 | T91 | 8 | T202 | 1 | T280 | 4 | ||||
| read_ops[0xbb] | 18 | 1 | T136 | 4 | T206 | 2 | T285 | 2 | ||||
| read_ops[0xeb] | 12 | 1 | T125 | 2 | T281 | 1 | T62 | 8 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |