Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	830	1			T6	15		T16	4		T17	4
all_values[1]	830	1			T6	15		T16	4		T17	4
all_values[2]	830	1			T6	15		T16	4		T17	4
all_values[3]	830	1			T6	15		T16	4		T17	4
all_values[4]	830	1			T6	15		T16	4		T17	4
all_values[5]	830	1			T6	15		T16	4		T17	4
all_values[6]	830	1			T6	15		T16	4		T17	4
all_values[7]	830	1			T6	15		T16	4		T17	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3485

1

T6

64

T16

17

T17

15

auto[1]

3155

1

T6

56

T16

15

T17

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2651

1

T6

44

T16

24

T17

12

auto[1]

3989

1

T6

76

T16

8

T17

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3817

1

T6

71

T16

26

T17

18

auto[1]

2823

1

T6

49

T16

6

T17

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	159	1			T6	1		T16	1		T19	6
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T6	4		T19	1		T21	2
all_values[0]	auto[0]	auto[1]	auto[0]	135	1			T6	1		T16	3		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	100	1			T6	5		T20	1		T22	2
all_values[0]	auto[1]	auto[0]	auto[1]	190	1			T6	3		T19	3		T20	2
all_values[0]	auto[1]	auto[1]	auto[1]	161	1			T6	1		T17	2		T20	2
all_values[1]	auto[0]	auto[0]	auto[0]	151	1			T6	1		T16	2		T19	4
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T6	2		T19	1		T21	1
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T6	2		T16	2		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T6	1		T19	2		T22	2
all_values[1]	auto[1]	auto[0]	auto[1]	196	1			T6	3		T19	4		T20	3
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T6	6		T17	2		T19	3
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T6	4		T16	2		T19	6
all_values[2]	auto[0]	auto[0]	auto[1]	96	1			T6	1		T20	1		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	158	1			T6	2		T16	2		T19	6
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T6	4		T17	1		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	181	1			T6	2		T17	2		T20	2
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T6	2		T17	1		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T6	2		T16	1		T19	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T17	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T6	2		T16	3		T19	5
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T6	2		T17	2		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	188	1			T6	7		T17	1		T19	1
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T6	1		T19	5		T20	2
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T6	6		T16	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T21	2		T22	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T17	2		T19	5		T20	2
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T6	2		T16	1		T69	2
all_values[4]	auto[1]	auto[0]	auto[1]	211	1			T6	3		T16	1		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	149	1			T6	3		T16	1		T19	5
all_values[5]	auto[0]	auto[0]	auto[0]	215	1			T6	4		T16	1		T17	2
all_values[5]	auto[0]	auto[1]	auto[0]	237	1			T6	6		T19	5		T20	3
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T6	1		T16	3		T17	2
all_values[5]	auto[1]	auto[1]	auto[1]	188	1			T6	4		T19	4		T20	2
all_values[6]	auto[0]	auto[0]	auto[0]	193	1			T6	6		T16	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T20	1		T22	1		T69	4
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T6	3		T16	3		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T6	1		T19	1		T21	3
all_values[6]	auto[1]	auto[0]	auto[1]	174	1			T6	1		T17	2		T19	1
all_values[6]	auto[1]	auto[1]	auto[1]	158	1			T6	4		T19	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	194	1			T6	4		T16	2		T19	1
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T6	2		T16	1		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T17	1		T19	2		T20	1
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T6	1		T17	1		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T6	5		T16	1		T17	1
all_values[7]	auto[1]	auto[1]	auto[1]	157	1			T6	3		T19	3		T20	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal