Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1920

1

T2

1

T7

4

T15

10

auto[1]

1971

1

T7

6

T15

10

T16

20

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2101

1

T2

1

T7

8

T15

20

auto[1]

1790

1

T7

2

T17

5

T23

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3109

1

T7

7

T15

9

T16

28

auto[1]

782

1

T2

1

T7

3

T15

11

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	813	1			T7	3		T15	2		T16	15
valid[1]	793	1			T7	1		T15	5		T16	7
valid[2]	786	1			T7	1		T15	5		T16	4
valid[3]	712	1			T7	3		T15	6		T16	8
valid[4]	787	1			T2	1		T7	2		T15	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T7	1		T16	3		T17	2
auto[0]	auto[0]	valid[0]	auto[1]	180	1			T23	1		T79	2		T67	1
auto[0]	auto[0]	valid[1]	auto[0]	129	1			T16	4		T17	2		T24	1
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T17	1		T23	2		T76	1
auto[0]	auto[0]	valid[2]	auto[0]	143	1			T7	1		T15	1		T16	1
auto[0]	auto[0]	valid[2]	auto[1]	185	1			T23	1		T75	2		T77	1
auto[0]	auto[0]	valid[3]	auto[0]	120	1			T15	3		T16	4		T17	1
auto[0]	auto[0]	valid[3]	auto[1]	154	1			T7	2		T17	2		T23	2
auto[0]	auto[0]	valid[4]	auto[0]	128	1			T16	3		T17	1		T31	1
auto[0]	auto[0]	valid[4]	auto[1]	185	1			T38	1		T75	1		T294	7
auto[0]	auto[1]	valid[0]	auto[0]	144	1			T7	1		T15	1		T16	9
auto[0]	auto[1]	valid[0]	auto[1]	208	1			T23	4		T38	1		T78	1
auto[0]	auto[1]	valid[1]	auto[0]	134	1			T15	1		T16	1		T17	4
auto[0]	auto[1]	valid[1]	auto[1]	189	1			T23	3		T75	1		T76	1
auto[0]	auto[1]	valid[2]	auto[0]	128	1			T15	1		T16	2		T17	1
auto[0]	auto[1]	valid[2]	auto[1]	169	1			T23	4		T77	1		T78	1
auto[0]	auto[1]	valid[3]	auto[0]	137	1			T15	2		T17	3		T24	1
auto[0]	auto[1]	valid[3]	auto[1]	150	1			T17	1		T23	3		T75	1
auto[0]	auto[1]	valid[4]	auto[0]	135	1			T7	2		T16	1		T17	1
auto[0]	auto[1]	valid[4]	auto[1]	190	1			T17	1		T23	6		T38	1
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T16	2		T17	2		T295	1
auto[1]	auto[0]	valid[1]	auto[0]	76	1			T15	2		T16	1		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	86	1			T15	2		T38	1		T76	2
auto[1]	auto[0]	valid[3]	auto[0]	79	1			T15	1		T16	2		T17	2
auto[1]	auto[0]	valid[4]	auto[0]	80	1			T2	1		T15	1		T16	2
auto[1]	auto[1]	valid[0]	auto[0]	86	1			T7	1		T15	1		T16	1
auto[1]	auto[1]	valid[1]	auto[0]	85	1			T7	1		T15	2		T16	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T15	1		T16	1		T17	2
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T7	1		T16	2		T28	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T15	1		T16	2		T17	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal