Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52017

1

T2

11

T4

6

T5

24

auto[1]

17547

1

T5

6

T7

58

T17

48

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50413

1

T2

5

T4

3

T5

23

auto[1]

19151

1

T2

6

T4

3

T5

7

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35864	1			T2	7		T4	2		T5	17
others[1]	5831	1			T2	1		T5	3		T7	20
others[2]	5856	1			T2	1		T5	2		T7	25
others[3]	6670	1			T4	1		T5	4		T7	21
interest[1]	3957	1			T5	1		T7	17		T15	29
interest[4]	23385	1			T2	4		T4	1		T5	8
interest[64]	11386	1			T2	2		T4	3		T5	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16869	1			T2	3		T4	2		T5	10
auto[0]	auto[0]	others[1]	2759	1			T2	1		T5	1		T7	11
auto[0]	auto[0]	others[2]	2783	1			T5	1		T7	7		T15	31
auto[0]	auto[0]	others[3]	3190	1			T5	3		T7	9		T15	37
auto[0]	auto[0]	interest[1]	1866	1			T7	7		T15	18		T16	47
auto[0]	auto[0]	interest[4]	10916	1			T4	1		T5	4		T7	44
auto[0]	auto[0]	interest[64]	5399	1			T2	1		T4	1		T5	2
auto[0]	auto[1]	others[0]	9199	1			T5	3		T7	29		T17	29
auto[0]	auto[1]	others[1]	1453	1			T5	2		T7	2		T17	3
auto[0]	auto[1]	others[2]	1444	1			T7	10		T17	3		T23	23
auto[0]	auto[1]	others[3]	1619	1			T5	1		T7	4		T17	7
auto[0]	auto[1]	interest[1]	989	1			T7	4		T17	2		T23	16
auto[0]	auto[1]	interest[4]	6119	1			T7	16		T17	14		T23	103
auto[0]	auto[1]	interest[64]	2843	1			T7	9		T17	4		T23	45
auto[1]	auto[0]	others[0]	9796	1			T2	4		T5	4		T7	37
auto[1]	auto[0]	others[1]	1619	1			T7	7		T15	13		T16	32
auto[1]	auto[0]	others[2]	1629	1			T2	1		T5	1		T7	8
auto[1]	auto[0]	others[3]	1861	1			T4	1		T7	8		T15	16
auto[1]	auto[0]	interest[1]	1102	1			T5	1		T7	6		T15	11
auto[1]	auto[0]	interest[4]	6350	1			T2	4		T5	4		T7	18
auto[1]	auto[0]	interest[64]	3144	1			T2	1		T4	2		T5	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal