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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
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T1025 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3117649871 Aug 19 04:36:53 PM PDT 24 Aug 19 04:36:54 PM PDT 24 17881663 ps
T1026 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2600090222 Aug 19 04:36:28 PM PDT 24 Aug 19 04:36:32 PM PDT 24 2982424092 ps
T1027 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.387768350 Aug 19 04:36:48 PM PDT 24 Aug 19 04:36:49 PM PDT 24 13544875 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3462809731 Aug 19 04:36:16 PM PDT 24 Aug 19 04:36:39 PM PDT 24 4328950177 ps
T105 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2391269693 Aug 19 04:36:32 PM PDT 24 Aug 19 04:36:47 PM PDT 24 3001830687 ps
T106 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2821302817 Aug 19 04:36:24 PM PDT 24 Aug 19 04:36:27 PM PDT 24 74000742 ps
T73 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3392225600 Aug 19 04:36:33 PM PDT 24 Aug 19 04:36:34 PM PDT 24 73608978 ps
T100 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3438954008 Aug 19 04:36:51 PM PDT 24 Aug 19 04:36:54 PM PDT 24 74519348 ps
T1028 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4021135888 Aug 19 04:36:51 PM PDT 24 Aug 19 04:36:52 PM PDT 24 136480630 ps
T1029 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2799980972 Aug 19 04:36:23 PM PDT 24 Aug 19 04:36:24 PM PDT 24 21341612 ps
T97 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1326979886 Aug 19 04:36:53 PM PDT 24 Aug 19 04:36:55 PM PDT 24 126197350 ps
T1030 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1123786218 Aug 19 04:36:50 PM PDT 24 Aug 19 04:36:51 PM PDT 24 140927354 ps
T117 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.605551678 Aug 19 04:36:30 PM PDT 24 Aug 19 04:36:45 PM PDT 24 1226695717 ps
T140 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1963705184 Aug 19 04:36:38 PM PDT 24 Aug 19 04:36:40 PM PDT 24 429313600 ps
T1031 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1062081745 Aug 19 04:36:52 PM PDT 24 Aug 19 04:36:56 PM PDT 24 56323660 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1959544775 Aug 19 04:36:42 PM PDT 24 Aug 19 04:36:44 PM PDT 24 99060924 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.804380964 Aug 19 04:36:37 PM PDT 24 Aug 19 04:36:39 PM PDT 24 81682039 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1536319828 Aug 19 04:37:03 PM PDT 24 Aug 19 04:37:07 PM PDT 24 722231445 ps
T1035 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1196311784 Aug 19 04:36:56 PM PDT 24 Aug 19 04:36:57 PM PDT 24 298374802 ps
T93 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2343365038 Aug 19 04:36:19 PM PDT 24 Aug 19 04:36:23 PM PDT 24 102413197 ps
T99 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.198916303 Aug 19 04:36:36 PM PDT 24 Aug 19 04:36:40 PM PDT 24 270616175 ps
T1036 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1974895290 Aug 19 04:36:53 PM PDT 24 Aug 19 04:36:53 PM PDT 24 31574196 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1561905403 Aug 19 04:36:53 PM PDT 24 Aug 19 04:36:54 PM PDT 24 13092477 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1851436788 Aug 19 04:36:42 PM PDT 24 Aug 19 04:36:45 PM PDT 24 36511556 ps
T1039 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3150442315 Aug 19 04:36:46 PM PDT 24 Aug 19 04:36:46 PM PDT 24 22462857 ps
T1040 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1637972199 Aug 19 04:37:06 PM PDT 24 Aug 19 04:37:07 PM PDT 24 67804400 ps
T1041 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2276691499 Aug 19 04:36:52 PM PDT 24 Aug 19 04:36:53 PM PDT 24 66870408 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2600677565 Aug 19 04:36:43 PM PDT 24 Aug 19 04:36:44 PM PDT 24 16898061 ps
T152 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4104879750 Aug 19 04:36:50 PM PDT 24 Aug 19 04:37:09 PM PDT 24 332425835 ps
T1043 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3406950717 Aug 19 04:36:31 PM PDT 24 Aug 19 04:36:32 PM PDT 24 21324205 ps
T151 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2706160627 Aug 19 04:36:50 PM PDT 24 Aug 19 04:37:05 PM PDT 24 563853061 ps
T1044 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1984720451 Aug 19 04:36:40 PM PDT 24 Aug 19 04:36:42 PM PDT 24 31948250 ps
T1045 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1088112341 Aug 19 04:36:49 PM PDT 24 Aug 19 04:36:52 PM PDT 24 343166306 ps
T1046 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3513990240 Aug 19 04:36:58 PM PDT 24 Aug 19 04:37:00 PM PDT 24 29870365 ps
T1047 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2386054307 Aug 19 04:36:51 PM PDT 24 Aug 19 04:36:53 PM PDT 24 726739615 ps
T1048 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.79415136 Aug 19 04:37:10 PM PDT 24 Aug 19 04:37:11 PM PDT 24 51388102 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3915617697 Aug 19 04:36:55 PM PDT 24 Aug 19 04:36:58 PM PDT 24 169775252 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2339049919 Aug 19 04:36:59 PM PDT 24 Aug 19 04:37:02 PM PDT 24 442305297 ps
T156 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.393129936 Aug 19 04:36:23 PM PDT 24 Aug 19 04:36:43 PM PDT 24 2829898565 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3409351056 Aug 19 04:36:34 PM PDT 24 Aug 19 04:36:35 PM PDT 24 29009566 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.357444360 Aug 19 04:36:57 PM PDT 24 Aug 19 04:37:31 PM PDT 24 524132293 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3441724571 Aug 19 04:36:49 PM PDT 24 Aug 19 04:36:51 PM PDT 24 62906863 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1071995976 Aug 19 04:36:24 PM PDT 24 Aug 19 04:36:29 PM PDT 24 33318729 ps
T153 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.510259247 Aug 19 04:36:37 PM PDT 24 Aug 19 04:37:00 PM PDT 24 3202210657 ps
T141 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.775866342 Aug 19 04:36:40 PM PDT 24 Aug 19 04:36:43 PM PDT 24 111524441 ps
T94 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1736337975 Aug 19 04:36:38 PM PDT 24 Aug 19 04:36:40 PM PDT 24 102013679 ps
T1055 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3261773764 Aug 19 04:36:24 PM PDT 24 Aug 19 04:36:25 PM PDT 24 12979410 ps
T102 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1310828355 Aug 19 04:36:47 PM PDT 24 Aug 19 04:36:49 PM PDT 24 510677396 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1309798236 Aug 19 04:36:52 PM PDT 24 Aug 19 04:36:55 PM PDT 24 158208197 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.956048325 Aug 19 04:36:24 PM PDT 24 Aug 19 04:36:26 PM PDT 24 19514334 ps
T155 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2838502797 Aug 19 04:36:53 PM PDT 24 Aug 19 04:37:09 PM PDT 24 1324724520 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1275797400 Aug 19 04:36:46 PM PDT 24 Aug 19 04:36:48 PM PDT 24 106083371 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.850694547 Aug 19 04:36:50 PM PDT 24 Aug 19 04:36:52 PM PDT 24 122345302 ps
T74 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2040577750 Aug 19 04:36:40 PM PDT 24 Aug 19 04:36:41 PM PDT 24 49200823 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4067982345 Aug 19 04:36:36 PM PDT 24 Aug 19 04:36:37 PM PDT 24 22546914 ps
T1061 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2397562574 Aug 19 04:36:56 PM PDT 24 Aug 19 04:36:56 PM PDT 24 31596082 ps
T1062 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.376220761 Aug 19 04:36:52 PM PDT 24 Aug 19 04:36:54 PM PDT 24 50449819 ps
T101 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1682185528 Aug 19 04:36:34 PM PDT 24 Aug 19 04:36:37 PM PDT 24 80241102 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3371757613 Aug 19 04:36:36 PM PDT 24 Aug 19 04:36:49 PM PDT 24 950406362 ps
T98 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3061834211 Aug 19 04:36:19 PM PDT 24 Aug 19 04:36:27 PM PDT 24 436806195 ps
T1064 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4280320770 Aug 19 04:36:30 PM PDT 24 Aug 19 04:36:47 PM PDT 24 1116753002 ps
T1065 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2991756952 Aug 19 04:36:56 PM PDT 24 Aug 19 04:37:10 PM PDT 24 1838156127 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3379214029 Aug 19 04:36:51 PM PDT 24 Aug 19 04:36:57 PM PDT 24 489008229 ps
T1067 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.884842870 Aug 19 04:36:50 PM PDT 24 Aug 19 04:36:50 PM PDT 24 25267436 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1909229359 Aug 19 04:36:35 PM PDT 24 Aug 19 04:36:37 PM PDT 24 100480812 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2156955107 Aug 19 04:36:50 PM PDT 24 Aug 19 04:36:52 PM PDT 24 163506216 ps
T1070 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3663288938 Aug 19 04:36:58 PM PDT 24 Aug 19 04:36:59 PM PDT 24 14863800 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3372935568 Aug 19 04:36:30 PM PDT 24 Aug 19 04:36:50 PM PDT 24 3301472158 ps
T1072 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3414685431 Aug 19 04:36:36 PM PDT 24 Aug 19 04:36:37 PM PDT 24 40068879 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3435615908 Aug 19 04:36:58 PM PDT 24 Aug 19 04:37:00 PM PDT 24 111293445 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.269978993 Aug 19 04:36:27 PM PDT 24 Aug 19 04:36:30 PM PDT 24 247986837 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3927744235 Aug 19 04:36:46 PM PDT 24 Aug 19 04:36:47 PM PDT 24 19020527 ps
T1076 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4260963007 Aug 19 04:36:28 PM PDT 24 Aug 19 04:36:29 PM PDT 24 41698337 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1389721479 Aug 19 04:36:22 PM PDT 24 Aug 19 04:36:46 PM PDT 24 1254394966 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2941319166 Aug 19 04:36:52 PM PDT 24 Aug 19 04:36:53 PM PDT 24 11811869 ps
T1079 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1274188861 Aug 19 04:36:51 PM PDT 24 Aug 19 04:36:58 PM PDT 24 71880688 ps
T1080 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2271828387 Aug 19 04:36:35 PM PDT 24 Aug 19 04:36:36 PM PDT 24 255660736 ps
T1081 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1747702554 Aug 19 04:36:47 PM PDT 24 Aug 19 04:36:51 PM PDT 24 441715673 ps
T1082 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.989347594 Aug 19 04:36:45 PM PDT 24 Aug 19 04:36:46 PM PDT 24 20305638 ps
T1083 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2396171663 Aug 19 04:36:17 PM PDT 24 Aug 19 04:36:20 PM PDT 24 117703552 ps
T1084 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.596980096 Aug 19 04:36:49 PM PDT 24 Aug 19 04:36:52 PM PDT 24 349566752 ps
T103 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3963185569 Aug 19 04:36:20 PM PDT 24 Aug 19 04:36:25 PM PDT 24 641556333 ps
T1085 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.307710450 Aug 19 04:36:42 PM PDT 24 Aug 19 04:36:42 PM PDT 24 59054904 ps
T1086 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3834209268 Aug 19 04:36:58 PM PDT 24 Aug 19 04:37:00 PM PDT 24 48416081 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1817253517 Aug 19 04:36:42 PM PDT 24 Aug 19 04:36:43 PM PDT 24 128255460 ps
T1088 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1984028785 Aug 19 04:36:57 PM PDT 24 Aug 19 04:36:59 PM PDT 24 28718888 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2958339392 Aug 19 04:36:45 PM PDT 24 Aug 19 04:36:46 PM PDT 24 34811353 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.255102726 Aug 19 04:36:53 PM PDT 24 Aug 19 04:37:01 PM PDT 24 426616064 ps
T1091 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2014118560 Aug 19 04:37:00 PM PDT 24 Aug 19 04:37:01 PM PDT 24 118538840 ps
T1092 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1944994743 Aug 19 04:37:00 PM PDT 24 Aug 19 04:37:03 PM PDT 24 129542169 ps
T1093 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1755413978 Aug 19 04:36:41 PM PDT 24 Aug 19 04:36:42 PM PDT 24 14521195 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3038171530 Aug 19 04:36:53 PM PDT 24 Aug 19 04:36:55 PM PDT 24 68993841 ps
T1095 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3165272183 Aug 19 04:36:41 PM PDT 24 Aug 19 04:36:42 PM PDT 24 42553116 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3864162540 Aug 19 04:36:37 PM PDT 24 Aug 19 04:36:40 PM PDT 24 46121309 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4221557930 Aug 19 04:36:23 PM PDT 24 Aug 19 04:36:26 PM PDT 24 252388686 ps
T1098 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1521691623 Aug 19 04:36:19 PM PDT 24 Aug 19 04:36:25 PM PDT 24 99978096 ps
T1099 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1410447316 Aug 19 04:36:42 PM PDT 24 Aug 19 04:36:44 PM PDT 24 153887737 ps
T1100 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.667306805 Aug 19 04:37:03 PM PDT 24 Aug 19 04:37:11 PM PDT 24 455603885 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3720638512 Aug 19 04:36:22 PM PDT 24 Aug 19 04:36:23 PM PDT 24 386836360 ps
T1102 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1491730739 Aug 19 04:36:49 PM PDT 24 Aug 19 04:36:53 PM PDT 24 543905349 ps
T1103 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2976760173 Aug 19 04:36:50 PM PDT 24 Aug 19 04:36:54 PM PDT 24 132016409 ps
T1104 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.880834735 Aug 19 04:36:40 PM PDT 24 Aug 19 04:36:43 PM PDT 24 46206074 ps
T150 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2144613842 Aug 19 04:36:27 PM PDT 24 Aug 19 04:36:31 PM PDT 24 225824221 ps
T1105 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.632200301 Aug 19 04:37:04 PM PDT 24 Aug 19 04:37:13 PM PDT 24 1347128652 ps
T1106 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2354119392 Aug 19 04:36:47 PM PDT 24 Aug 19 04:36:49 PM PDT 24 95864347 ps
T1107 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1016028953 Aug 19 04:36:28 PM PDT 24 Aug 19 04:36:54 PM PDT 24 3688905872 ps
T1108 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.193938342 Aug 19 04:36:50 PM PDT 24 Aug 19 04:36:51 PM PDT 24 14080208 ps
T1109 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1584713477 Aug 19 04:36:46 PM PDT 24 Aug 19 04:36:53 PM PDT 24 109842087 ps
T1110 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2858550123 Aug 19 04:36:37 PM PDT 24 Aug 19 04:36:38 PM PDT 24 14000635 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.317529168 Aug 19 04:36:38 PM PDT 24 Aug 19 04:36:40 PM PDT 24 58514672 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.915723569 Aug 19 04:36:51 PM PDT 24 Aug 19 04:36:53 PM PDT 24 107728376 ps
T1113 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4129578596 Aug 19 04:36:31 PM PDT 24 Aug 19 04:36:32 PM PDT 24 18656374 ps
T1114 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.857771038 Aug 19 04:36:36 PM PDT 24 Aug 19 04:36:37 PM PDT 24 50780400 ps
T1115 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4172740712 Aug 19 04:36:33 PM PDT 24 Aug 19 04:36:34 PM PDT 24 16607843 ps
T1116 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3592235525 Aug 19 04:36:17 PM PDT 24 Aug 19 04:36:20 PM PDT 24 157507557 ps
T1117 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1423672980 Aug 19 04:36:38 PM PDT 24 Aug 19 04:36:39 PM PDT 24 14832294 ps
T1118 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1471649549 Aug 19 04:36:45 PM PDT 24 Aug 19 04:36:58 PM PDT 24 708933025 ps
T1119 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1397785906 Aug 19 04:36:42 PM PDT 24 Aug 19 04:36:43 PM PDT 24 78728393 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1313349528 Aug 19 04:36:39 PM PDT 24 Aug 19 04:36:43 PM PDT 24 67173027 ps
T1121 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1032718913 Aug 19 04:36:28 PM PDT 24 Aug 19 04:36:29 PM PDT 24 28614164 ps
T1122 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1345824595 Aug 19 04:36:56 PM PDT 24 Aug 19 04:37:00 PM PDT 24 133997775 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1823113514 Aug 19 04:36:33 PM PDT 24 Aug 19 04:36:34 PM PDT 24 15352431 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1693530256 Aug 19 04:36:39 PM PDT 24 Aug 19 04:36:40 PM PDT 24 17686089 ps
T1125 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2220147337 Aug 19 04:36:34 PM PDT 24 Aug 19 04:36:37 PM PDT 24 166822911 ps
T1126 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2635597243 Aug 19 04:36:41 PM PDT 24 Aug 19 04:36:41 PM PDT 24 37094398 ps
T154 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3730842099 Aug 19 04:36:41 PM PDT 24 Aug 19 04:36:55 PM PDT 24 537906526 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1372278636 Aug 19 04:36:19 PM PDT 24 Aug 19 04:36:26 PM PDT 24 886212143 ps
T1128 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2764411527 Aug 19 04:36:38 PM PDT 24 Aug 19 04:36:39 PM PDT 24 28786715 ps
T1129 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.996154967 Aug 19 04:36:29 PM PDT 24 Aug 19 04:36:30 PM PDT 24 44590425 ps
T1130 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3969259475 Aug 19 04:36:39 PM PDT 24 Aug 19 04:36:46 PM PDT 24 113805949 ps

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2355396570
Short name T9
Test name
Test status
Simulation time 1940194969 ps
CPU time 16.86 seconds
Started Aug 19 05:45:34 PM PDT 24
Finished Aug 19 05:45:51 PM PDT 24
Peak memory 235280 kb
Host smart-44a233f2-f396-4f7f-9091-fa620da8cef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355396570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2355396570
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3518800453
Short name T16
Test name
Test status
Simulation time 97771153188 ps
CPU time 601.15 seconds
Started Aug 19 05:45:11 PM PDT 24
Finished Aug 19 05:55:13 PM PDT 24
Peak memory 274812 kb
Host smart-01fbf19e-09e1-4e86-93d8-cd513c706c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518800453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3518800453
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1035684347
Short name T17
Test name
Test status
Simulation time 15258433801 ps
CPU time 204.66 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:47:55 PM PDT 24
Peak memory 280192 kb
Host smart-e05391af-b0e6-4992-b940-edce7d2d3621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035684347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1035684347
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.147574383
Short name T87
Test name
Test status
Simulation time 8969750289 ps
CPU time 16.21 seconds
Started Aug 19 04:36:45 PM PDT 24
Finished Aug 19 04:37:02 PM PDT 24
Peak memory 223460 kb
Host smart-4bd209e5-0ed6-494b-a949-90b7a31e6ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147574383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.147574383
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1727631574
Short name T26
Test name
Test status
Simulation time 46571674445 ps
CPU time 428.83 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:50:23 PM PDT 24
Peak memory 274860 kb
Host smart-4a1ff34f-6f39-49a9-9f1c-25f55ea31b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727631574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1727631574
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3435882848
Short name T51
Test name
Test status
Simulation time 18257835 ps
CPU time 0.78 seconds
Started Aug 19 05:42:36 PM PDT 24
Finished Aug 19 05:42:37 PM PDT 24
Peak memory 216876 kb
Host smart-c4917c28-5ef2-40cf-a54e-5b3c22829bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435882848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3435882848
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4211136477
Short name T18
Test name
Test status
Simulation time 14558939670 ps
CPU time 190.87 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:47:26 PM PDT 24
Peak memory 261256 kb
Host smart-bb633455-b307-4f87-b318-5fdab5f15e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211136477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4211136477
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2213929255
Short name T15
Test name
Test status
Simulation time 28570336332 ps
CPU time 319.26 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 269072 kb
Host smart-7b5bd9fd-5270-42ed-8eca-0e9d6b3453b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213929255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2213929255
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3159360566
Short name T86
Test name
Test status
Simulation time 169732309 ps
CPU time 5.65 seconds
Started Aug 19 04:36:18 PM PDT 24
Finished Aug 19 04:36:24 PM PDT 24
Peak memory 215416 kb
Host smart-4b390c9e-2789-4903-b586-cd16113df66a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159360566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
159360566
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1896120589
Short name T10
Test name
Test status
Simulation time 305737434 ps
CPU time 3.9 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:44:07 PM PDT 24
Peak memory 224176 kb
Host smart-1e9a810a-79cf-4519-95ad-977d7b3a01c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1896120589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1896120589
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2251536548
Short name T192
Test name
Test status
Simulation time 44956511514 ps
CPU time 329.6 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:48:33 PM PDT 24
Peak memory 269540 kb
Host smart-84230ac5-acd9-4144-ad8b-226aef3545fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251536548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2251536548
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1492629342
Short name T44
Test name
Test status
Simulation time 47696051 ps
CPU time 0.77 seconds
Started Aug 19 05:42:41 PM PDT 24
Finished Aug 19 05:42:42 PM PDT 24
Peak memory 206632 kb
Host smart-7e79f4cc-b084-44b7-bf9d-2ec7ef3f51b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492629342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
492629342
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.906086389
Short name T43
Test name
Test status
Simulation time 69312342652 ps
CPU time 411.52 seconds
Started Aug 19 05:43:26 PM PDT 24
Finished Aug 19 05:50:18 PM PDT 24
Peak memory 267144 kb
Host smart-982d62e2-1368-4ec3-8d25-1a6ef20c016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906086389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.906086389
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4209196634
Short name T168
Test name
Test status
Simulation time 146223313006 ps
CPU time 285.82 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:48:50 PM PDT 24
Peak memory 257888 kb
Host smart-12f6f41a-3e69-4272-8b98-f20dbbc9ffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209196634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4209196634
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.475109959
Short name T22
Test name
Test status
Simulation time 23847352476 ps
CPU time 132.63 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:47:09 PM PDT 24
Peak memory 274688 kb
Host smart-28207461-b8ed-48e9-bf59-a0e9a7a1edfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475109959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.475109959
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3614438383
Short name T71
Test name
Test status
Simulation time 79736962 ps
CPU time 1.2 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 206892 kb
Host smart-c578d830-0d0c-4311-b88c-6356d119f22d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614438383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3614438383
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1375878460
Short name T142
Test name
Test status
Simulation time 600690994135 ps
CPU time 548.71 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:52:26 PM PDT 24
Peak memory 267512 kb
Host smart-64147067-668e-4ce7-aaf5-55f6dd14fadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375878460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1375878460
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1431072065
Short name T30
Test name
Test status
Simulation time 204813368429 ps
CPU time 419.22 seconds
Started Aug 19 05:44:38 PM PDT 24
Finished Aug 19 05:51:37 PM PDT 24
Peak memory 257796 kb
Host smart-4b08124b-d75e-42e8-868a-4598526d4dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431072065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1431072065
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3030313470
Short name T589
Test name
Test status
Simulation time 191098710348 ps
CPU time 347.63 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:50:07 PM PDT 24
Peak memory 255716 kb
Host smart-7e55c2e4-6a8f-461c-9217-ace53851a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030313470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3030313470
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3881622103
Short name T53
Test name
Test status
Simulation time 345409421 ps
CPU time 1.22 seconds
Started Aug 19 05:42:38 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 237220 kb
Host smart-ec78b0e3-f684-4465-8d35-a0a02e9c5e6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881622103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3881622103
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2524729110
Short name T11
Test name
Test status
Simulation time 23126404917 ps
CPU time 160.16 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:47:28 PM PDT 24
Peak memory 250164 kb
Host smart-0c2ba5c3-03ad-4cb5-94aa-00b22360ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524729110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2524729110
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2676806004
Short name T38
Test name
Test status
Simulation time 91578667928 ps
CPU time 873.12 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:59:22 PM PDT 24
Peak memory 274548 kb
Host smart-bf70df29-1556-4fdb-9fd9-63f21ae6a460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676806004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2676806004
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3025231449
Short name T126
Test name
Test status
Simulation time 4549883283 ps
CPU time 111.41 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:47:29 PM PDT 24
Peak memory 250288 kb
Host smart-59c502c1-ed64-42cb-8a97-2ae366b08044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025231449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3025231449
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2782315497
Short name T62
Test name
Test status
Simulation time 11532515087 ps
CPU time 51.91 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:44:39 PM PDT 24
Peak memory 235008 kb
Host smart-984b1e23-79d7-435f-ae8d-7fc12b243586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782315497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2782315497
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1690886465
Short name T67
Test name
Test status
Simulation time 156583290518 ps
CPU time 420.15 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:51:04 PM PDT 24
Peak memory 251316 kb
Host smart-0de8f53d-d408-46c0-b25a-2245fdc1a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690886465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1690886465
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3934935706
Short name T273
Test name
Test status
Simulation time 83790483910 ps
CPU time 308.42 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:48:36 PM PDT 24
Peak memory 255056 kb
Host smart-b1b265da-886d-4133-8b3e-77390079c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934935706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3934935706
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2485266911
Short name T104
Test name
Test status
Simulation time 621517647 ps
CPU time 18.41 seconds
Started Aug 19 04:37:11 PM PDT 24
Finished Aug 19 04:37:30 PM PDT 24
Peak memory 215200 kb
Host smart-40dbdea2-3c83-47a0-bb54-86856f5ab7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485266911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2485266911
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3942640981
Short name T259
Test name
Test status
Simulation time 158509028889 ps
CPU time 296.14 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:48:11 PM PDT 24
Peak memory 266140 kb
Host smart-11589a54-9e16-4aaa-8263-f644b9a8d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942640981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3942640981
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3163248287
Short name T675
Test name
Test status
Simulation time 273938069014 ps
CPU time 619.24 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 282948 kb
Host smart-fb6044a6-5832-41ff-97bd-c6415ebb34d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163248287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3163248287
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.528301648
Short name T791
Test name
Test status
Simulation time 25139926622 ps
CPU time 109.28 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:46:48 PM PDT 24
Peak memory 250136 kb
Host smart-36e85316-7370-44a9-b52b-f2bbf91ccb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528301648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.528301648
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2098582279
Short name T83
Test name
Test status
Simulation time 4888541258 ps
CPU time 44.98 seconds
Started Aug 19 05:42:41 PM PDT 24
Finished Aug 19 05:43:26 PM PDT 24
Peak memory 250128 kb
Host smart-fe0ea884-f624-4490-a9e7-95fcd6a0279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098582279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2098582279
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4252067418
Short name T90
Test name
Test status
Simulation time 234356974 ps
CPU time 3.41 seconds
Started Aug 19 04:36:18 PM PDT 24
Finished Aug 19 04:36:22 PM PDT 24
Peak memory 215404 kb
Host smart-ad72bf5c-9b94-4f93-9f96-6f3e3302e34c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252067418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
252067418
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.616555572
Short name T181
Test name
Test status
Simulation time 85475657887 ps
CPU time 132.39 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:45:59 PM PDT 24
Peak memory 239736 kb
Host smart-aad72a55-e90e-42aa-9690-528d424db1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616555572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.616555572
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.908527358
Short name T69
Test name
Test status
Simulation time 14319797824 ps
CPU time 109.27 seconds
Started Aug 19 05:44:34 PM PDT 24
Finished Aug 19 05:46:24 PM PDT 24
Peak memory 264064 kb
Host smart-1d62363e-c46e-4c24-99fa-e1f0f11d688a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908527358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.908527358
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1351252951
Short name T206
Test name
Test status
Simulation time 17294430331 ps
CPU time 63.4 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:45:52 PM PDT 24
Peak memory 250116 kb
Host smart-344d6755-55b0-47c6-ab50-7b41f6d368da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351252951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1351252951
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.862576644
Short name T37
Test name
Test status
Simulation time 16355621056 ps
CPU time 37.14 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 236704 kb
Host smart-da46e560-de38-4f8e-9d0c-89584fdff1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862576644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
862576644
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.510259247
Short name T153
Test name
Test status
Simulation time 3202210657 ps
CPU time 22.21 seconds
Started Aug 19 04:36:37 PM PDT 24
Finished Aug 19 04:37:00 PM PDT 24
Peak memory 215292 kb
Host smart-4dee234e-937a-4c77-beb7-596238453867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510259247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.510259247
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2391269693
Short name T105
Test name
Test status
Simulation time 3001830687 ps
CPU time 15.71 seconds
Started Aug 19 04:36:32 PM PDT 24
Finished Aug 19 04:36:47 PM PDT 24
Peak memory 217392 kb
Host smart-cc719eac-0844-4b7d-a901-743bed7b1f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391269693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2391269693
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2891233034
Short name T314
Test name
Test status
Simulation time 1633144816 ps
CPU time 3.31 seconds
Started Aug 19 05:43:13 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 217284 kb
Host smart-92a67268-d895-46bc-afcf-b1702a3ef1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891233034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2891233034
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4079187030
Short name T64
Test name
Test status
Simulation time 10525167334 ps
CPU time 70.88 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:44:57 PM PDT 24
Peak memory 261836 kb
Host smart-c4f8f4e7-f2c5-486a-b3e6-3163a88b40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079187030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4079187030
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1733386182
Short name T984
Test name
Test status
Simulation time 55308079349 ps
CPU time 502.31 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:52:25 PM PDT 24
Peak memory 284020 kb
Host smart-e4a5894c-ab8a-47fb-a13f-a4fe0eded1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733386182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1733386182
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3278198141
Short name T968
Test name
Test status
Simulation time 15205313929 ps
CPU time 97.08 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:47:16 PM PDT 24
Peak memory 267496 kb
Host smart-8df5665c-c553-4012-a5f3-925d61bd1469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278198141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3278198141
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3963185569
Short name T103
Test name
Test status
Simulation time 641556333 ps
CPU time 3.93 seconds
Started Aug 19 04:36:20 PM PDT 24
Finished Aug 19 04:36:25 PM PDT 24
Peak memory 216324 kb
Host smart-6fa8695d-c1e2-426f-ae80-43990495615e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963185569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
963185569
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.605551678
Short name T117
Test name
Test status
Simulation time 1226695717 ps
CPU time 14.17 seconds
Started Aug 19 04:36:30 PM PDT 24
Finished Aug 19 04:36:45 PM PDT 24
Peak memory 216184 kb
Host smart-34a808ab-36f1-4d01-a4f5-dda180920720
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605551678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.605551678
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1389721479
Short name T1077
Test name
Test status
Simulation time 1254394966 ps
CPU time 24.26 seconds
Started Aug 19 04:36:22 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 206892 kb
Host smart-66575992-5354-4f9d-9128-228be0e73575
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389721479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1389721479
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2040577750
Short name T74
Test name
Test status
Simulation time 49200823 ps
CPU time 1.49 seconds
Started Aug 19 04:36:40 PM PDT 24
Finished Aug 19 04:36:41 PM PDT 24
Peak memory 206944 kb
Host smart-be35893a-8854-467a-b6b7-c0377f15ed42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040577750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2040577750
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3592235525
Short name T1116
Test name
Test status
Simulation time 157507557 ps
CPU time 3.55 seconds
Started Aug 19 04:36:17 PM PDT 24
Finished Aug 19 04:36:20 PM PDT 24
Peak memory 218532 kb
Host smart-ac2ebfe8-727a-465d-a6aa-e571d1c2839c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592235525 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3592235525
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.956048325
Short name T1057
Test name
Test status
Simulation time 19514334 ps
CPU time 1.32 seconds
Started Aug 19 04:36:24 PM PDT 24
Finished Aug 19 04:36:26 PM PDT 24
Peak memory 206944 kb
Host smart-a7f34186-be8b-4c61-b403-0a7efb8aa169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956048325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.956048325
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2600677565
Short name T1042
Test name
Test status
Simulation time 16898061 ps
CPU time 0.68 seconds
Started Aug 19 04:36:43 PM PDT 24
Finished Aug 19 04:36:44 PM PDT 24
Peak memory 204112 kb
Host smart-444edfc4-de27-4d14-b9f2-c275bcea5d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600677565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
600677565
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3038171530
Short name T1094
Test name
Test status
Simulation time 68993841 ps
CPU time 2.2 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:36:55 PM PDT 24
Peak memory 215204 kb
Host smart-ff98b620-6002-4c35-9422-76b51dfcc085
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038171530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3038171530
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3416673353
Short name T1013
Test name
Test status
Simulation time 22610731 ps
CPU time 0.68 seconds
Started Aug 19 04:36:24 PM PDT 24
Finished Aug 19 04:36:25 PM PDT 24
Peak memory 203556 kb
Host smart-cc8f5315-722a-4b64-836d-d943616bd46f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416673353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3416673353
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3423267939
Short name T132
Test name
Test status
Simulation time 50047247 ps
CPU time 1.7 seconds
Started Aug 19 04:36:17 PM PDT 24
Finished Aug 19 04:36:19 PM PDT 24
Peak memory 206852 kb
Host smart-95e61ecc-b036-40cc-8f0e-e3fee25067cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423267939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3423267939
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3372935568
Short name T1071
Test name
Test status
Simulation time 3301472158 ps
CPU time 19.94 seconds
Started Aug 19 04:36:30 PM PDT 24
Finished Aug 19 04:36:50 PM PDT 24
Peak memory 215620 kb
Host smart-79af4ac6-fdcf-4d6b-a15d-2bd87a9998e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372935568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3372935568
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3462809731
Short name T115
Test name
Test status
Simulation time 4328950177 ps
CPU time 22.45 seconds
Started Aug 19 04:36:16 PM PDT 24
Finished Aug 19 04:36:39 PM PDT 24
Peak memory 215256 kb
Host smart-82ce63ee-e081-4b07-a10e-ef51b83cf897
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462809731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3462809731
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3371757613
Short name T1063
Test name
Test status
Simulation time 950406362 ps
CPU time 12.98 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:49 PM PDT 24
Peak memory 215076 kb
Host smart-ad044551-b3b7-4232-8636-75a3e07a9a09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371757613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3371757613
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3392225600
Short name T73
Test name
Test status
Simulation time 73608978 ps
CPU time 1.1 seconds
Started Aug 19 04:36:33 PM PDT 24
Finished Aug 19 04:36:34 PM PDT 24
Peak memory 206864 kb
Host smart-77b1a3a5-a6c4-4ef4-8369-af0513df36f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392225600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3392225600
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2396171663
Short name T1083
Test name
Test status
Simulation time 117703552 ps
CPU time 2.91 seconds
Started Aug 19 04:36:17 PM PDT 24
Finished Aug 19 04:36:20 PM PDT 24
Peak memory 217860 kb
Host smart-1b44cd24-8bc2-4454-bf5e-4c892cc1266f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396171663 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2396171663
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.183322833
Short name T107
Test name
Test status
Simulation time 478447771 ps
CPU time 2.46 seconds
Started Aug 19 04:37:08 PM PDT 24
Finished Aug 19 04:37:15 PM PDT 24
Peak memory 215112 kb
Host smart-afad9b4c-35a8-4368-a383-b829f6304dac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183322833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.183322833
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.795484243
Short name T1014
Test name
Test status
Simulation time 56362511 ps
CPU time 0.74 seconds
Started Aug 19 04:36:43 PM PDT 24
Finished Aug 19 04:36:44 PM PDT 24
Peak memory 204084 kb
Host smart-2adcb3c6-cd1a-49d7-ba82-72552ac0af1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795484243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.795484243
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1210945750
Short name T113
Test name
Test status
Simulation time 117238956 ps
CPU time 1.86 seconds
Started Aug 19 04:36:29 PM PDT 24
Finished Aug 19 04:36:31 PM PDT 24
Peak memory 215168 kb
Host smart-cf2105da-2cbb-4b1a-8f72-1197dd1a419b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210945750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1210945750
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3409351056
Short name T1051
Test name
Test status
Simulation time 29009566 ps
CPU time 0.68 seconds
Started Aug 19 04:36:34 PM PDT 24
Finished Aug 19 04:36:35 PM PDT 24
Peak memory 203972 kb
Host smart-5c4ec123-f7a0-4c10-b6aa-8d51d581157c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409351056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3409351056
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1506395178
Short name T1023
Test name
Test status
Simulation time 1710978396 ps
CPU time 3.06 seconds
Started Aug 19 04:36:45 PM PDT 24
Finished Aug 19 04:36:48 PM PDT 24
Peak memory 215112 kb
Host smart-ee18f862-e511-4f36-a2d0-4cf671526fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506395178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1506395178
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1313349528
Short name T1120
Test name
Test status
Simulation time 67173027 ps
CPU time 3.95 seconds
Started Aug 19 04:36:39 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 216416 kb
Host smart-5c663ba6-44af-4b05-8b02-33c101c0c413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313349528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
313349528
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2855842971
Short name T139
Test name
Test status
Simulation time 2189257994 ps
CPU time 7.61 seconds
Started Aug 19 04:36:32 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 216508 kb
Host smart-904fd4a8-1a27-453d-83ce-85e39f329a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855842971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2855842971
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2821302817
Short name T106
Test name
Test status
Simulation time 74000742 ps
CPU time 3.39 seconds
Started Aug 19 04:36:24 PM PDT 24
Finished Aug 19 04:36:27 PM PDT 24
Peak memory 217048 kb
Host smart-7d082731-12a0-4e06-831f-7f4e8852fdf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821302817 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2821302817
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2710505283
Short name T114
Test name
Test status
Simulation time 736474523 ps
CPU time 1.94 seconds
Started Aug 19 04:36:20 PM PDT 24
Finished Aug 19 04:36:22 PM PDT 24
Peak memory 215184 kb
Host smart-9476a46f-9dc1-43b6-a2a8-583e90da2766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710505283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2710505283
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1397785906
Short name T1119
Test name
Test status
Simulation time 78728393 ps
CPU time 0.74 seconds
Started Aug 19 04:36:42 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 203804 kb
Host smart-f78a5fcc-f690-49e7-86c6-5dad4abac61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397785906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1397785906
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2339049919
Short name T1050
Test name
Test status
Simulation time 442305297 ps
CPU time 3.02 seconds
Started Aug 19 04:36:59 PM PDT 24
Finished Aug 19 04:37:02 PM PDT 24
Peak memory 215196 kb
Host smart-a2609c8d-67e7-499a-ba5a-33ec1bd7dcab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339049919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2339049919
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1944994743
Short name T1092
Test name
Test status
Simulation time 129542169 ps
CPU time 3.29 seconds
Started Aug 19 04:37:00 PM PDT 24
Finished Aug 19 04:37:03 PM PDT 24
Peak memory 215460 kb
Host smart-171949d3-ab3b-4fee-be14-d90c9385c320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944994743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1944994743
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4280320770
Short name T1064
Test name
Test status
Simulation time 1116753002 ps
CPU time 17.3 seconds
Started Aug 19 04:36:30 PM PDT 24
Finished Aug 19 04:36:47 PM PDT 24
Peak memory 215308 kb
Host smart-0cc5bf87-da0d-4035-ad89-10ec14753100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280320770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4280320770
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.411928861
Short name T85
Test name
Test status
Simulation time 507731728 ps
CPU time 3.04 seconds
Started Aug 19 04:36:43 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 216692 kb
Host smart-cda5f1ba-d75f-4efc-ae58-420ad9c09780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411928861 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.411928861
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3406950717
Short name T1043
Test name
Test status
Simulation time 21324205 ps
CPU time 1.17 seconds
Started Aug 19 04:36:31 PM PDT 24
Finished Aug 19 04:36:32 PM PDT 24
Peak memory 206928 kb
Host smart-de7fac65-d646-4c7a-8657-e5627b3088df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406950717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3406950717
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2941319166
Short name T1078
Test name
Test status
Simulation time 11811869 ps
CPU time 0.71 seconds
Started Aug 19 04:36:52 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 203768 kb
Host smart-1f47b94d-a450-40ee-aea6-1eb965a8f104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941319166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2941319166
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1410447316
Short name T1099
Test name
Test status
Simulation time 153887737 ps
CPU time 2.62 seconds
Started Aug 19 04:36:42 PM PDT 24
Finished Aug 19 04:36:44 PM PDT 24
Peak memory 215176 kb
Host smart-153972c4-682b-4d97-90f7-e3f8f12970e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410447316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1410447316
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4171088295
Short name T49
Test name
Test status
Simulation time 219740890 ps
CPU time 3.37 seconds
Started Aug 19 04:36:23 PM PDT 24
Finished Aug 19 04:36:26 PM PDT 24
Peak memory 215360 kb
Host smart-9af584d3-b2a0-4c0b-b99a-88ef9a66b4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171088295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4171088295
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.393129936
Short name T156
Test name
Test status
Simulation time 2829898565 ps
CPU time 19.28 seconds
Started Aug 19 04:36:23 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 215244 kb
Host smart-95a382e3-4eaa-48b4-9cac-a1d926eec081
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393129936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.393129936
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1736337975
Short name T94
Test name
Test status
Simulation time 102013679 ps
CPU time 2.61 seconds
Started Aug 19 04:36:38 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 217452 kb
Host smart-aecab897-8c9c-4d36-ae61-54c11c11ff75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736337975 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1736337975
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1088112341
Short name T1045
Test name
Test status
Simulation time 343166306 ps
CPU time 2.38 seconds
Started Aug 19 04:36:49 PM PDT 24
Finished Aug 19 04:36:52 PM PDT 24
Peak memory 215096 kb
Host smart-7f60539a-3132-441c-b3d5-8dea343f2a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088112341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1088112341
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2626112181
Short name T1022
Test name
Test status
Simulation time 11397207 ps
CPU time 0.71 seconds
Started Aug 19 04:36:59 PM PDT 24
Finished Aug 19 04:37:00 PM PDT 24
Peak memory 204120 kb
Host smart-e71828a4-231c-40de-9f79-3e9b784d3db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626112181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2626112181
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3167546770
Short name T1015
Test name
Test status
Simulation time 142677171 ps
CPU time 1.84 seconds
Started Aug 19 04:36:38 PM PDT 24
Finished Aug 19 04:36:39 PM PDT 24
Peak memory 215112 kb
Host smart-4b3243da-d3d1-4e3d-91b6-4679cc1895a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167546770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3167546770
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1310828355
Short name T102
Test name
Test status
Simulation time 510677396 ps
CPU time 2.06 seconds
Started Aug 19 04:36:47 PM PDT 24
Finished Aug 19 04:36:49 PM PDT 24
Peak memory 215468 kb
Host smart-43f72ad4-46b1-4e45-ac59-d58944498e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310828355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1310828355
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1274188861
Short name T1079
Test name
Test status
Simulation time 71880688 ps
CPU time 1.54 seconds
Started Aug 19 04:36:51 PM PDT 24
Finished Aug 19 04:36:58 PM PDT 24
Peak memory 215176 kb
Host smart-620eed7e-6a99-4688-af20-eab39635c489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274188861 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1274188861
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3834209268
Short name T1086
Test name
Test status
Simulation time 48416081 ps
CPU time 1.41 seconds
Started Aug 19 04:36:58 PM PDT 24
Finished Aug 19 04:37:00 PM PDT 24
Peak memory 215092 kb
Host smart-2285381c-e8fb-4c32-9c68-b3561f832d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834209268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3834209268
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2858550123
Short name T1110
Test name
Test status
Simulation time 14000635 ps
CPU time 0.71 seconds
Started Aug 19 04:36:37 PM PDT 24
Finished Aug 19 04:36:38 PM PDT 24
Peak memory 203804 kb
Host smart-09bea0c7-47a6-4722-a90c-40bc25741440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858550123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2858550123
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1963705184
Short name T140
Test name
Test status
Simulation time 429313600 ps
CPU time 1.9 seconds
Started Aug 19 04:36:38 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 206804 kb
Host smart-15c368ad-492b-4f5d-a4ad-7a4472655cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963705184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1963705184
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2976760173
Short name T1103
Test name
Test status
Simulation time 132016409 ps
CPU time 3.78 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 215324 kb
Host smart-bbc0089b-2b24-4e7c-8454-89da5ec8cb6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976760173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2976760173
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1471649549
Short name T1118
Test name
Test status
Simulation time 708933025 ps
CPU time 12.68 seconds
Started Aug 19 04:36:45 PM PDT 24
Finished Aug 19 04:36:58 PM PDT 24
Peak memory 215264 kb
Host smart-70c4a2c7-9e20-446c-9b7a-b2cbe057f075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471649549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1471649549
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1326979886
Short name T97
Test name
Test status
Simulation time 126197350 ps
CPU time 1.58 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:36:55 PM PDT 24
Peak memory 215160 kb
Host smart-504ddfac-dfc5-4dae-b2b8-a5669235413a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326979886 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1326979886
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1275797400
Short name T1058
Test name
Test status
Simulation time 106083371 ps
CPU time 2.55 seconds
Started Aug 19 04:36:46 PM PDT 24
Finished Aug 19 04:36:48 PM PDT 24
Peak memory 215132 kb
Host smart-70ade913-d8c6-49aa-93ef-643d01f49d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275797400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1275797400
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3117649871
Short name T1025
Test name
Test status
Simulation time 17881663 ps
CPU time 0.68 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 203800 kb
Host smart-6028fb2b-5c2f-4fb8-b3df-c488d7bb1fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117649871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3117649871
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1536319828
Short name T1034
Test name
Test status
Simulation time 722231445 ps
CPU time 4.05 seconds
Started Aug 19 04:37:03 PM PDT 24
Finished Aug 19 04:37:07 PM PDT 24
Peak memory 215092 kb
Host smart-a411a9a5-be95-4061-82cc-3639ea28b1c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536319828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1536319828
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.376220761
Short name T1062
Test name
Test status
Simulation time 50449819 ps
CPU time 1.56 seconds
Started Aug 19 04:36:52 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 215360 kb
Host smart-2601af1c-43be-44a5-b240-3897b881ee56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376220761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.376220761
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3379214029
Short name T1066
Test name
Test status
Simulation time 489008229 ps
CPU time 6.08 seconds
Started Aug 19 04:36:51 PM PDT 24
Finished Aug 19 04:36:57 PM PDT 24
Peak memory 215240 kb
Host smart-e88dd987-aab7-4812-8fd7-f5108b3ad34e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379214029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3379214029
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1491730739
Short name T1102
Test name
Test status
Simulation time 543905349 ps
CPU time 3.68 seconds
Started Aug 19 04:36:49 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 217512 kb
Host smart-803a1d4f-860f-4a12-af8a-87be741061f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491730739 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1491730739
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3927744235
Short name T1075
Test name
Test status
Simulation time 19020527 ps
CPU time 1.21 seconds
Started Aug 19 04:36:46 PM PDT 24
Finished Aug 19 04:36:47 PM PDT 24
Peak memory 215080 kb
Host smart-a0e20279-7a4d-4b37-9447-bb5aeb2b3944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927744235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3927744235
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2384078617
Short name T1006
Test name
Test status
Simulation time 41218231 ps
CPU time 0.71 seconds
Started Aug 19 04:36:45 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 204064 kb
Host smart-0bd5f110-3598-401b-9d30-1734cc50d8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384078617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2384078617
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.934955586
Short name T138
Test name
Test status
Simulation time 563927350 ps
CPU time 3.09 seconds
Started Aug 19 04:36:37 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 215096 kb
Host smart-25fb1086-174c-4b7b-a8c8-31ab346e866c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934955586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.934955586
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1682185528
Short name T101
Test name
Test status
Simulation time 80241102 ps
CPU time 2.27 seconds
Started Aug 19 04:36:34 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 216368 kb
Host smart-7e0a222b-ab03-4a39-9a9c-0bc701523890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682185528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1682185528
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1984028785
Short name T1088
Test name
Test status
Simulation time 28718888 ps
CPU time 1.81 seconds
Started Aug 19 04:36:57 PM PDT 24
Finished Aug 19 04:36:59 PM PDT 24
Peak memory 216280 kb
Host smart-a277e885-b68b-4a09-b6fc-d29eab749eef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984028785 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1984028785
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.850694547
Short name T1059
Test name
Test status
Simulation time 122345302 ps
CPU time 1.35 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:52 PM PDT 24
Peak memory 215176 kb
Host smart-59adc6bc-492e-4f6f-bf1d-e001dba79ab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850694547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.850694547
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3261773764
Short name T1055
Test name
Test status
Simulation time 12979410 ps
CPU time 0.71 seconds
Started Aug 19 04:36:24 PM PDT 24
Finished Aug 19 04:36:25 PM PDT 24
Peak memory 203824 kb
Host smart-e155f1ae-8334-4262-beed-d8cc18a17e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261773764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3261773764
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2673640388
Short name T131
Test name
Test status
Simulation time 315103153 ps
CPU time 4.25 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 215068 kb
Host smart-7647010b-13aa-4ed2-b147-12478d8b2c31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673640388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2673640388
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.596980096
Short name T1084
Test name
Test status
Simulation time 349566752 ps
CPU time 3.67 seconds
Started Aug 19 04:36:49 PM PDT 24
Finished Aug 19 04:36:52 PM PDT 24
Peak memory 215276 kb
Host smart-0e01f795-e64d-44e2-bb39-4923b9428e27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596980096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.596980096
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4104879750
Short name T152
Test name
Test status
Simulation time 332425835 ps
CPU time 18.41 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:37:09 PM PDT 24
Peak memory 215172 kb
Host smart-9c1709f2-3f42-4149-96eb-2aefc96634fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104879750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4104879750
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3438954008
Short name T100
Test name
Test status
Simulation time 74519348 ps
CPU time 2.51 seconds
Started Aug 19 04:36:51 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 217352 kb
Host smart-ad873ac7-0440-48fd-a90f-33aad507841b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438954008 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3438954008
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1909229359
Short name T1068
Test name
Test status
Simulation time 100480812 ps
CPU time 2.45 seconds
Started Aug 19 04:36:35 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 215124 kb
Host smart-c39baae0-0324-4f48-8957-0a7e23f07abe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909229359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1909229359
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2271828387
Short name T1080
Test name
Test status
Simulation time 255660736 ps
CPU time 0.73 seconds
Started Aug 19 04:36:35 PM PDT 24
Finished Aug 19 04:36:36 PM PDT 24
Peak memory 203824 kb
Host smart-b935dc4d-5f85-4bf2-a182-87dd8c2d30c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271828387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2271828387
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3555780784
Short name T1019
Test name
Test status
Simulation time 83569143 ps
CPU time 2.64 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:39 PM PDT 24
Peak memory 215104 kb
Host smart-06cc87cb-3ceb-4381-8d64-9dd7326c15ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555780784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3555780784
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2343365038
Short name T93
Test name
Test status
Simulation time 102413197 ps
CPU time 3.16 seconds
Started Aug 19 04:36:19 PM PDT 24
Finished Aug 19 04:36:23 PM PDT 24
Peak memory 215456 kb
Host smart-95eb2c68-edec-4caa-9e24-f88976641ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343365038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2343365038
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3969259475
Short name T1130
Test name
Test status
Simulation time 113805949 ps
CPU time 6.81 seconds
Started Aug 19 04:36:39 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 215180 kb
Host smart-f9e0cff1-79f6-4fab-94e8-00517acee501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969259475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3969259475
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.775866342
Short name T141
Test name
Test status
Simulation time 111524441 ps
CPU time 2.94 seconds
Started Aug 19 04:36:40 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 218108 kb
Host smart-40f9ca26-14ce-460e-8e87-23f59ab0f388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775866342 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.775866342
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2386054307
Short name T1047
Test name
Test status
Simulation time 726739615 ps
CPU time 1.42 seconds
Started Aug 19 04:36:51 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 206832 kb
Host smart-665c9715-a94b-4e02-94ab-e17f19f26448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386054307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2386054307
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1561905403
Short name T1037
Test name
Test status
Simulation time 13092477 ps
CPU time 0.72 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 203780 kb
Host smart-219b587e-ae37-46eb-a23a-659251d3cd7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561905403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1561905403
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.915723569
Short name T1112
Test name
Test status
Simulation time 107728376 ps
CPU time 1.71 seconds
Started Aug 19 04:36:51 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 215148 kb
Host smart-6d03fc2d-295a-4d51-83c8-50caec6fc88c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915723569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.915723569
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.880834735
Short name T1104
Test name
Test status
Simulation time 46206074 ps
CPU time 2.78 seconds
Started Aug 19 04:36:40 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 215316 kb
Host smart-1c8573c5-fe10-4c2c-9405-55a20e0cbbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880834735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.880834735
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.632200301
Short name T1105
Test name
Test status
Simulation time 1347128652 ps
CPU time 8 seconds
Started Aug 19 04:37:04 PM PDT 24
Finished Aug 19 04:37:13 PM PDT 24
Peak memory 215260 kb
Host smart-2344c3c9-6ccd-494b-843e-c02a6378e632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632200301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.632200301
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.557981337
Short name T89
Test name
Test status
Simulation time 523364203 ps
CPU time 3.45 seconds
Started Aug 19 04:36:58 PM PDT 24
Finished Aug 19 04:37:02 PM PDT 24
Peak memory 217772 kb
Host smart-2d6ea1ba-7435-40f4-9d3b-77d4126401b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557981337 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.557981337
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1170308110
Short name T110
Test name
Test status
Simulation time 101369715 ps
CPU time 1.8 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 215160 kb
Host smart-90f9d9a3-31a5-4e9d-b949-660582a6f1f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170308110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1170308110
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1262668857
Short name T1020
Test name
Test status
Simulation time 20914383 ps
CPU time 0.73 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 203836 kb
Host smart-fa360dac-367f-4bee-b4de-c13625791619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262668857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1262668857
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1608735061
Short name T1012
Test name
Test status
Simulation time 45829198 ps
CPU time 2.68 seconds
Started Aug 19 04:37:08 PM PDT 24
Finished Aug 19 04:37:11 PM PDT 24
Peak memory 215084 kb
Host smart-5b8ec5be-f788-4ac9-96fb-45a1290fa72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608735061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1608735061
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1345824595
Short name T1122
Test name
Test status
Simulation time 133997775 ps
CPU time 3.75 seconds
Started Aug 19 04:36:56 PM PDT 24
Finished Aug 19 04:37:00 PM PDT 24
Peak memory 215372 kb
Host smart-7d66f00b-1e60-44f4-bc1a-e9ef57141fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345824595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1345824595
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2991756952
Short name T1065
Test name
Test status
Simulation time 1838156127 ps
CPU time 8.46 seconds
Started Aug 19 04:36:56 PM PDT 24
Finished Aug 19 04:37:10 PM PDT 24
Peak memory 215284 kb
Host smart-003e6014-c4ee-40cc-a7d6-f79a73038dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991756952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2991756952
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.255102726
Short name T1090
Test name
Test status
Simulation time 426616064 ps
CPU time 7.17 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:37:01 PM PDT 24
Peak memory 206860 kb
Host smart-5665da10-9dc6-4858-8b3a-47c6d158aac1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255102726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.255102726
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.357444360
Short name T1052
Test name
Test status
Simulation time 524132293 ps
CPU time 33.51 seconds
Started Aug 19 04:36:57 PM PDT 24
Finished Aug 19 04:37:31 PM PDT 24
Peak memory 215092 kb
Host smart-ed37428e-ca07-49fa-9fcb-56fe43c2d6d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357444360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.357444360
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1637972199
Short name T1040
Test name
Test status
Simulation time 67804400 ps
CPU time 0.97 seconds
Started Aug 19 04:37:06 PM PDT 24
Finished Aug 19 04:37:07 PM PDT 24
Peak memory 206712 kb
Host smart-9a1ee8f5-99e6-4cdd-b3d9-93f99bdea7a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637972199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1637972199
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3864162540
Short name T1096
Test name
Test status
Simulation time 46121309 ps
CPU time 2.83 seconds
Started Aug 19 04:36:37 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 217100 kb
Host smart-1a510ab0-c4b7-4a67-ad2c-4de3e619e790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864162540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3864162540
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1817253517
Short name T1087
Test name
Test status
Simulation time 128255460 ps
CPU time 1.23 seconds
Started Aug 19 04:36:42 PM PDT 24
Finished Aug 19 04:36:43 PM PDT 24
Peak memory 215116 kb
Host smart-45791fc5-3855-41b5-83e0-c0386bd38116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817253517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
817253517
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1071995976
Short name T1054
Test name
Test status
Simulation time 33318729 ps
CPU time 0.68 seconds
Started Aug 19 04:36:24 PM PDT 24
Finished Aug 19 04:36:29 PM PDT 24
Peak memory 203788 kb
Host smart-e611fbc1-e162-4b64-b556-5f51636fdb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071995976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
071995976
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3720638512
Short name T1101
Test name
Test status
Simulation time 386836360 ps
CPU time 1.28 seconds
Started Aug 19 04:36:22 PM PDT 24
Finished Aug 19 04:36:23 PM PDT 24
Peak memory 215176 kb
Host smart-59b42d64-6ddd-41be-bac7-bc6b70bd7f74
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720638512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3720638512
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2799980972
Short name T1029
Test name
Test status
Simulation time 21341612 ps
CPU time 0.64 seconds
Started Aug 19 04:36:23 PM PDT 24
Finished Aug 19 04:36:24 PM PDT 24
Peak memory 203644 kb
Host smart-84d97bd7-2fe3-4cdd-9ba7-9758a45caf89
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799980972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2799980972
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3915617697
Short name T1049
Test name
Test status
Simulation time 169775252 ps
CPU time 2.79 seconds
Started Aug 19 04:36:55 PM PDT 24
Finished Aug 19 04:36:58 PM PDT 24
Peak memory 215092 kb
Host smart-61cc63e4-9245-4861-b90d-825353a4af5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915617697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3915617697
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1673018708
Short name T95
Test name
Test status
Simulation time 202478437 ps
CPU time 5.69 seconds
Started Aug 19 04:36:27 PM PDT 24
Finished Aug 19 04:36:33 PM PDT 24
Peak memory 215368 kb
Host smart-83700c62-ea0d-4053-9afe-908cc977fc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673018708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
673018708
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2838502797
Short name T155
Test name
Test status
Simulation time 1324724520 ps
CPU time 15.41 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:37:09 PM PDT 24
Peak memory 215788 kb
Host smart-51a7dc1a-9597-4d38-89a4-6c3311966de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838502797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2838502797
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.989347594
Short name T1082
Test name
Test status
Simulation time 20305638 ps
CPU time 0.73 seconds
Started Aug 19 04:36:45 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 204084 kb
Host smart-299aa87a-e4ea-402e-a5cf-e348be1a57af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989347594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.989347594
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.387768350
Short name T1027
Test name
Test status
Simulation time 13544875 ps
CPU time 0.74 seconds
Started Aug 19 04:36:48 PM PDT 24
Finished Aug 19 04:36:49 PM PDT 24
Peak memory 203780 kb
Host smart-39661f72-eccf-446f-8a66-70b406ebb33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387768350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.387768350
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.193938342
Short name T1108
Test name
Test status
Simulation time 14080208 ps
CPU time 0.69 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:51 PM PDT 24
Peak memory 203792 kb
Host smart-cc5cdc6e-dca5-44b8-9546-61d7178f92ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193938342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.193938342
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1341567218
Short name T1018
Test name
Test status
Simulation time 37066312 ps
CPU time 0.71 seconds
Started Aug 19 04:36:57 PM PDT 24
Finished Aug 19 04:36:57 PM PDT 24
Peak memory 203812 kb
Host smart-244f51f3-6ec1-4f9e-98d0-4d13a1b45c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341567218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1341567218
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4021135888
Short name T1028
Test name
Test status
Simulation time 136480630 ps
CPU time 0.71 seconds
Started Aug 19 04:36:51 PM PDT 24
Finished Aug 19 04:36:52 PM PDT 24
Peak memory 203772 kb
Host smart-582f78d5-dc4b-4f8b-92f2-6440eeaae7ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021135888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4021135888
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.857771038
Short name T1114
Test name
Test status
Simulation time 50780400 ps
CPU time 0.77 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 203800 kb
Host smart-988173cf-b0fe-48cd-aa4a-e5e8657066dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857771038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.857771038
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2014118560
Short name T1091
Test name
Test status
Simulation time 118538840 ps
CPU time 0.74 seconds
Started Aug 19 04:37:00 PM PDT 24
Finished Aug 19 04:37:01 PM PDT 24
Peak memory 203796 kb
Host smart-6e30ed59-8443-4c72-97ec-4e86b5b6f9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014118560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2014118560
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3414685431
Short name T1072
Test name
Test status
Simulation time 40068879 ps
CPU time 0.7 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 203804 kb
Host smart-f9b62464-11df-4840-b0ca-72372159ab9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414685431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3414685431
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.677168028
Short name T1010
Test name
Test status
Simulation time 16087774 ps
CPU time 0.75 seconds
Started Aug 19 04:37:01 PM PDT 24
Finished Aug 19 04:37:02 PM PDT 24
Peak memory 204068 kb
Host smart-44b21f9f-6275-4906-8a97-be5310ce3a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677168028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.677168028
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.772219405
Short name T1007
Test name
Test status
Simulation time 12614592 ps
CPU time 0.71 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:51 PM PDT 24
Peak memory 204092 kb
Host smart-2a24a19d-bff7-431b-8e6d-8974c6f59945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772219405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.772219405
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.793713682
Short name T111
Test name
Test status
Simulation time 3639457925 ps
CPU time 23.73 seconds
Started Aug 19 04:36:30 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 215228 kb
Host smart-5de0e573-5888-43eb-a63c-8295c7b3b7f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793713682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.793713682
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3639401313
Short name T116
Test name
Test status
Simulation time 7206619953 ps
CPU time 36.34 seconds
Started Aug 19 04:37:04 PM PDT 24
Finished Aug 19 04:37:40 PM PDT 24
Peak memory 206928 kb
Host smart-dc821487-0777-434e-bbd2-08ed7a11b4c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639401313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3639401313
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3155112865
Short name T72
Test name
Test status
Simulation time 186766852 ps
CPU time 1.44 seconds
Started Aug 19 04:36:30 PM PDT 24
Finished Aug 19 04:36:31 PM PDT 24
Peak memory 207028 kb
Host smart-96ccad29-55e0-442f-adad-735fb6181d9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155112865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3155112865
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3457832410
Short name T48
Test name
Test status
Simulation time 155357907 ps
CPU time 1.85 seconds
Started Aug 19 04:36:35 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 215264 kb
Host smart-e986370d-b3f5-4e94-aa1a-c1e8619c7f72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457832410 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3457832410
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2220147337
Short name T1125
Test name
Test status
Simulation time 166822911 ps
CPU time 2.24 seconds
Started Aug 19 04:36:34 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 215112 kb
Host smart-c66ccf71-c15f-4c01-a906-2fc51f3fc7f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220147337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
220147337
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.307710450
Short name T1085
Test name
Test status
Simulation time 59054904 ps
CPU time 0.73 seconds
Started Aug 19 04:36:42 PM PDT 24
Finished Aug 19 04:36:42 PM PDT 24
Peak memory 203792 kb
Host smart-ac78a8f4-61f1-4961-84ac-01215cd66e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307710450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.307710450
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4067982345
Short name T1060
Test name
Test status
Simulation time 22546914 ps
CPU time 1.41 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:37 PM PDT 24
Peak memory 215084 kb
Host smart-597da85a-fa23-4da3-8329-de130b8ddad4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067982345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4067982345
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3291933098
Short name T1017
Test name
Test status
Simulation time 67345303 ps
CPU time 0.68 seconds
Started Aug 19 04:36:17 PM PDT 24
Finished Aug 19 04:36:18 PM PDT 24
Peak memory 203628 kb
Host smart-888945a9-97e0-4d60-ac28-6d233f7e0d8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291933098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3291933098
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.269978993
Short name T1074
Test name
Test status
Simulation time 247986837 ps
CPU time 2.73 seconds
Started Aug 19 04:36:27 PM PDT 24
Finished Aug 19 04:36:30 PM PDT 24
Peak memory 215112 kb
Host smart-18a72353-2a67-4979-805b-d473e96ae905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269978993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.269978993
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1372278636
Short name T1127
Test name
Test status
Simulation time 886212143 ps
CPU time 4.18 seconds
Started Aug 19 04:36:19 PM PDT 24
Finished Aug 19 04:36:26 PM PDT 24
Peak memory 215332 kb
Host smart-42f4dd38-8db5-4e3a-b7b6-f30900a6db01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372278636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
372278636
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.996154967
Short name T1129
Test name
Test status
Simulation time 44590425 ps
CPU time 0.69 seconds
Started Aug 19 04:36:29 PM PDT 24
Finished Aug 19 04:36:30 PM PDT 24
Peak memory 204092 kb
Host smart-2054eb9f-9383-4181-8009-c78e23a11e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996154967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.996154967
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2276691499
Short name T1041
Test name
Test status
Simulation time 66870408 ps
CPU time 0.73 seconds
Started Aug 19 04:36:52 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 203820 kb
Host smart-af315a4c-2af9-4031-bfca-bda2529558e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276691499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2276691499
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1755413978
Short name T1093
Test name
Test status
Simulation time 14521195 ps
CPU time 0.77 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:42 PM PDT 24
Peak memory 203752 kb
Host smart-9521c882-c846-47d0-9784-564cbd8dda87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755413978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1755413978
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.344875512
Short name T1009
Test name
Test status
Simulation time 39515859 ps
CPU time 0.7 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:42 PM PDT 24
Peak memory 204088 kb
Host smart-8d7d6ccb-7ca6-4932-8859-500a368fc12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344875512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.344875512
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.79415136
Short name T1048
Test name
Test status
Simulation time 51388102 ps
CPU time 0.74 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:37:11 PM PDT 24
Peak memory 203820 kb
Host smart-17a92919-2d75-4c29-9a5f-a5380b149b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79415136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.79415136
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.358969265
Short name T1016
Test name
Test status
Simulation time 23250490 ps
CPU time 0.68 seconds
Started Aug 19 04:36:34 PM PDT 24
Finished Aug 19 04:36:34 PM PDT 24
Peak memory 203808 kb
Host smart-fcdc9149-a862-4c57-b6fb-f9bb126f2c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358969265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.358969265
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1423672980
Short name T1117
Test name
Test status
Simulation time 14832294 ps
CPU time 0.69 seconds
Started Aug 19 04:36:38 PM PDT 24
Finished Aug 19 04:36:39 PM PDT 24
Peak memory 204108 kb
Host smart-04a13aa8-8ff4-40d0-a3da-a9ac30866ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423672980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1423672980
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1974895290
Short name T1036
Test name
Test status
Simulation time 31574196 ps
CPU time 0.71 seconds
Started Aug 19 04:36:53 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 204104 kb
Host smart-5bcb8fc6-a7ae-4472-98e6-3d43f96aaedc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974895290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1974895290
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4129578596
Short name T1113
Test name
Test status
Simulation time 18656374 ps
CPU time 0.68 seconds
Started Aug 19 04:36:31 PM PDT 24
Finished Aug 19 04:36:32 PM PDT 24
Peak memory 203828 kb
Host smart-18553022-ddd1-4a78-aff0-8a5e4a2322e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129578596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4129578596
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2635597243
Short name T1126
Test name
Test status
Simulation time 37094398 ps
CPU time 0.7 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:41 PM PDT 24
Peak memory 203792 kb
Host smart-8325fc51-91b7-43f5-b989-354683fc7cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635597243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2635597243
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.667306805
Short name T1100
Test name
Test status
Simulation time 455603885 ps
CPU time 7.62 seconds
Started Aug 19 04:37:03 PM PDT 24
Finished Aug 19 04:37:11 PM PDT 24
Peak memory 206884 kb
Host smart-724237b8-249a-443a-b544-15aff5cadd36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667306805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.667306805
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1016028953
Short name T1107
Test name
Test status
Simulation time 3688905872 ps
CPU time 25.38 seconds
Started Aug 19 04:36:28 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 207052 kb
Host smart-2b0fa95c-00d5-4656-827c-547f7b88ebd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016028953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1016028953
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.317529168
Short name T1111
Test name
Test status
Simulation time 58514672 ps
CPU time 1.74 seconds
Started Aug 19 04:36:38 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 216364 kb
Host smart-79c05e63-bea2-4077-b0ed-7811a92619e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317529168 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.317529168
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1851436788
Short name T1038
Test name
Test status
Simulation time 36511556 ps
CPU time 2.51 seconds
Started Aug 19 04:36:42 PM PDT 24
Finished Aug 19 04:36:45 PM PDT 24
Peak memory 215136 kb
Host smart-c035f651-ec60-4e8c-9786-ed0288c966f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851436788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
851436788
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1823113514
Short name T1123
Test name
Test status
Simulation time 15352431 ps
CPU time 0.76 seconds
Started Aug 19 04:36:33 PM PDT 24
Finished Aug 19 04:36:34 PM PDT 24
Peak memory 203820 kb
Host smart-63e63c0d-330f-4cc9-99fa-f789a016706d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823113514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
823113514
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.291600503
Short name T109
Test name
Test status
Simulation time 203092909 ps
CPU time 1.79 seconds
Started Aug 19 04:36:22 PM PDT 24
Finished Aug 19 04:36:24 PM PDT 24
Peak memory 215076 kb
Host smart-433a4b7c-3b8f-4798-b618-4bc49fcacd1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291600503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.291600503
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1693530256
Short name T1124
Test name
Test status
Simulation time 17686089 ps
CPU time 0.66 seconds
Started Aug 19 04:36:39 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 203936 kb
Host smart-c7a69da2-7a3b-4ff4-8637-b7e9e98db550
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693530256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1693530256
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2600090222
Short name T1026
Test name
Test status
Simulation time 2982424092 ps
CPU time 3.81 seconds
Started Aug 19 04:36:28 PM PDT 24
Finished Aug 19 04:36:32 PM PDT 24
Peak memory 215192 kb
Host smart-b70635d6-1a08-4849-9fcb-c08e0bc742f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600090222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2600090222
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3730842099
Short name T154
Test name
Test status
Simulation time 537906526 ps
CPU time 13.58 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:55 PM PDT 24
Peak memory 215480 kb
Host smart-e757621e-5913-4f47-a6af-b2318d06385c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730842099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3730842099
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2900377653
Short name T1008
Test name
Test status
Simulation time 39443309 ps
CPU time 0.78 seconds
Started Aug 19 04:37:04 PM PDT 24
Finished Aug 19 04:37:05 PM PDT 24
Peak memory 203808 kb
Host smart-719e948a-7f7d-487f-ba0c-d4c8fead706f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900377653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2900377653
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2397562574
Short name T1061
Test name
Test status
Simulation time 31596082 ps
CPU time 0.71 seconds
Started Aug 19 04:36:56 PM PDT 24
Finished Aug 19 04:36:56 PM PDT 24
Peak memory 203788 kb
Host smart-1bcc8863-3859-4dda-b0bf-0c16ada51026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397562574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2397562574
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3150442315
Short name T1039
Test name
Test status
Simulation time 22462857 ps
CPU time 0.72 seconds
Started Aug 19 04:36:46 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 203680 kb
Host smart-e2d261a0-c4ea-4b75-8f3a-838025e691f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150442315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3150442315
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3663288938
Short name T1070
Test name
Test status
Simulation time 14863800 ps
CPU time 0.69 seconds
Started Aug 19 04:36:58 PM PDT 24
Finished Aug 19 04:36:59 PM PDT 24
Peak memory 203808 kb
Host smart-a014d64f-4ecc-4ea6-8b7d-a2fb0c3022e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663288938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3663288938
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2599738840
Short name T1011
Test name
Test status
Simulation time 208513131 ps
CPU time 0.74 seconds
Started Aug 19 04:36:57 PM PDT 24
Finished Aug 19 04:36:58 PM PDT 24
Peak memory 203768 kb
Host smart-808cb355-1fd4-44e8-a170-5623e2d76e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599738840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2599738840
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4260963007
Short name T1076
Test name
Test status
Simulation time 41698337 ps
CPU time 0.68 seconds
Started Aug 19 04:36:28 PM PDT 24
Finished Aug 19 04:36:29 PM PDT 24
Peak memory 203792 kb
Host smart-ed263001-9bba-4f2b-ac1a-adab1a1342f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260963007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4260963007
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3165272183
Short name T1095
Test name
Test status
Simulation time 42553116 ps
CPU time 0.75 seconds
Started Aug 19 04:36:41 PM PDT 24
Finished Aug 19 04:36:42 PM PDT 24
Peak memory 203788 kb
Host smart-9d00277d-1081-42d4-9b1d-aa7dcd346cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165272183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3165272183
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1123786218
Short name T1030
Test name
Test status
Simulation time 140927354 ps
CPU time 0.78 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:51 PM PDT 24
Peak memory 203804 kb
Host smart-f905286d-f3a8-4dcc-9015-8241a9c38263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123786218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1123786218
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2097450132
Short name T1021
Test name
Test status
Simulation time 11115427 ps
CPU time 0.74 seconds
Started Aug 19 04:36:44 PM PDT 24
Finished Aug 19 04:36:45 PM PDT 24
Peak memory 203788 kb
Host smart-417cf608-b8b6-43a7-b64a-f2245c44b3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097450132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2097450132
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.884842870
Short name T1067
Test name
Test status
Simulation time 25267436 ps
CPU time 0.69 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:50 PM PDT 24
Peak memory 203752 kb
Host smart-3b9f67b4-0edf-4054-b97f-559427d733fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884842870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.884842870
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.804380964
Short name T1033
Test name
Test status
Simulation time 81682039 ps
CPU time 1.72 seconds
Started Aug 19 04:36:37 PM PDT 24
Finished Aug 19 04:36:39 PM PDT 24
Peak memory 215284 kb
Host smart-d7a194b4-9528-428c-bd31-b026b533c829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804380964 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.804380964
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1984720451
Short name T1044
Test name
Test status
Simulation time 31948250 ps
CPU time 1.81 seconds
Started Aug 19 04:36:40 PM PDT 24
Finished Aug 19 04:36:42 PM PDT 24
Peak memory 206904 kb
Host smart-14c91e87-acec-4294-9cda-2a7b4f36835d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984720451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
984720451
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2958339392
Short name T1089
Test name
Test status
Simulation time 34811353 ps
CPU time 0.83 seconds
Started Aug 19 04:36:45 PM PDT 24
Finished Aug 19 04:36:46 PM PDT 24
Peak memory 203784 kb
Host smart-376a3e89-b2af-4fa8-8815-c3811d05bf44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958339392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
958339392
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1521691623
Short name T1098
Test name
Test status
Simulation time 99978096 ps
CPU time 2.62 seconds
Started Aug 19 04:36:19 PM PDT 24
Finished Aug 19 04:36:25 PM PDT 24
Peak memory 215080 kb
Host smart-711653f7-523d-48af-a9bf-ba2335e23184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521691623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1521691623
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2144613842
Short name T150
Test name
Test status
Simulation time 225824221 ps
CPU time 3.63 seconds
Started Aug 19 04:36:27 PM PDT 24
Finished Aug 19 04:36:31 PM PDT 24
Peak memory 215424 kb
Host smart-11f7153c-7074-44bc-8a78-b9678e6030d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144613842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
144613842
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1584713477
Short name T1109
Test name
Test status
Simulation time 109842087 ps
CPU time 6.76 seconds
Started Aug 19 04:36:46 PM PDT 24
Finished Aug 19 04:36:53 PM PDT 24
Peak memory 215240 kb
Host smart-0c8889c8-ef52-4182-bd62-dee4d5521af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584713477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1584713477
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4221557930
Short name T1097
Test name
Test status
Simulation time 252388686 ps
CPU time 3.38 seconds
Started Aug 19 04:36:23 PM PDT 24
Finished Aug 19 04:36:26 PM PDT 24
Peak memory 217620 kb
Host smart-4753a649-56ec-49f6-94aa-3d40e9df8f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221557930 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4221557930
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3712060719
Short name T108
Test name
Test status
Simulation time 65796087 ps
CPU time 1.78 seconds
Started Aug 19 04:36:23 PM PDT 24
Finished Aug 19 04:36:25 PM PDT 24
Peak memory 215184 kb
Host smart-6fe950df-d7a9-44a4-8c6b-f8f9d102d767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712060719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
712060719
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2764411527
Short name T1128
Test name
Test status
Simulation time 28786715 ps
CPU time 0.76 seconds
Started Aug 19 04:36:38 PM PDT 24
Finished Aug 19 04:36:39 PM PDT 24
Peak memory 203816 kb
Host smart-f714745b-cb80-4b7c-9098-e26357846715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764411527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
764411527
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1959544775
Short name T1032
Test name
Test status
Simulation time 99060924 ps
CPU time 1.67 seconds
Started Aug 19 04:36:42 PM PDT 24
Finished Aug 19 04:36:44 PM PDT 24
Peak memory 206976 kb
Host smart-97d857b8-cb39-4f4d-be88-484d4cf22b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959544775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1959544775
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1062081745
Short name T1031
Test name
Test status
Simulation time 56323660 ps
CPU time 3.89 seconds
Started Aug 19 04:36:52 PM PDT 24
Finished Aug 19 04:36:56 PM PDT 24
Peak memory 217556 kb
Host smart-4a632a14-f803-4806-a448-3e473aca8820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062081745 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1062081745
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.150903023
Short name T112
Test name
Test status
Simulation time 115692846 ps
CPU time 2.73 seconds
Started Aug 19 04:36:58 PM PDT 24
Finished Aug 19 04:37:01 PM PDT 24
Peak memory 215144 kb
Host smart-ec96b41e-d0cb-4313-975e-8a2cec028e04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150903023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.150903023
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4172740712
Short name T1115
Test name
Test status
Simulation time 16607843 ps
CPU time 0.76 seconds
Started Aug 19 04:36:33 PM PDT 24
Finished Aug 19 04:36:34 PM PDT 24
Peak memory 203808 kb
Host smart-0afb2c5f-6751-4aa8-9a4d-78c0e95925fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172740712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
172740712
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1747702554
Short name T1081
Test name
Test status
Simulation time 441715673 ps
CPU time 4.28 seconds
Started Aug 19 04:36:47 PM PDT 24
Finished Aug 19 04:36:51 PM PDT 24
Peak memory 215084 kb
Host smart-8576ec40-d67d-4886-a5a7-951b2d01296c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747702554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1747702554
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1032718913
Short name T1121
Test name
Test status
Simulation time 28614164 ps
CPU time 1.64 seconds
Started Aug 19 04:36:28 PM PDT 24
Finished Aug 19 04:36:29 PM PDT 24
Peak memory 215432 kb
Host smart-a713b708-7d6b-40c4-97bc-2140afdd0bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032718913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
032718913
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3281854274
Short name T88
Test name
Test status
Simulation time 628219683 ps
CPU time 7.57 seconds
Started Aug 19 04:36:46 PM PDT 24
Finished Aug 19 04:36:54 PM PDT 24
Peak memory 215732 kb
Host smart-258a539b-7125-407e-bc51-8d181e506d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281854274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3281854274
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3435615908
Short name T1073
Test name
Test status
Simulation time 111293445 ps
CPU time 1.73 seconds
Started Aug 19 04:36:58 PM PDT 24
Finished Aug 19 04:37:00 PM PDT 24
Peak memory 215188 kb
Host smart-310f7003-2c0a-4004-a10a-82889eec5946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435615908 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3435615908
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2156955107
Short name T1069
Test name
Test status
Simulation time 163506216 ps
CPU time 1.39 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:36:52 PM PDT 24
Peak memory 207024 kb
Host smart-47e4cccb-969f-4427-aacf-ad9b8b19583a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156955107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
156955107
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.993408129
Short name T1024
Test name
Test status
Simulation time 39655056 ps
CPU time 0.71 seconds
Started Aug 19 04:36:57 PM PDT 24
Finished Aug 19 04:36:58 PM PDT 24
Peak memory 203788 kb
Host smart-a3c2fed7-d959-4961-89c7-eff460a80251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993408129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.993408129
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1309798236
Short name T1056
Test name
Test status
Simulation time 158208197 ps
CPU time 2.85 seconds
Started Aug 19 04:36:52 PM PDT 24
Finished Aug 19 04:36:55 PM PDT 24
Peak memory 215092 kb
Host smart-72f16e15-d986-4d8e-98d2-792f4d22ae87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309798236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1309798236
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3061834211
Short name T98
Test name
Test status
Simulation time 436806195 ps
CPU time 4.82 seconds
Started Aug 19 04:36:19 PM PDT 24
Finished Aug 19 04:36:27 PM PDT 24
Peak memory 215332 kb
Host smart-d169cd82-a8d3-4e8e-8d5c-2babc18a1382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061834211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
061834211
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4265734825
Short name T50
Test name
Test status
Simulation time 1856285704 ps
CPU time 18.09 seconds
Started Aug 19 04:37:01 PM PDT 24
Finished Aug 19 04:37:19 PM PDT 24
Peak memory 215584 kb
Host smart-0eddd1aa-5796-4e85-8130-3a3aeb205b71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265734825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4265734825
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2354119392
Short name T1106
Test name
Test status
Simulation time 95864347 ps
CPU time 1.62 seconds
Started Aug 19 04:36:47 PM PDT 24
Finished Aug 19 04:36:49 PM PDT 24
Peak memory 215328 kb
Host smart-a6e374d2-058e-438a-b775-098ccf8eb1c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354119392 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2354119392
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3441724571
Short name T1053
Test name
Test status
Simulation time 62906863 ps
CPU time 1.99 seconds
Started Aug 19 04:36:49 PM PDT 24
Finished Aug 19 04:36:51 PM PDT 24
Peak memory 206908 kb
Host smart-6f066916-2851-49de-bc28-ed1a9bba6924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441724571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
441724571
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1196311784
Short name T1035
Test name
Test status
Simulation time 298374802 ps
CPU time 0.73 seconds
Started Aug 19 04:36:56 PM PDT 24
Finished Aug 19 04:36:57 PM PDT 24
Peak memory 203812 kb
Host smart-cead261a-f373-4b3e-84f4-6b122960f449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196311784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
196311784
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3513990240
Short name T1046
Test name
Test status
Simulation time 29870365 ps
CPU time 1.81 seconds
Started Aug 19 04:36:58 PM PDT 24
Finished Aug 19 04:37:00 PM PDT 24
Peak memory 215100 kb
Host smart-fd200e04-3a09-4714-8038-996fff68bb54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513990240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3513990240
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.198916303
Short name T99
Test name
Test status
Simulation time 270616175 ps
CPU time 3.33 seconds
Started Aug 19 04:36:36 PM PDT 24
Finished Aug 19 04:36:40 PM PDT 24
Peak memory 215376 kb
Host smart-a1df029f-a0d0-4a38-bb92-17e3f9a119e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198916303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.198916303
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2706160627
Short name T151
Test name
Test status
Simulation time 563853061 ps
CPU time 14.33 seconds
Started Aug 19 04:36:50 PM PDT 24
Finished Aug 19 04:37:05 PM PDT 24
Peak memory 215284 kb
Host smart-e50dda0a-9710-4a8b-8548-777f499209df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706160627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2706160627
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2953562550
Short name T997
Test name
Test status
Simulation time 64188107 ps
CPU time 0.72 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:41 PM PDT 24
Peak memory 205752 kb
Host smart-1b4f17ab-124e-4321-8c74-12d2b760c070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953562550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
953562550
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3445311538
Short name T485
Test name
Test status
Simulation time 1542590608 ps
CPU time 14.77 seconds
Started Aug 19 05:42:45 PM PDT 24
Finished Aug 19 05:43:00 PM PDT 24
Peak memory 225380 kb
Host smart-3ed34d20-dbce-41d4-87ab-33ef5c8240dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445311538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3445311538
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3788499509
Short name T380
Test name
Test status
Simulation time 68777880 ps
CPU time 0.79 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:42:43 PM PDT 24
Peak memory 207484 kb
Host smart-9a0072f1-b243-499e-80a9-76654bbaefda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788499509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3788499509
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.664348541
Short name T780
Test name
Test status
Simulation time 7475287629 ps
CPU time 72.61 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:43:53 PM PDT 24
Peak memory 251184 kb
Host smart-c8b4bfd4-8c19-478c-a17c-078a37128c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664348541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.664348541
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.777997685
Short name T163
Test name
Test status
Simulation time 58481573445 ps
CPU time 94.29 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:44:18 PM PDT 24
Peak memory 258320 kb
Host smart-1b3c13fb-d697-4e90-915b-9eebceddac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777997685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.777997685
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4095365788
Short name T129
Test name
Test status
Simulation time 403993368319 ps
CPU time 930.67 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:58:12 PM PDT 24
Peak memory 274764 kb
Host smart-e527488a-02fa-47f6-8ea7-4cbb1516b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095365788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4095365788
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2421131847
Short name T538
Test name
Test status
Simulation time 208452178 ps
CPU time 4.04 seconds
Started Aug 19 05:42:39 PM PDT 24
Finished Aug 19 05:42:43 PM PDT 24
Peak memory 233600 kb
Host smart-4ccf9642-fb4a-4004-b016-bac3c16e55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421131847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2421131847
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.352148603
Short name T158
Test name
Test status
Simulation time 161622066434 ps
CPU time 195.48 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:45:55 PM PDT 24
Peak memory 251704 kb
Host smart-4cf35469-3c69-46f1-b157-aca59ebfcfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352148603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
352148603
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.513436280
Short name T700
Test name
Test status
Simulation time 408667801 ps
CPU time 6.19 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:47 PM PDT 24
Peak memory 233676 kb
Host smart-5dbe3d56-910c-425f-b0f2-4139393fd023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513436280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.513436280
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1895337127
Short name T857
Test name
Test status
Simulation time 846305398 ps
CPU time 9.74 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:42:53 PM PDT 24
Peak memory 249032 kb
Host smart-715421ce-c546-4a58-b573-d7d1162dbede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895337127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1895337127
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4274771971
Short name T752
Test name
Test status
Simulation time 1935643648 ps
CPU time 13.8 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:42:55 PM PDT 24
Peak memory 251156 kb
Host smart-fd358486-3671-4959-bc3d-c1e9ba2d1386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274771971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4274771971
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1975535309
Short name T371
Test name
Test status
Simulation time 988154190 ps
CPU time 4.18 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:42:46 PM PDT 24
Peak memory 225336 kb
Host smart-e0815f49-e129-47b2-b8c4-18b12179e612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975535309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1975535309
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3903133188
Short name T704
Test name
Test status
Simulation time 308887234 ps
CPU time 4.61 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:44 PM PDT 24
Peak memory 224032 kb
Host smart-e326f389-d0a5-4c3e-9cba-b07951f4b76a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903133188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3903133188
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.65367124
Short name T443
Test name
Test status
Simulation time 143143631918 ps
CPU time 306.86 seconds
Started Aug 19 05:42:39 PM PDT 24
Finished Aug 19 05:47:46 PM PDT 24
Peak memory 253104 kb
Host smart-f8812c34-35ce-45c9-ad5f-4f3fdb6473d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65367124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_
all.65367124
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1828284531
Short name T514
Test name
Test status
Simulation time 771855826 ps
CPU time 5.9 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:42:49 PM PDT 24
Peak memory 217192 kb
Host smart-239c6d67-79ae-48e6-8e69-26c8a448d5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828284531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1828284531
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.698200986
Short name T959
Test name
Test status
Simulation time 593536572 ps
CPU time 4.97 seconds
Started Aug 19 05:42:41 PM PDT 24
Finished Aug 19 05:42:46 PM PDT 24
Peak memory 217260 kb
Host smart-55353ca9-4f8f-4b85-8375-dcb656c9e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698200986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.698200986
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.26949101
Short name T346
Test name
Test status
Simulation time 197670326 ps
CPU time 1.58 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:42 PM PDT 24
Peak memory 217204 kb
Host smart-fe3c5f7b-0af8-4bcd-9868-7e8eecfcd285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26949101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.26949101
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1705261509
Short name T301
Test name
Test status
Simulation time 37668227 ps
CPU time 0.7 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:42:44 PM PDT 24
Peak memory 206500 kb
Host smart-e4296a2d-4fb0-45a9-a6d0-b0c60618ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705261509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1705261509
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.687250879
Short name T746
Test name
Test status
Simulation time 6653302568 ps
CPU time 12.94 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:42:56 PM PDT 24
Peak memory 233616 kb
Host smart-5d343f6d-ffda-4b5c-8f2a-60760a8a559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687250879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.687250879
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.53841701
Short name T785
Test name
Test status
Simulation time 163058834 ps
CPU time 3.34 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:42:48 PM PDT 24
Peak memory 225396 kb
Host smart-82c787fa-7de7-4efa-9648-7e1002e428e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53841701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.53841701
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2090371585
Short name T438
Test name
Test status
Simulation time 18372304 ps
CPU time 0.79 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:42:45 PM PDT 24
Peak memory 207464 kb
Host smart-c6c5a757-b0e8-4b30-b37c-81f50ed9a043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090371585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2090371585
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3293705684
Short name T335
Test name
Test status
Simulation time 33397795930 ps
CPU time 56.72 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:43:38 PM PDT 24
Peak memory 250692 kb
Host smart-c251536c-81c7-4a17-861e-1fe85f2a401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293705684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3293705684
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2332936406
Short name T347
Test name
Test status
Simulation time 4599514918 ps
CPU time 25.21 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 218604 kb
Host smart-7cdd0a4e-b6ce-4774-842d-e638eff7e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332936406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2332936406
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2439217553
Short name T694
Test name
Test status
Simulation time 5060391791 ps
CPU time 8.8 seconds
Started Aug 19 05:42:38 PM PDT 24
Finished Aug 19 05:42:47 PM PDT 24
Peak memory 218796 kb
Host smart-be6be0be-442a-41a0-9287-10a5d7a31074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439217553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2439217553
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3829955195
Short name T651
Test name
Test status
Simulation time 283360258 ps
CPU time 4 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:45 PM PDT 24
Peak memory 233548 kb
Host smart-d52bb527-ac20-44eb-b44f-712c6d24730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829955195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3829955195
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4257062415
Short name T520
Test name
Test status
Simulation time 3072326980 ps
CPU time 4.53 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:42:48 PM PDT 24
Peak memory 225468 kb
Host smart-bfd288ea-fbdd-4067-b561-ec89416eeb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257062415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4257062415
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.751359698
Short name T122
Test name
Test status
Simulation time 3834556513 ps
CPU time 26.37 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 233784 kb
Host smart-75bc5c4a-5d15-4091-8509-c05cac3fef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751359698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.751359698
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1641407069
Short name T548
Test name
Test status
Simulation time 2037375660 ps
CPU time 3.5 seconds
Started Aug 19 05:42:38 PM PDT 24
Finished Aug 19 05:42:42 PM PDT 24
Peak memory 219772 kb
Host smart-a8008cf8-8a47-4faa-905b-cffb11500486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641407069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1641407069
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2899062805
Short name T1004
Test name
Test status
Simulation time 385443372 ps
CPU time 4.45 seconds
Started Aug 19 05:42:39 PM PDT 24
Finished Aug 19 05:42:44 PM PDT 24
Peak memory 221108 kb
Host smart-bd5c033f-ac99-43d1-a8f0-b04fb37a94c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2899062805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2899062805
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.990169821
Short name T52
Test name
Test status
Simulation time 61856267 ps
CPU time 1.14 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:42:45 PM PDT 24
Peak memory 237260 kb
Host smart-b4287b21-5b09-4f86-8e6c-b4a8e251b76a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990169821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.990169821
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1658170319
Short name T171
Test name
Test status
Simulation time 476369221434 ps
CPU time 942.21 seconds
Started Aug 19 05:42:36 PM PDT 24
Finished Aug 19 05:58:18 PM PDT 24
Peak memory 257876 kb
Host smart-9f014e1a-f53c-4425-8734-545a07a66e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658170319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1658170319
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1631582996
Short name T286
Test name
Test status
Simulation time 7815270367 ps
CPU time 18.76 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:59 PM PDT 24
Peak memory 221256 kb
Host smart-fdc623d4-4f65-4e7a-a5c4-b6682871afd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631582996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1631582996
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.744520437
Short name T366
Test name
Test status
Simulation time 3665610636 ps
CPU time 12.99 seconds
Started Aug 19 05:42:43 PM PDT 24
Finished Aug 19 05:42:56 PM PDT 24
Peak memory 217384 kb
Host smart-6cf6ff34-0598-452c-a7c7-50d70fc2d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744520437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.744520437
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2657410174
Short name T400
Test name
Test status
Simulation time 105789726 ps
CPU time 0.79 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:42:43 PM PDT 24
Peak memory 206860 kb
Host smart-a5488000-6184-4572-b1f3-254c48fd7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657410174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2657410174
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4110197920
Short name T764
Test name
Test status
Simulation time 88773836 ps
CPU time 0.99 seconds
Started Aug 19 05:42:45 PM PDT 24
Finished Aug 19 05:42:46 PM PDT 24
Peak memory 207356 kb
Host smart-38af79cf-42fe-4601-82ca-3a789e215f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110197920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4110197920
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.59403764
Short name T576
Test name
Test status
Simulation time 4822390451 ps
CPU time 5.8 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:42:50 PM PDT 24
Peak memory 233400 kb
Host smart-66cb353f-1fa5-434e-b5c8-9482823f76b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59403764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.59403764
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4068245109
Short name T971
Test name
Test status
Simulation time 13144346 ps
CPU time 0.79 seconds
Started Aug 19 05:43:11 PM PDT 24
Finished Aug 19 05:43:12 PM PDT 24
Peak memory 205708 kb
Host smart-6183a883-3e8b-4c6a-b5d7-8597f15776d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068245109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4068245109
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.675744059
Short name T824
Test name
Test status
Simulation time 369418080 ps
CPU time 5.07 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:22 PM PDT 24
Peak memory 233640 kb
Host smart-c44b470a-b96f-4306-9123-aa55cec47013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675744059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.675744059
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4116831562
Short name T306
Test name
Test status
Simulation time 47359079 ps
CPU time 0.79 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 207456 kb
Host smart-7f88b429-66fd-45dd-83ba-eb3b4642a442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116831562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4116831562
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2216644108
Short name T584
Test name
Test status
Simulation time 3281101957 ps
CPU time 33.37 seconds
Started Aug 19 05:43:15 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 241992 kb
Host smart-10beaf1a-ce8e-4591-a9c6-63fb425017f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216644108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2216644108
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1314159595
Short name T629
Test name
Test status
Simulation time 23265120458 ps
CPU time 13.1 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:43:27 PM PDT 24
Peak memory 218620 kb
Host smart-ecf8c777-0dfd-4aef-9786-b0369755e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314159595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1314159595
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1883371041
Short name T454
Test name
Test status
Simulation time 1401457402 ps
CPU time 7.27 seconds
Started Aug 19 05:43:11 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 241840 kb
Host smart-a71335e0-3be5-4564-8745-bf790689cf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883371041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1883371041
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3184203643
Short name T254
Test name
Test status
Simulation time 78356985152 ps
CPU time 171.78 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:46:06 PM PDT 24
Peak memory 254612 kb
Host smart-e221cb62-2093-4af9-a093-4f6db0460e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184203643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3184203643
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1259232998
Short name T707
Test name
Test status
Simulation time 575315294 ps
CPU time 4.8 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 233640 kb
Host smart-9521c139-5390-4913-88b4-7645c7ef21c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259232998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1259232998
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4185119102
Short name T770
Test name
Test status
Simulation time 1533158885 ps
CPU time 12.78 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 233656 kb
Host smart-34e01d17-4d34-4352-af98-e206448a317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185119102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4185119102
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3073338302
Short name T797
Test name
Test status
Simulation time 861824943 ps
CPU time 7.96 seconds
Started Aug 19 05:43:12 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 233628 kb
Host smart-c3ed141b-1b85-48ab-9e27-c012062cec8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073338302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3073338302
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3039950814
Short name T204
Test name
Test status
Simulation time 32796983397 ps
CPU time 17.49 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:27 PM PDT 24
Peak memory 225540 kb
Host smart-74ab90aa-a3f5-447b-847e-d567479cd979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039950814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3039950814
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4103173849
Short name T414
Test name
Test status
Simulation time 365543369 ps
CPU time 4.42 seconds
Started Aug 19 05:43:10 PM PDT 24
Finished Aug 19 05:43:14 PM PDT 24
Peak memory 224032 kb
Host smart-d243f7cf-933f-49e0-a2a4-57f5c0a51db1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103173849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4103173849
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.848522816
Short name T5
Test name
Test status
Simulation time 701676173 ps
CPU time 2.3 seconds
Started Aug 19 05:43:11 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 217416 kb
Host smart-d2e4ebf9-6e28-4b18-a5c5-f81c82409d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848522816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.848522816
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3917708291
Short name T830
Test name
Test status
Simulation time 1723027944 ps
CPU time 4.07 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 217248 kb
Host smart-e5c38857-bd61-4668-bb9c-eb6c2a8177c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917708291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3917708291
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2721347719
Short name T1005
Test name
Test status
Simulation time 104740144 ps
CPU time 1.68 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 217244 kb
Host smart-4ab23a86-5a58-4a23-9da4-db53296cdbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721347719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2721347719
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3790730992
Short name T406
Test name
Test status
Simulation time 16600087 ps
CPU time 0.75 seconds
Started Aug 19 05:43:13 PM PDT 24
Finished Aug 19 05:43:14 PM PDT 24
Peak memory 206880 kb
Host smart-43acd328-0473-4ce6-bbc2-bb7b3531737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790730992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3790730992
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3972094527
Short name T783
Test name
Test status
Simulation time 296781779 ps
CPU time 4.9 seconds
Started Aug 19 05:43:16 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 233628 kb
Host smart-152ab52d-3711-43dd-b28f-6b4564d6ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972094527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3972094527
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1669005999
Short name T608
Test name
Test status
Simulation time 20414286 ps
CPU time 0.73 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 205696 kb
Host smart-3e0f2e0f-dc60-4f51-9212-8a01013900c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669005999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1669005999
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3158771851
Short name T905
Test name
Test status
Simulation time 516810411 ps
CPU time 7.8 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:26 PM PDT 24
Peak memory 233452 kb
Host smart-97cdb669-9cd5-40db-bf37-ce46c0568ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158771851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3158771851
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.994323805
Short name T908
Test name
Test status
Simulation time 29350193 ps
CPU time 0.75 seconds
Started Aug 19 05:43:13 PM PDT 24
Finished Aug 19 05:43:14 PM PDT 24
Peak memory 206748 kb
Host smart-7ba19de7-b59d-4b3a-a3c3-2e3a85240cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994323805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.994323805
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3743417381
Short name T828
Test name
Test status
Simulation time 14247465811 ps
CPU time 26.47 seconds
Started Aug 19 05:43:16 PM PDT 24
Finished Aug 19 05:43:43 PM PDT 24
Peak memory 225556 kb
Host smart-6b14b0f6-a9ac-4363-af74-b5bb5899270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743417381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3743417381
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.316226588
Short name T676
Test name
Test status
Simulation time 18355719580 ps
CPU time 130.54 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 240820 kb
Host smart-532f0078-f12a-4399-85dd-94e1aaf19329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316226588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.316226588
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1324848061
Short name T504
Test name
Test status
Simulation time 163639770078 ps
CPU time 335.27 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:48:52 PM PDT 24
Peak memory 266656 kb
Host smart-f0ac9a1c-d79a-41b5-b446-26ddd4c38495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324848061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1324848061
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4148419197
Short name T440
Test name
Test status
Simulation time 689348039 ps
CPU time 7.51 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:43:27 PM PDT 24
Peak memory 239156 kb
Host smart-4d83ea19-28b9-45ae-be24-21b7e2ae5ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148419197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4148419197
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1070243004
Short name T885
Test name
Test status
Simulation time 21297178047 ps
CPU time 208.15 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:46:48 PM PDT 24
Peak memory 252708 kb
Host smart-402a07d1-380d-4551-8562-c6f33be71e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070243004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1070243004
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2882244063
Short name T211
Test name
Test status
Simulation time 160061352 ps
CPU time 3.81 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 225408 kb
Host smart-10568d8e-ae27-46d7-bf94-4bc6c1655ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882244063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2882244063
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1045028400
Short name T194
Test name
Test status
Simulation time 654784856 ps
CPU time 12.4 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 233612 kb
Host smart-c685dff4-9afc-4e9a-bead-9aac5a958bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045028400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1045028400
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1849045129
Short name T507
Test name
Test status
Simulation time 5464745325 ps
CPU time 8.75 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:43:23 PM PDT 24
Peak memory 233776 kb
Host smart-db31dd50-b09f-4145-9674-120e6907f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849045129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1849045129
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3305221362
Short name T789
Test name
Test status
Simulation time 13086289504 ps
CPU time 10.92 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 235636 kb
Host smart-cb849230-079e-4201-b3d3-9931e4e7821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305221362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3305221362
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4058594677
Short name T134
Test name
Test status
Simulation time 1864217633 ps
CPU time 4.73 seconds
Started Aug 19 05:43:16 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 219800 kb
Host smart-a62a2309-a6ff-4ffb-a435-10a602ff2c65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4058594677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4058594677
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4159052512
Short name T257
Test name
Test status
Simulation time 48499649227 ps
CPU time 343.61 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:49:03 PM PDT 24
Peak memory 274776 kb
Host smart-f2735e38-628f-45f1-bf6f-19294b6dfd82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159052512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4159052512
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.17053581
Short name T515
Test name
Test status
Simulation time 7820067007 ps
CPU time 40.05 seconds
Started Aug 19 05:43:15 PM PDT 24
Finished Aug 19 05:43:55 PM PDT 24
Peak memory 217084 kb
Host smart-c24c7444-1a7e-49b3-b9a1-b0fdeab00cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17053581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.17053581
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3659280300
Short name T321
Test name
Test status
Simulation time 245002088 ps
CPU time 3.92 seconds
Started Aug 19 05:43:13 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 217252 kb
Host smart-f755d37f-f37a-47b9-9043-bccfcc9c19fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659280300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3659280300
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.285011801
Short name T374
Test name
Test status
Simulation time 326274620 ps
CPU time 0.88 seconds
Started Aug 19 05:43:13 PM PDT 24
Finished Aug 19 05:43:14 PM PDT 24
Peak memory 206892 kb
Host smart-6270f389-f24f-4efd-9801-22c868ba82f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285011801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.285011801
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.795345669
Short name T663
Test name
Test status
Simulation time 811452523 ps
CPU time 3.47 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:43:22 PM PDT 24
Peak memory 233656 kb
Host smart-dcc83e2d-d789-4a0a-adc2-52798c617273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795345669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.795345669
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3208708973
Short name T307
Test name
Test status
Simulation time 40092767 ps
CPU time 0.75 seconds
Started Aug 19 05:43:16 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 206316 kb
Host smart-66ee9e27-3d27-4493-8dd7-13963c9f12fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208708973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3208708973
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2526482871
Short name T672
Test name
Test status
Simulation time 478511543 ps
CPU time 3.65 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 233648 kb
Host smart-b11ead50-5349-4d0d-b20e-adf3519bb3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526482871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2526482871
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1649954505
Short name T402
Test name
Test status
Simulation time 30627583 ps
CPU time 0.79 seconds
Started Aug 19 05:43:16 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 207516 kb
Host smart-f0dd6692-eee4-4bc7-a540-b6033dde4d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649954505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1649954505
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.863599040
Short name T460
Test name
Test status
Simulation time 12908668909 ps
CPU time 99.39 seconds
Started Aug 19 05:43:21 PM PDT 24
Finished Aug 19 05:45:00 PM PDT 24
Peak memory 250140 kb
Host smart-4b99fbfd-5eb8-4009-9cba-58422fba8fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863599040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.863599040
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3451316175
Short name T276
Test name
Test status
Simulation time 2409285154 ps
CPU time 69.6 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:44:29 PM PDT 24
Peak memory 253356 kb
Host smart-3ffc0d63-456a-473e-a478-1253c752b7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451316175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3451316175
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1516281074
Short name T275
Test name
Test status
Simulation time 6442418765 ps
CPU time 94.03 seconds
Started Aug 19 05:43:23 PM PDT 24
Finished Aug 19 05:44:58 PM PDT 24
Peak memory 253548 kb
Host smart-a33e29d5-22a7-4126-a0ef-ccfea11f560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516281074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1516281074
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.136169354
Short name T754
Test name
Test status
Simulation time 286293831 ps
CPU time 9.99 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 235632 kb
Host smart-b3067500-e9a0-476e-8342-34ddf2071a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136169354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.136169354
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3946794801
Short name T558
Test name
Test status
Simulation time 17953608113 ps
CPU time 66.94 seconds
Started Aug 19 05:43:21 PM PDT 24
Finished Aug 19 05:44:28 PM PDT 24
Peak memory 250132 kb
Host smart-da5e7288-154c-45ea-a962-c8b22b49110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946794801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3946794801
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3132395891
Short name T522
Test name
Test status
Simulation time 63460294 ps
CPU time 2.47 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:43:22 PM PDT 24
Peak memory 227644 kb
Host smart-de1affb9-f782-47e6-8165-6ddae54ccf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132395891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3132395891
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4164037247
Short name T388
Test name
Test status
Simulation time 700215381 ps
CPU time 9.04 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 225296 kb
Host smart-84493b6b-91ec-4545-9c58-019748a1d65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164037247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4164037247
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4060389923
Short name T175
Test name
Test status
Simulation time 2177518818 ps
CPU time 4.97 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:43:25 PM PDT 24
Peak memory 233788 kb
Host smart-92dac0ee-94fa-457e-9455-2b0a1ce3434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060389923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4060389923
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2637075166
Short name T191
Test name
Test status
Simulation time 4844229443 ps
CPU time 9.2 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:43:28 PM PDT 24
Peak memory 225464 kb
Host smart-a0e3b974-42d4-42c0-8c6a-3747659af321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637075166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2637075166
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3770520573
Short name T397
Test name
Test status
Simulation time 375027970 ps
CPU time 5.49 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:23 PM PDT 24
Peak memory 219780 kb
Host smart-139ea923-31f0-4c65-a470-30e1b9882c12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770520573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3770520573
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1878813033
Short name T20
Test name
Test status
Simulation time 138879715 ps
CPU time 0.93 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 206720 kb
Host smart-4ff366cf-dd54-4c0e-9405-51413c4955cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878813033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1878813033
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2893220848
Short name T648
Test name
Test status
Simulation time 12223477 ps
CPU time 0.73 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 206912 kb
Host smart-2ed7873c-4cc0-4660-b3da-37b3ba21c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893220848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2893220848
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2792472130
Short name T503
Test name
Test status
Simulation time 1707076028 ps
CPU time 4.85 seconds
Started Aug 19 05:43:23 PM PDT 24
Finished Aug 19 05:43:28 PM PDT 24
Peak memory 217076 kb
Host smart-54b0e997-2a21-4fa7-9f0a-59252d4c3796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792472130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2792472130
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1853752428
Short name T305
Test name
Test status
Simulation time 33131161 ps
CPU time 1.54 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 217212 kb
Host smart-76285a8b-55ec-46f3-8f12-3297067cb642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853752428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1853752428
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2773777074
Short name T950
Test name
Test status
Simulation time 68766578 ps
CPU time 0.96 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 207916 kb
Host smart-7f1fb18f-2412-45f4-aecc-6b0d3f6d0583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773777074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2773777074
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.24393939
Short name T656
Test name
Test status
Simulation time 2051124889 ps
CPU time 9.77 seconds
Started Aug 19 05:43:20 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 224020 kb
Host smart-da4eb96c-1b68-43d5-b4e1-2856d8c0a547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24393939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.24393939
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4179305626
Short name T670
Test name
Test status
Simulation time 25160963 ps
CPU time 0.74 seconds
Started Aug 19 05:43:23 PM PDT 24
Finished Aug 19 05:43:23 PM PDT 24
Peak memory 205648 kb
Host smart-7662c66f-e3f5-4f41-86e8-40d1e6b17f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179305626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4179305626
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.689087253
Short name T225
Test name
Test status
Simulation time 84648391 ps
CPU time 2.37 seconds
Started Aug 19 05:43:15 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 225340 kb
Host smart-1736f028-77a2-4d9b-b46c-c63c7054cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689087253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.689087253
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1929580529
Short name T309
Test name
Test status
Simulation time 18193602 ps
CPU time 0.76 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 207404 kb
Host smart-d5d55b9f-3162-4a58-bfec-792b36ba1a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929580529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1929580529
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1569799905
Short name T727
Test name
Test status
Simulation time 52080057184 ps
CPU time 368.45 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:49:36 PM PDT 24
Peak memory 258292 kb
Host smart-a4ccf497-d7a5-448a-9871-4030545a2a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569799905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1569799905
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3526831471
Short name T795
Test name
Test status
Simulation time 3275223296 ps
CPU time 23.38 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:51 PM PDT 24
Peak memory 241888 kb
Host smart-76347a59-ab71-4b82-91cc-0a7c57764461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526831471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3526831471
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2846991567
Short name T850
Test name
Test status
Simulation time 12813673349 ps
CPU time 127.02 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:45:35 PM PDT 24
Peak memory 241064 kb
Host smart-859b9f39-ce38-4abc-9c71-6eb6484643a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846991567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2846991567
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2989155660
Short name T125
Test name
Test status
Simulation time 3154938439 ps
CPU time 51.14 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:44:10 PM PDT 24
Peak memory 233696 kb
Host smart-4ac8b0d6-0dcc-4688-9d84-52ade90c13fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989155660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2989155660
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3689376858
Short name T661
Test name
Test status
Simulation time 33937219962 ps
CPU time 78 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:44:36 PM PDT 24
Peak memory 250336 kb
Host smart-a4258222-808a-49b3-bd41-27378403c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689376858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3689376858
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.480087632
Short name T851
Test name
Test status
Simulation time 1693962190 ps
CPU time 4.71 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:23 PM PDT 24
Peak memory 225176 kb
Host smart-d7bdee5b-f0eb-448b-9f0c-7db3e25ee284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480087632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.480087632
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2207107507
Short name T918
Test name
Test status
Simulation time 9318303032 ps
CPU time 42.07 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:44:10 PM PDT 24
Peak memory 233584 kb
Host smart-39fde048-4feb-4753-baf3-621266cb0e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207107507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2207107507
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3047604129
Short name T237
Test name
Test status
Simulation time 631500931 ps
CPU time 6.19 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:24 PM PDT 24
Peak memory 225392 kb
Host smart-829919f1-5b43-4e4f-8457-30b8df0d82f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047604129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3047604129
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.354566524
Short name T166
Test name
Test status
Simulation time 18199667011 ps
CPU time 10.45 seconds
Started Aug 19 05:43:23 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 225428 kb
Host smart-2599a12a-3afb-45bd-85ea-d3d1ced753f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354566524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.354566524
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2000429628
Short name T133
Test name
Test status
Simulation time 2419699486 ps
CPU time 9.88 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:28 PM PDT 24
Peak memory 223640 kb
Host smart-8b443a4b-ed30-4bfb-ab69-4627853667db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2000429628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2000429628
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3113893061
Short name T917
Test name
Test status
Simulation time 22286878402 ps
CPU time 19.14 seconds
Started Aug 19 05:43:26 PM PDT 24
Finished Aug 19 05:43:45 PM PDT 24
Peak memory 217472 kb
Host smart-f806a1d2-c579-48d5-9508-56dd1f8f77ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113893061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3113893061
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1191029785
Short name T342
Test name
Test status
Simulation time 15352862 ps
CPU time 0.72 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 206516 kb
Host smart-2b7907ec-f03f-4251-886e-5b8187ec8475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191029785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1191029785
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1698803377
Short name T2
Test name
Test status
Simulation time 46567635 ps
CPU time 1.31 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 217220 kb
Host smart-3609cb5f-5529-4588-9cc5-5a964d138730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698803377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1698803377
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2198018550
Short name T942
Test name
Test status
Simulation time 126758091 ps
CPU time 0.87 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 207908 kb
Host smart-df53bfcf-14d6-4e7e-a8de-37140c256bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198018550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2198018550
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.540168270
Short name T221
Test name
Test status
Simulation time 1839546800 ps
CPU time 3.96 seconds
Started Aug 19 05:43:17 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 225444 kb
Host smart-f20bab91-8100-4648-8612-1200488e37de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540168270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.540168270
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2999010919
Short name T356
Test name
Test status
Simulation time 26185676 ps
CPU time 0.68 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 205752 kb
Host smart-8a6b108a-74c6-450c-9f44-4aa83349584e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999010919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2999010919
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.753557736
Short name T848
Test name
Test status
Simulation time 122506839 ps
CPU time 2.23 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:43:30 PM PDT 24
Peak memory 233636 kb
Host smart-62ddfb97-074f-4fee-b5a6-dcaa76c49a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753557736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.753557736
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2093599314
Short name T442
Test name
Test status
Simulation time 74029935 ps
CPU time 0.8 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 207472 kb
Host smart-0901ad01-b9f6-4728-9488-21932864181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093599314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2093599314
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4263922181
Short name T76
Test name
Test status
Simulation time 119019304139 ps
CPU time 76.54 seconds
Started Aug 19 05:43:26 PM PDT 24
Finished Aug 19 05:44:42 PM PDT 24
Peak memory 250256 kb
Host smart-a4c82386-677b-4435-ac65-136666eb0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263922181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4263922181
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2551330447
Short name T743
Test name
Test status
Simulation time 30643644236 ps
CPU time 120.7 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:45:28 PM PDT 24
Peak memory 256888 kb
Host smart-41e2e945-7b79-4d0c-9c33-bb02d5826e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551330447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2551330447
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2430327257
Short name T607
Test name
Test status
Simulation time 89341278 ps
CPU time 2.98 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:43:32 PM PDT 24
Peak memory 225472 kb
Host smart-ffda8daf-2600-4d45-822d-28f0edd2b059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430327257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2430327257
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.889204836
Short name T981
Test name
Test status
Simulation time 31107013600 ps
CPU time 250.56 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:47:40 PM PDT 24
Peak memory 258272 kb
Host smart-aa8eaef9-5c63-42d9-b9e8-80db179b90c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889204836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.889204836
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1004904185
Short name T650
Test name
Test status
Simulation time 658715470 ps
CPU time 3.49 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 233600 kb
Host smart-b1617f0e-900a-4296-8a98-f59ecd2a3c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004904185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1004904185
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4110765820
Short name T563
Test name
Test status
Simulation time 5292132289 ps
CPU time 13.32 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 219988 kb
Host smart-6d8d6b04-c0ac-40e0-9bc8-0d83c914ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110765820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4110765820
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1673972556
Short name T614
Test name
Test status
Simulation time 646210221 ps
CPU time 2.65 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:31 PM PDT 24
Peak memory 225284 kb
Host smart-6131d802-fbb7-4577-abd3-5588b18c74b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673972556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1673972556
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2388884340
Short name T592
Test name
Test status
Simulation time 710904194 ps
CPU time 3.57 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 225316 kb
Host smart-eda061d0-7def-496f-98d2-287c5f1f47aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388884340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2388884340
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3977172961
Short name T542
Test name
Test status
Simulation time 634277455 ps
CPU time 4.39 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 224036 kb
Host smart-de55093b-3eec-47f6-ba70-4f38f381d590
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977172961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3977172961
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2778713562
Short name T990
Test name
Test status
Simulation time 4348925294 ps
CPU time 13.26 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 218732 kb
Host smart-e768ca4a-169f-4a9c-a6a1-47e5bb4ba7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778713562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2778713562
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3475251468
Short name T288
Test name
Test status
Simulation time 13290553476 ps
CPU time 10.47 seconds
Started Aug 19 05:43:30 PM PDT 24
Finished Aug 19 05:43:40 PM PDT 24
Peak memory 217368 kb
Host smart-434bd805-e66b-4969-b821-3f75aa87ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475251468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3475251468
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2540948974
Short name T23
Test name
Test status
Simulation time 1678614045 ps
CPU time 3.47 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:31 PM PDT 24
Peak memory 217140 kb
Host smart-1024a16c-19ed-4c75-9acd-81cfb948b222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540948974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2540948974
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1662267215
Short name T991
Test name
Test status
Simulation time 27108238 ps
CPU time 0.86 seconds
Started Aug 19 05:43:25 PM PDT 24
Finished Aug 19 05:43:26 PM PDT 24
Peak memory 207524 kb
Host smart-c071ed90-bee6-442c-b944-8fd9b8b3dd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662267215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1662267215
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.238424673
Short name T666
Test name
Test status
Simulation time 30919437 ps
CPU time 0.74 seconds
Started Aug 19 05:43:30 PM PDT 24
Finished Aug 19 05:43:30 PM PDT 24
Peak memory 206892 kb
Host smart-2c6ce740-cb84-47e6-a507-555d1b678488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238424673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.238424673
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.398279443
Short name T216
Test name
Test status
Simulation time 3918797526 ps
CPU time 15.53 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:43:43 PM PDT 24
Peak memory 239164 kb
Host smart-b0e7db8d-62c1-4307-bfef-da72e93b9b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398279443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.398279443
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2804764144
Short name T392
Test name
Test status
Simulation time 34977383 ps
CPU time 0.74 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 206324 kb
Host smart-6b8744f4-6471-426c-85c2-f79f280100aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804764144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2804764144
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2381714826
Short name T980
Test name
Test status
Simulation time 942817306 ps
CPU time 3.35 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:31 PM PDT 24
Peak memory 225356 kb
Host smart-63ccd4b5-2099-4d3c-9ea4-fb543d7f89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381714826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2381714826
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1811533595
Short name T448
Test name
Test status
Simulation time 28893893 ps
CPU time 0.77 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 206476 kb
Host smart-4fb2ed85-d32b-4e89-8598-4a848d332c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811533595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1811533595
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2930880975
Short name T790
Test name
Test status
Simulation time 4809156819 ps
CPU time 63.79 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:44:33 PM PDT 24
Peak memory 250416 kb
Host smart-0c7d75f2-d371-4436-9a44-7b69e6700486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930880975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2930880975
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.177674026
Short name T160
Test name
Test status
Simulation time 65967548213 ps
CPU time 602.39 seconds
Started Aug 19 05:43:30 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 273252 kb
Host smart-1aeda213-1bc1-411a-ba38-0afd0dbd3646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177674026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.177674026
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3496548948
Short name T945
Test name
Test status
Simulation time 719360865 ps
CPU time 5.07 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 235440 kb
Host smart-a837973b-04a2-4102-9a1b-f17ff77f66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496548948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3496548948
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3938125216
Short name T953
Test name
Test status
Simulation time 31332184469 ps
CPU time 107.62 seconds
Started Aug 19 05:43:30 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 263556 kb
Host smart-131f13ca-f094-4d3a-94e0-5b09f351abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938125216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3938125216
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.192557906
Short name T719
Test name
Test status
Simulation time 289241515 ps
CPU time 6.46 seconds
Started Aug 19 05:43:30 PM PDT 24
Finished Aug 19 05:43:37 PM PDT 24
Peak memory 225452 kb
Host smart-ecefdafa-2b1e-422b-b146-a6dcbbc153d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192557906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.192557906
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.678399232
Short name T574
Test name
Test status
Simulation time 1622738794 ps
CPU time 13.73 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 235256 kb
Host smart-f422d3c1-9c22-48be-97b4-b46f3c973740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678399232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.678399232
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3699862578
Short name T40
Test name
Test status
Simulation time 1434532049 ps
CPU time 5.78 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:34 PM PDT 24
Peak memory 225164 kb
Host smart-eb9dafc3-6d85-4074-8c5b-f229d4570bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699862578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3699862578
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1223909649
Short name T124
Test name
Test status
Simulation time 34491817 ps
CPU time 2.15 seconds
Started Aug 19 05:43:24 PM PDT 24
Finished Aug 19 05:43:27 PM PDT 24
Peak memory 233500 kb
Host smart-8af8dbd5-3d43-4e8e-9bab-c4b4e277def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223909649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1223909649
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1653251495
Short name T408
Test name
Test status
Simulation time 7218330649 ps
CPU time 16.61 seconds
Started Aug 19 05:43:31 PM PDT 24
Finished Aug 19 05:43:47 PM PDT 24
Peak memory 221052 kb
Host smart-50ada61d-0ba7-489a-bb34-b476102424b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1653251495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1653251495
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.236318506
Short name T426
Test name
Test status
Simulation time 132502959508 ps
CPU time 435.83 seconds
Started Aug 19 05:43:29 PM PDT 24
Finished Aug 19 05:50:45 PM PDT 24
Peak memory 258396 kb
Host smart-aba97884-06f1-4196-b520-e29fd0544b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236318506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.236318506
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1341150016
Short name T391
Test name
Test status
Simulation time 17735941858 ps
CPU time 27.32 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:43:55 PM PDT 24
Peak memory 217424 kb
Host smart-5c59bbe6-52a8-47b6-9cfb-ac4182979008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341150016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1341150016
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3128984437
Short name T315
Test name
Test status
Simulation time 8228724588 ps
CPU time 14.01 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 217276 kb
Host smart-56c69dab-2f4e-433f-8384-fae7e1ca992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128984437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3128984437
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3476642133
Short name T337
Test name
Test status
Simulation time 2007513506 ps
CPU time 5.12 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:33 PM PDT 24
Peak memory 217272 kb
Host smart-9a0e91d3-2707-41d7-93bc-d743ea8cf7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476642133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3476642133
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2276523632
Short name T805
Test name
Test status
Simulation time 41849425 ps
CPU time 0.78 seconds
Started Aug 19 05:43:28 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 206892 kb
Host smart-ee3ea9c6-4f59-400e-ae9b-9e3aaa959444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276523632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2276523632
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.441713791
Short name T818
Test name
Test status
Simulation time 705763433 ps
CPU time 4.78 seconds
Started Aug 19 05:43:25 PM PDT 24
Finished Aug 19 05:43:30 PM PDT 24
Peak memory 233592 kb
Host smart-eaeaad62-a4b4-40ac-8bdf-f55003642124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441713791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.441713791
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3804412579
Short name T339
Test name
Test status
Simulation time 40182187 ps
CPU time 0.7 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 206640 kb
Host smart-3df4af09-55f4-488b-b5f9-c7cf6fe067d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804412579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3804412579
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.420469360
Short name T966
Test name
Test status
Simulation time 115960747 ps
CPU time 2.13 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:43:43 PM PDT 24
Peak memory 225336 kb
Host smart-3b05d102-6af7-45c4-9532-7246444581e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420469360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.420469360
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1998438479
Short name T445
Test name
Test status
Simulation time 13465259 ps
CPU time 0.76 seconds
Started Aug 19 05:43:31 PM PDT 24
Finished Aug 19 05:43:31 PM PDT 24
Peak memory 207800 kb
Host smart-34fb830e-c838-40c3-8789-ea391252006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998438479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1998438479
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3478710679
Short name T988
Test name
Test status
Simulation time 15016450365 ps
CPU time 52.15 seconds
Started Aug 19 05:43:43 PM PDT 24
Finished Aug 19 05:44:36 PM PDT 24
Peak memory 250100 kb
Host smart-58a30c5d-92af-4e01-978b-5d4a88225836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478710679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3478710679
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3061185684
Short name T456
Test name
Test status
Simulation time 5585007462 ps
CPU time 53.31 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:44:34 PM PDT 24
Peak memory 233880 kb
Host smart-32539577-6f59-4290-9e4f-997e095b461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061185684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3061185684
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.576496262
Short name T722
Test name
Test status
Simulation time 4601220168 ps
CPU time 46.55 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:44:26 PM PDT 24
Peak memory 250080 kb
Host smart-a5d1fa31-d849-4481-905d-56d2b099db4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576496262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.576496262
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1091397811
Short name T965
Test name
Test status
Simulation time 1543047139 ps
CPU time 10.43 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:43:48 PM PDT 24
Peak memory 225436 kb
Host smart-0c051266-7b8c-4577-ac0e-ea8fa5aa50ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091397811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1091397811
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3104468238
Short name T858
Test name
Test status
Simulation time 21668195110 ps
CPU time 153.28 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:46:12 PM PDT 24
Peak memory 254788 kb
Host smart-b62f1774-e319-4bdf-98a3-bb390e788c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104468238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3104468238
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3177023800
Short name T248
Test name
Test status
Simulation time 1805326172 ps
CPU time 4.6 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:43:45 PM PDT 24
Peak memory 225388 kb
Host smart-030d2605-0347-4d89-87e5-3f36987d8059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177023800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3177023800
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.547666981
Short name T222
Test name
Test status
Simulation time 6121426622 ps
CPU time 56.22 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 225484 kb
Host smart-96f233ff-3402-4090-85f2-2d09db16fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547666981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.547666981
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1438387370
Short name T205
Test name
Test status
Simulation time 7594879301 ps
CPU time 10.19 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:43:48 PM PDT 24
Peak memory 225468 kb
Host smart-2fded272-5cc4-4280-9dc7-c23da66f8a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438387370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1438387370
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3745868385
Short name T227
Test name
Test status
Simulation time 198863672 ps
CPU time 5.27 seconds
Started Aug 19 05:43:43 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 233612 kb
Host smart-6c56007d-9527-46b8-ab43-e03675b0bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745868385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3745868385
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1427525164
Short name T952
Test name
Test status
Simulation time 2093167016 ps
CPU time 5.02 seconds
Started Aug 19 05:43:36 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 223532 kb
Host smart-c1283ae8-5c61-424e-8162-695830f4adee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1427525164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1427525164
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1661361765
Short name T234
Test name
Test status
Simulation time 80219373525 ps
CPU time 322.91 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:49:01 PM PDT 24
Peak memory 253164 kb
Host smart-2026fcd0-3064-473c-9b47-3983fc983274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661361765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1661361765
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.669351770
Short name T412
Test name
Test status
Simulation time 14022942580 ps
CPU time 39.94 seconds
Started Aug 19 05:43:30 PM PDT 24
Finished Aug 19 05:44:10 PM PDT 24
Peak memory 217416 kb
Host smart-60c43739-db7d-4bdf-ae84-64dcbf11d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669351770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.669351770
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1179122891
Short name T79
Test name
Test status
Simulation time 413872825 ps
CPU time 2.53 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:43:30 PM PDT 24
Peak memory 217208 kb
Host smart-37838165-6e58-4167-9365-edd1ff4adbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179122891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1179122891
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.605774718
Short name T336
Test name
Test status
Simulation time 100898506 ps
CPU time 1.27 seconds
Started Aug 19 05:43:31 PM PDT 24
Finished Aug 19 05:43:32 PM PDT 24
Peak memory 217352 kb
Host smart-3e58d908-3159-4517-8012-ed4cef0b4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605774718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.605774718
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2105438299
Short name T683
Test name
Test status
Simulation time 21965189 ps
CPU time 0.78 seconds
Started Aug 19 05:43:27 PM PDT 24
Finished Aug 19 05:43:28 PM PDT 24
Peak memory 206916 kb
Host smart-6995e180-c96f-4a0e-92f4-6d0ba2ecbecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105438299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2105438299
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1460417284
Short name T482
Test name
Test status
Simulation time 2540736089 ps
CPU time 5.72 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:43:47 PM PDT 24
Peak memory 233744 kb
Host smart-592291c9-f2a6-4e8b-b71c-b76bb2436fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460417284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1460417284
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3782907863
Short name T949
Test name
Test status
Simulation time 13545062 ps
CPU time 0.71 seconds
Started Aug 19 05:43:43 PM PDT 24
Finished Aug 19 05:43:44 PM PDT 24
Peak memory 206568 kb
Host smart-125970fd-d462-4a95-a5d1-ea977eeb4aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782907863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3782907863
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.323615297
Short name T439
Test name
Test status
Simulation time 1277631934 ps
CPU time 6.4 seconds
Started Aug 19 05:43:45 PM PDT 24
Finished Aug 19 05:43:51 PM PDT 24
Peak memory 233608 kb
Host smart-66270e15-3e99-4d2f-9a88-74267fbc88d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323615297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.323615297
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2081807933
Short name T611
Test name
Test status
Simulation time 21131061 ps
CPU time 0.87 seconds
Started Aug 19 05:43:37 PM PDT 24
Finished Aug 19 05:43:38 PM PDT 24
Peak memory 207724 kb
Host smart-0ec4b7e9-4c0c-4b1c-befa-136c30940bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081807933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2081807933
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1519645156
Short name T34
Test name
Test status
Simulation time 165620801437 ps
CPU time 137.48 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:45:56 PM PDT 24
Peak memory 257504 kb
Host smart-7f93d633-3e4d-41aa-b853-8846b3e53136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519645156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1519645156
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2078517464
Short name T59
Test name
Test status
Simulation time 24228355290 ps
CPU time 37.26 seconds
Started Aug 19 05:43:35 PM PDT 24
Finished Aug 19 05:44:12 PM PDT 24
Peak memory 218860 kb
Host smart-6e303f00-9283-4f7e-ad9b-4e510c03b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078517464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2078517464
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2070173539
Short name T884
Test name
Test status
Simulation time 12777651651 ps
CPU time 36.05 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:44:15 PM PDT 24
Peak memory 225808 kb
Host smart-02f9f668-4f22-4068-91c8-fe4c28310763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070173539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2070173539
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.854539170
Short name T963
Test name
Test status
Simulation time 107399632 ps
CPU time 3.53 seconds
Started Aug 19 05:43:37 PM PDT 24
Finished Aug 19 05:43:40 PM PDT 24
Peak memory 234108 kb
Host smart-5ca349e1-4f36-40d4-9203-7ff299610109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854539170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.854539170
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1983467961
Short name T897
Test name
Test status
Simulation time 10449631989 ps
CPU time 75.85 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:44:55 PM PDT 24
Peak memory 254592 kb
Host smart-6f858eed-9b1b-408d-bf00-1effa4cc1167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983467961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1983467961
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1375423929
Short name T547
Test name
Test status
Simulation time 8401256388 ps
CPU time 40.71 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:44:21 PM PDT 24
Peak memory 225420 kb
Host smart-f7ad35bf-b9bf-42e0-a375-555e8374d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375423929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1375423929
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.634186906
Short name T487
Test name
Test status
Simulation time 13436355645 ps
CPU time 35.12 seconds
Started Aug 19 05:43:39 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 235056 kb
Host smart-1aa66f77-4a54-473a-9eb7-b54879e1295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634186906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.634186906
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3715418476
Short name T243
Test name
Test status
Simulation time 75469927 ps
CPU time 2.63 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 233648 kb
Host smart-4d4908c1-c0c2-42cd-933c-aa9d59510678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715418476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3715418476
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.922759862
Short name T251
Test name
Test status
Simulation time 436319914 ps
CPU time 3.19 seconds
Started Aug 19 05:43:39 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 233628 kb
Host smart-6eb6e83c-0116-42bb-8f8b-ac2250be0669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922759862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.922759862
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2663377455
Short name T405
Test name
Test status
Simulation time 1050159978 ps
CPU time 13.7 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:43:53 PM PDT 24
Peak memory 223568 kb
Host smart-2cd364ba-75d7-4f41-a3fa-6d2589568441
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663377455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2663377455
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.692658801
Short name T691
Test name
Test status
Simulation time 44778705 ps
CPU time 0.99 seconds
Started Aug 19 05:43:37 PM PDT 24
Finished Aug 19 05:43:38 PM PDT 24
Peak memory 207808 kb
Host smart-c267b025-d71d-4f00-a08b-7b65f2dd7e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692658801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.692658801
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2027141361
Short name T493
Test name
Test status
Simulation time 1653953904 ps
CPU time 5.25 seconds
Started Aug 19 05:43:35 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 217284 kb
Host smart-c89faee7-d0a5-49b6-a2c0-06489897f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027141361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2027141361
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1729340742
Short name T916
Test name
Test status
Simulation time 2466041560 ps
CPU time 5.97 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:43:47 PM PDT 24
Peak memory 217340 kb
Host smart-7c836ccf-b889-421c-84a8-9886e9714d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729340742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1729340742
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.514038126
Short name T461
Test name
Test status
Simulation time 271932485 ps
CPU time 1.74 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 217176 kb
Host smart-49109fc9-abef-4fe4-9c36-f2b6b71cc82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514038126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.514038126
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2451515418
Short name T595
Test name
Test status
Simulation time 78145397 ps
CPU time 0.97 seconds
Started Aug 19 05:43:40 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 206900 kb
Host smart-da004fae-303b-4597-b0d4-82fc607d9360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451515418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2451515418
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3955412139
Short name T601
Test name
Test status
Simulation time 31050072325 ps
CPU time 9.52 seconds
Started Aug 19 05:43:39 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 237596 kb
Host smart-07b12a7b-8c84-4d02-90ec-024751ba332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955412139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3955412139
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3444740957
Short name T800
Test name
Test status
Simulation time 73607839 ps
CPU time 0.76 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 206248 kb
Host smart-dc6b02b2-99ff-44c0-9d41-4d6e7d237c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444740957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3444740957
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4169548797
Short name T914
Test name
Test status
Simulation time 463118233 ps
CPU time 5.4 seconds
Started Aug 19 05:43:53 PM PDT 24
Finished Aug 19 05:43:58 PM PDT 24
Peak memory 225448 kb
Host smart-8c7f61ed-323c-4302-b438-9ac0c8b06935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169548797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4169548797
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3299951526
Short name T447
Test name
Test status
Simulation time 63107744 ps
CPU time 0.8 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 207768 kb
Host smart-f635bdde-6303-415e-8e02-e3fd7d87dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299951526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3299951526
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3271313456
Short name T170
Test name
Test status
Simulation time 1449588661 ps
CPU time 6.42 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:54 PM PDT 24
Peak memory 225472 kb
Host smart-890b7d93-47b0-44b1-8a02-b1e27a3700e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271313456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3271313456
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.27953421
Short name T262
Test name
Test status
Simulation time 3271114357 ps
CPU time 94.9 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 257592 kb
Host smart-36656376-bcfa-4a6d-b6b2-1edc48734272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27953421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.27953421
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1173545341
Short name T598
Test name
Test status
Simulation time 25188560456 ps
CPU time 207.4 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:47:15 PM PDT 24
Peak memory 249324 kb
Host smart-edba2cf2-2502-4ccc-bebb-6d74dbb27141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173545341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1173545341
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1419015146
Short name T431
Test name
Test status
Simulation time 619978463 ps
CPU time 8.12 seconds
Started Aug 19 05:43:43 PM PDT 24
Finished Aug 19 05:43:52 PM PDT 24
Peak memory 233288 kb
Host smart-11b2d44d-673d-4b52-95c4-7236c2318b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419015146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1419015146
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2388814423
Short name T910
Test name
Test status
Simulation time 17908440127 ps
CPU time 50.71 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:44:40 PM PDT 24
Peak memory 241036 kb
Host smart-32e9c396-3071-4f75-868e-f7713f6cfb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388814423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2388814423
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1594297556
Short name T505
Test name
Test status
Simulation time 2024410890 ps
CPU time 3.21 seconds
Started Aug 19 05:43:38 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 233632 kb
Host smart-2095bd3d-44fd-448e-95b3-69417136ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594297556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1594297556
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1663576187
Short name T898
Test name
Test status
Simulation time 763808806 ps
CPU time 6.64 seconds
Started Aug 19 05:43:39 PM PDT 24
Finished Aug 19 05:43:46 PM PDT 24
Peak memory 225356 kb
Host smart-c7784045-39a4-44c8-945f-aa286d374c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663576187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1663576187
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2559440158
Short name T588
Test name
Test status
Simulation time 1252620335 ps
CPU time 8.65 seconds
Started Aug 19 05:43:53 PM PDT 24
Finished Aug 19 05:44:01 PM PDT 24
Peak memory 223048 kb
Host smart-1b4626f5-95fa-4fe1-b1ff-351ffd4dc6d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2559440158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2559440158
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1972126513
Short name T266
Test name
Test status
Simulation time 77379780425 ps
CPU time 195.15 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:47:03 PM PDT 24
Peak memory 253972 kb
Host smart-0c03522b-4174-4acb-b928-3bf2ad1ca7be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972126513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1972126513
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3852766613
Short name T579
Test name
Test status
Simulation time 2305874100 ps
CPU time 2.17 seconds
Started Aug 19 05:43:37 PM PDT 24
Finished Aug 19 05:43:39 PM PDT 24
Peak memory 219288 kb
Host smart-b89e9094-bb2c-42e0-831b-0db2f647c054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852766613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3852766613
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3308511402
Short name T302
Test name
Test status
Simulation time 83183156 ps
CPU time 0.73 seconds
Started Aug 19 05:43:41 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 206512 kb
Host smart-3a8b24a6-66f9-4317-b6b3-5a8c8b77007b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308511402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3308511402
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2672168025
Short name T312
Test name
Test status
Simulation time 274111900 ps
CPU time 1.84 seconds
Started Aug 19 05:43:39 PM PDT 24
Finished Aug 19 05:43:41 PM PDT 24
Peak memory 217228 kb
Host smart-cb44da37-605c-404f-84c7-63987160b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672168025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2672168025
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3877806477
Short name T351
Test name
Test status
Simulation time 157534142 ps
CPU time 0.98 seconds
Started Aug 19 05:43:37 PM PDT 24
Finished Aug 19 05:43:38 PM PDT 24
Peak memory 206896 kb
Host smart-951608ab-69a7-437b-af70-d3b4352bfdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877806477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3877806477
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1282337195
Short name T753
Test name
Test status
Simulation time 4195624925 ps
CPU time 7.71 seconds
Started Aug 19 05:43:50 PM PDT 24
Finished Aug 19 05:43:58 PM PDT 24
Peak memory 225560 kb
Host smart-74faed49-3c38-4d72-bd6d-23768d1bc01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282337195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1282337195
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4152931577
Short name T1
Test name
Test status
Simulation time 39656564 ps
CPU time 0.78 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 205556 kb
Host smart-265584e4-9792-4613-b43b-671b3fc46128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152931577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4152931577
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3552514443
Short name T420
Test name
Test status
Simulation time 1751932472 ps
CPU time 6.98 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:55 PM PDT 24
Peak memory 233588 kb
Host smart-369a41f0-be1c-4302-84c3-6c1c605c2390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552514443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3552514443
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2195556419
Short name T585
Test name
Test status
Simulation time 14813380 ps
CPU time 0.83 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:43:50 PM PDT 24
Peak memory 207472 kb
Host smart-628e44d9-2c7f-4503-a92e-2da747ed0144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195556419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2195556419
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2179395174
Short name T586
Test name
Test status
Simulation time 2814141525 ps
CPU time 20.73 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:44:08 PM PDT 24
Peak memory 236988 kb
Host smart-7f562389-d905-470e-b191-23dda03c9c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179395174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2179395174
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3824124765
Short name T422
Test name
Test status
Simulation time 47111791119 ps
CPU time 42.37 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 218828 kb
Host smart-759a7dd7-16f0-4453-af98-4ab7b7080410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824124765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3824124765
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3140207955
Short name T861
Test name
Test status
Simulation time 53286940 ps
CPU time 3.04 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:51 PM PDT 24
Peak memory 233616 kb
Host smart-a97e9084-54be-4fe1-ba13-b7371ee1c2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140207955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3140207955
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3607919390
Short name T468
Test name
Test status
Simulation time 14894977094 ps
CPU time 65.43 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:44:54 PM PDT 24
Peak memory 252132 kb
Host smart-24090257-abe1-4b8f-bf8a-1471aa972d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607919390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3607919390
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1577855896
Short name T732
Test name
Test status
Simulation time 818684888 ps
CPU time 9.63 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:43:59 PM PDT 24
Peak memory 233668 kb
Host smart-a85ae082-8f0b-4603-b740-3a4098b7df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577855896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1577855896
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2251793315
Short name T605
Test name
Test status
Simulation time 159533485 ps
CPU time 3.5 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:52 PM PDT 24
Peak memory 233556 kb
Host smart-9fe17ec5-917f-4fff-a8df-b0e2a714fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251793315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2251793315
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.389641964
Short name T867
Test name
Test status
Simulation time 7989823092 ps
CPU time 11.71 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:43:57 PM PDT 24
Peak memory 241828 kb
Host smart-d2f8bdeb-9c27-4f08-867b-21ec418d3a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389641964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.389641964
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2177119598
Short name T660
Test name
Test status
Simulation time 635580583 ps
CPU time 4.35 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:53 PM PDT 24
Peak memory 225388 kb
Host smart-88ec95a0-32d6-4b4c-a0e6-1d68ce84dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177119598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2177119598
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2881348680
Short name T495
Test name
Test status
Simulation time 248086808 ps
CPU time 4.87 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:54 PM PDT 24
Peak memory 223936 kb
Host smart-b06215b9-e8a6-4c4e-9e55-b36b5b75408f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881348680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2881348680
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1464126682
Short name T246
Test name
Test status
Simulation time 72802568578 ps
CPU time 568.62 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:53:16 PM PDT 24
Peak memory 258436 kb
Host smart-e2ded388-f0fd-46b9-95bb-30807dc72410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464126682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1464126682
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3879048370
Short name T599
Test name
Test status
Simulation time 4120373403 ps
CPU time 27.77 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 217324 kb
Host smart-335cc775-a8fa-4938-be6f-a5a7eea0e1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879048370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3879048370
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.447228918
Short name T577
Test name
Test status
Simulation time 7361396787 ps
CPU time 7.62 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:43:55 PM PDT 24
Peak memory 217344 kb
Host smart-46376096-cb40-45d4-91b3-2739e0777348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447228918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.447228918
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.612101863
Short name T900
Test name
Test status
Simulation time 132381416 ps
CPU time 2.12 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:43:51 PM PDT 24
Peak memory 217116 kb
Host smart-7f2e152d-5860-4b33-90a8-c6939c70a33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612101863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.612101863
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1670506744
Short name T413
Test name
Test status
Simulation time 56924204 ps
CPU time 0.79 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 206896 kb
Host smart-8a7b5def-151c-4f27-b2ae-a87b2b053116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670506744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1670506744
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.92406463
Short name T208
Test name
Test status
Simulation time 265014291 ps
CPU time 5.61 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:43:53 PM PDT 24
Peak memory 233620 kb
Host smart-012d33ad-478d-4607-a623-ddcefc0e6d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92406463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.92406463
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3757838670
Short name T536
Test name
Test status
Simulation time 13655091 ps
CPU time 0.81 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:42:52 PM PDT 24
Peak memory 206704 kb
Host smart-9afbe0b8-11de-404a-94ab-7c7daeec93a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757838670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
757838670
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.981132996
Short name T713
Test name
Test status
Simulation time 199317728 ps
CPU time 2.64 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:42:54 PM PDT 24
Peak memory 225420 kb
Host smart-a15f6438-fbfe-4b86-9b1c-1ef9547543df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981132996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.981132996
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.407544095
Short name T758
Test name
Test status
Simulation time 67761407 ps
CPU time 0.83 seconds
Started Aug 19 05:42:38 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 207432 kb
Host smart-03496dc8-1aed-42ca-bf5b-fd9632e6a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407544095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.407544095
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.877489887
Short name T278
Test name
Test status
Simulation time 26844360994 ps
CPU time 157.84 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 250160 kb
Host smart-50b47f3d-e3e0-4c86-9fa2-395e02f56356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877489887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.877489887
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1563235982
Short name T176
Test name
Test status
Simulation time 29551091234 ps
CPU time 136.61 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:45:08 PM PDT 24
Peak memory 250232 kb
Host smart-11414d66-2124-46eb-abd3-0e855793cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563235982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1563235982
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1931020867
Short name T24
Test name
Test status
Simulation time 8444748127 ps
CPU time 51.67 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:43:42 PM PDT 24
Peak memory 225672 kb
Host smart-b90a470f-b22d-40ce-a59a-3363bb7c90e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931020867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1931020867
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2485190929
Short name T593
Test name
Test status
Simulation time 115021935 ps
CPU time 4.88 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:42:56 PM PDT 24
Peak memory 225476 kb
Host smart-b5fa2d94-dc3a-4150-9138-d6fe452df02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485190929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2485190929
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1502721532
Short name T744
Test name
Test status
Simulation time 172102519 ps
CPU time 0.86 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:42:51 PM PDT 24
Peak memory 216932 kb
Host smart-d8bcc0d2-2bb7-45fe-8883-b39250754c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502721532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1502721532
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1266092228
Short name T92
Test name
Test status
Simulation time 498367059 ps
CPU time 3.92 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:44 PM PDT 24
Peak memory 233620 kb
Host smart-6a6d767e-4ebb-49c4-978d-d5903a92893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266092228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1266092228
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.272921845
Short name T537
Test name
Test status
Simulation time 4273385940 ps
CPU time 13.33 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:43:03 PM PDT 24
Peak memory 225556 kb
Host smart-8a3ca0d4-5f1b-4a18-94c7-4296ab3dd3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272921845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.272921845
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2919178955
Short name T57
Test name
Test status
Simulation time 1810615041 ps
CPU time 7.74 seconds
Started Aug 19 05:42:39 PM PDT 24
Finished Aug 19 05:42:47 PM PDT 24
Peak memory 233540 kb
Host smart-0ce20ea3-a61d-49c1-a333-ec3d6b9f1ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919178955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2919178955
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.889308054
Short name T484
Test name
Test status
Simulation time 902251835 ps
CPU time 4.21 seconds
Started Aug 19 05:42:42 PM PDT 24
Finished Aug 19 05:42:46 PM PDT 24
Peak memory 225364 kb
Host smart-11828bf0-c87b-45a1-b6ef-a5eb86da93c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889308054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.889308054
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1472112236
Short name T724
Test name
Test status
Simulation time 93263741 ps
CPU time 3.88 seconds
Started Aug 19 05:42:55 PM PDT 24
Finished Aug 19 05:42:59 PM PDT 24
Peak memory 223916 kb
Host smart-f1acc616-f067-4e99-b3b1-bea92f42407f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472112236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1472112236
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1000285710
Short name T55
Test name
Test status
Simulation time 122618089 ps
CPU time 0.99 seconds
Started Aug 19 05:42:57 PM PDT 24
Finished Aug 19 05:42:58 PM PDT 24
Peak memory 236536 kb
Host smart-08db7c72-380e-4c1e-8eca-d486da3cdc53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000285710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1000285710
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2464612394
Short name T6
Test name
Test status
Simulation time 51604039 ps
CPU time 1.01 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:42:53 PM PDT 24
Peak memory 207504 kb
Host smart-129b6623-6471-4e5d-91e8-95c10efb4615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464612394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2464612394
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3363031520
Short name T549
Test name
Test status
Simulation time 3204672582 ps
CPU time 14.97 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:42:59 PM PDT 24
Peak memory 217116 kb
Host smart-090509a7-8f44-40d7-8b19-1444503a82e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363031520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3363031520
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.917086595
Short name T627
Test name
Test status
Simulation time 2210946616 ps
CPU time 5.06 seconds
Started Aug 19 05:42:44 PM PDT 24
Finished Aug 19 05:42:50 PM PDT 24
Peak memory 217012 kb
Host smart-402cc833-c859-47fa-946d-b161a033df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917086595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.917086595
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3647757308
Short name T323
Test name
Test status
Simulation time 2327459493 ps
CPU time 2.15 seconds
Started Aug 19 05:42:37 PM PDT 24
Finished Aug 19 05:42:40 PM PDT 24
Peak memory 217308 kb
Host smart-67b325ee-ce22-4bc3-904a-a516c36b0221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647757308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3647757308
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2329608609
Short name T937
Test name
Test status
Simulation time 15115995 ps
CPU time 0.75 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:42:41 PM PDT 24
Peak memory 206900 kb
Host smart-a7ff7af0-f582-40e7-a1d7-72b13b07950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329608609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2329608609
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.673594299
Short name T432
Test name
Test status
Simulation time 65331405391 ps
CPU time 37 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 240544 kb
Host smart-5b0d14e4-9a51-41b2-a49b-6c90b499068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673594299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.673594299
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2470657455
Short name T382
Test name
Test status
Simulation time 14089948 ps
CPU time 0.72 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:01 PM PDT 24
Peak memory 206336 kb
Host smart-2f5b85cd-8f18-4ff8-9766-9d31ddea4dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470657455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2470657455
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1978885191
Short name T226
Test name
Test status
Simulation time 424884319 ps
CPU time 3.35 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:43:50 PM PDT 24
Peak memory 233648 kb
Host smart-33517d8c-180f-4aee-b150-037975b614ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978885191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1978885191
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2534514395
Short name T572
Test name
Test status
Simulation time 69126771 ps
CPU time 0.78 seconds
Started Aug 19 05:43:47 PM PDT 24
Finished Aug 19 05:43:48 PM PDT 24
Peak memory 207784 kb
Host smart-31bce5bd-850b-47e6-bd13-5ab943c6d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534514395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2534514395
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4065328946
Short name T256
Test name
Test status
Simulation time 8004758321 ps
CPU time 100.98 seconds
Started Aug 19 05:43:50 PM PDT 24
Finished Aug 19 05:45:31 PM PDT 24
Peak memory 254356 kb
Host smart-d760a053-5f14-4115-b8b2-211eb661439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065328946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4065328946
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1051316828
Short name T186
Test name
Test status
Simulation time 10993382627 ps
CPU time 83.36 seconds
Started Aug 19 05:43:51 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 254024 kb
Host smart-3cb08ceb-13d7-43bf-86c0-aed3befd5e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051316828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1051316828
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.593854519
Short name T398
Test name
Test status
Simulation time 26097041427 ps
CPU time 68.49 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:45:09 PM PDT 24
Peak memory 240000 kb
Host smart-b4a68a3a-a328-4048-a1a2-948bcdc7b3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593854519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.593854519
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3660618033
Short name T282
Test name
Test status
Simulation time 1278472801 ps
CPU time 11.72 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:44:01 PM PDT 24
Peak memory 233624 kb
Host smart-2ff8e2c1-b45a-4add-ba0f-2c5108d50bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660618033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3660618033
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1578519841
Short name T794
Test name
Test status
Simulation time 51289448824 ps
CPU time 111.8 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:45:40 PM PDT 24
Peak memory 250136 kb
Host smart-34b4e4a4-a8bb-468a-8584-096cd989578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578519841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1578519841
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2642681764
Short name T734
Test name
Test status
Simulation time 2513654914 ps
CPU time 24.81 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:44:13 PM PDT 24
Peak memory 225508 kb
Host smart-e11e0133-da6c-4193-b8fc-513e423083ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642681764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2642681764
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.549572445
Short name T735
Test name
Test status
Simulation time 3194764846 ps
CPU time 18.27 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 225500 kb
Host smart-42c18ece-aba3-4065-9f43-0e4cd50e9cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549572445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.549572445
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3061655782
Short name T825
Test name
Test status
Simulation time 484645439 ps
CPU time 2.47 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:51 PM PDT 24
Peak memory 224988 kb
Host smart-38d9bfbd-e071-4c78-88c8-1b1bb4a22c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061655782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3061655782
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3939378339
Short name T891
Test name
Test status
Simulation time 58906691 ps
CPU time 2.15 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:43:48 PM PDT 24
Peak memory 225272 kb
Host smart-50026429-b555-4517-b5ca-f97e92c9613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939378339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3939378339
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3153841093
Short name T367
Test name
Test status
Simulation time 410671924 ps
CPU time 5.62 seconds
Started Aug 19 05:43:46 PM PDT 24
Finished Aug 19 05:43:52 PM PDT 24
Peak memory 223540 kb
Host smart-fdc7e062-df0b-42ae-8e3d-92ab765c7fd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3153841093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3153841093
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4151431778
Short name T822
Test name
Test status
Simulation time 56478797075 ps
CPU time 124.88 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:46:06 PM PDT 24
Peak memory 233816 kb
Host smart-6df7bbef-4b09-4a6b-9d47-e44ccba8c0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151431778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4151431778
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4046866223
Short name T287
Test name
Test status
Simulation time 2039532927 ps
CPU time 20.27 seconds
Started Aug 19 05:43:49 PM PDT 24
Finished Aug 19 05:44:09 PM PDT 24
Peak memory 217208 kb
Host smart-61afd2a6-d5a1-447c-9dee-7104e3e4d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046866223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4046866223
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.905140828
Short name T799
Test name
Test status
Simulation time 21611790 ps
CPU time 0.72 seconds
Started Aug 19 05:43:52 PM PDT 24
Finished Aug 19 05:43:53 PM PDT 24
Peak memory 206568 kb
Host smart-8cf7b770-758b-466e-ac5b-05ab415c4bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905140828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.905140828
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2322234356
Short name T852
Test name
Test status
Simulation time 51139827 ps
CPU time 0.97 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:49 PM PDT 24
Peak memory 207980 kb
Host smart-1f83bb54-f25c-4c23-b853-2dfdee97ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322234356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2322234356
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2133995299
Short name T969
Test name
Test status
Simulation time 67883158 ps
CPU time 0.94 seconds
Started Aug 19 05:43:45 PM PDT 24
Finished Aug 19 05:43:46 PM PDT 24
Peak memory 206852 kb
Host smart-0d9850b7-8326-4994-8fd4-c911b06b9f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133995299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2133995299
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.226383306
Short name T668
Test name
Test status
Simulation time 1731442129 ps
CPU time 6.25 seconds
Started Aug 19 05:43:48 PM PDT 24
Finished Aug 19 05:43:54 PM PDT 24
Peak memory 225484 kb
Host smart-4a293825-b61c-448e-ba43-8a064a0ceab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226383306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.226383306
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.437352821
Short name T552
Test name
Test status
Simulation time 139091644 ps
CPU time 0.72 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:02 PM PDT 24
Peak memory 205756 kb
Host smart-b250de5a-5748-476c-87b1-f194b2843492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437352821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.437352821
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2289089747
Short name T249
Test name
Test status
Simulation time 54707079 ps
CPU time 2.83 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:04 PM PDT 24
Peak memory 233452 kb
Host smart-b86590c4-8851-46ba-a54f-78dcd7a77f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289089747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2289089747
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.962219864
Short name T623
Test name
Test status
Simulation time 18558364 ps
CPU time 0.76 seconds
Started Aug 19 05:43:59 PM PDT 24
Finished Aug 19 05:44:00 PM PDT 24
Peak memory 206416 kb
Host smart-a3709efa-f1bc-4bff-abfc-e643d2de8152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962219864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.962219864
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2153441102
Short name T978
Test name
Test status
Simulation time 6147286737 ps
CPU time 13.58 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:15 PM PDT 24
Peak memory 235128 kb
Host smart-110b68c5-41ae-4832-8213-fb459d8e384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153441102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2153441102
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2459449261
Short name T488
Test name
Test status
Simulation time 27507384173 ps
CPU time 121.29 seconds
Started Aug 19 05:44:06 PM PDT 24
Finished Aug 19 05:46:07 PM PDT 24
Peak memory 241984 kb
Host smart-56e23984-e035-46dc-acb9-7c37f347292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459449261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2459449261
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1946439009
Short name T280
Test name
Test status
Simulation time 17247107166 ps
CPU time 22.27 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:23 PM PDT 24
Peak memory 235448 kb
Host smart-08f97d96-d901-4ab2-815f-c7acb9d2a1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946439009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1946439009
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2437304785
Short name T519
Test name
Test status
Simulation time 8209224847 ps
CPU time 16.21 seconds
Started Aug 19 05:43:58 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 225564 kb
Host smart-f5464a64-5383-4f7d-a683-68bb35be70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437304785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2437304785
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3337275305
Short name T177
Test name
Test status
Simulation time 2465003552 ps
CPU time 14.73 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:15 PM PDT 24
Peak memory 233712 kb
Host smart-b22e85cf-5575-4096-ad48-22dd602b8d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337275305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3337275305
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3667735074
Short name T528
Test name
Test status
Simulation time 530643184 ps
CPU time 10.93 seconds
Started Aug 19 05:43:59 PM PDT 24
Finished Aug 19 05:44:10 PM PDT 24
Peak memory 225404 kb
Host smart-b01925b8-3a4a-495f-b787-f8faeb665812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667735074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3667735074
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1986406626
Short name T200
Test name
Test status
Simulation time 849763065 ps
CPU time 3.73 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 225324 kb
Host smart-6e4adf81-32ae-4325-b6bb-35d27b222c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986406626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1986406626
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.693392366
Short name T252
Test name
Test status
Simulation time 29717906759 ps
CPU time 21.94 seconds
Started Aug 19 05:44:05 PM PDT 24
Finished Aug 19 05:44:27 PM PDT 24
Peak memory 241872 kb
Host smart-a3e12556-18ca-406b-b908-852339188882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693392366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.693392366
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2401090300
Short name T986
Test name
Test status
Simulation time 1142494852 ps
CPU time 7.24 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:07 PM PDT 24
Peak memory 220932 kb
Host smart-13c380b8-aa66-428d-b86b-d067d8d0feab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2401090300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2401090300
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3943887431
Short name T782
Test name
Test status
Simulation time 88562830 ps
CPU time 1.09 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:44:04 PM PDT 24
Peak memory 208564 kb
Host smart-f77d4413-2d05-443d-8a18-b7c5362822f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943887431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3943887431
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3974278767
Short name T327
Test name
Test status
Simulation time 21606495 ps
CPU time 0.75 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:02 PM PDT 24
Peak memory 206560 kb
Host smart-03af1987-8d25-4eb4-b173-c9e7b84ef9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974278767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3974278767
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3574220670
Short name T75
Test name
Test status
Simulation time 1458865917 ps
CPU time 2.98 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 217276 kb
Host smart-d1471833-b7d1-4ecc-8823-fa0ee595f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574220670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3574220670
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3265059726
Short name T958
Test name
Test status
Simulation time 128612242 ps
CPU time 0.89 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:03 PM PDT 24
Peak memory 207540 kb
Host smart-3501aff0-25af-4303-8513-961c81f3b9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265059726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3265059726
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.916282850
Short name T775
Test name
Test status
Simulation time 100244740 ps
CPU time 0.77 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:01 PM PDT 24
Peak memory 206884 kb
Host smart-c2a5fdb3-0763-4d96-b102-de1f47a44a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916282850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.916282850
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.592012294
Short name T403
Test name
Test status
Simulation time 3084824713 ps
CPU time 4.89 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 233644 kb
Host smart-d816bcdf-8bfb-4aff-b104-8b923bdad2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592012294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.592012294
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4235960591
Short name T833
Test name
Test status
Simulation time 11416655 ps
CPU time 0.71 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:02 PM PDT 24
Peak memory 205760 kb
Host smart-13694450-61af-4212-9bbb-6bec3289daa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235960591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4235960591
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1757545163
Short name T712
Test name
Test status
Simulation time 322453018 ps
CPU time 4.39 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 225380 kb
Host smart-c01fc8e6-770b-4fa7-b522-7b78a4c531bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757545163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1757545163
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2117489520
Short name T304
Test name
Test status
Simulation time 14923262 ps
CPU time 0.77 seconds
Started Aug 19 05:43:59 PM PDT 24
Finished Aug 19 05:44:00 PM PDT 24
Peak memory 207512 kb
Host smart-8af5a58e-24c5-4524-898e-39b13f9dec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117489520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2117489520
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.752156586
Short name T465
Test name
Test status
Simulation time 78232288501 ps
CPU time 82.2 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:45:26 PM PDT 24
Peak memory 252048 kb
Host smart-b0fe78a0-34b7-41f3-b324-a911b7140e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752156586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.752156586
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2675361300
Short name T653
Test name
Test status
Simulation time 2029151227 ps
CPU time 34.82 seconds
Started Aug 19 05:44:05 PM PDT 24
Finished Aug 19 05:44:39 PM PDT 24
Peak memory 234588 kb
Host smart-af25f193-17ed-49ec-88c3-d8a3a726ac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675361300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2675361300
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4089586392
Short name T889
Test name
Test status
Simulation time 21508845290 ps
CPU time 135.08 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:46:18 PM PDT 24
Peak memory 266548 kb
Host smart-b1c00e74-b134-474d-b19a-53ada3b2992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089586392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4089586392
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.905365931
Short name T458
Test name
Test status
Simulation time 1030022421 ps
CPU time 3.64 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 225384 kb
Host smart-8b706b38-ca85-4a13-8ac8-7f9795e322ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905365931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.905365931
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.859997388
Short name T801
Test name
Test status
Simulation time 38760407543 ps
CPU time 102.18 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:45:45 PM PDT 24
Peak memory 233768 kb
Host smart-bb074c36-fdc7-4d8f-a9a7-79b9a735c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859997388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.859997388
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.910748801
Short name T433
Test name
Test status
Simulation time 962808904 ps
CPU time 6.17 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:06 PM PDT 24
Peak memory 239704 kb
Host smart-580cdcad-8781-4a90-9949-8651cbd2ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910748801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.910748801
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2222573534
Short name T671
Test name
Test status
Simulation time 37893880 ps
CPU time 2.67 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 233548 kb
Host smart-221486d7-c85d-41f0-bb0f-adbc4657ed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222573534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2222573534
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2096574822
Short name T127
Test name
Test status
Simulation time 191483750717 ps
CPU time 418.05 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:51:02 PM PDT 24
Peak memory 289384 kb
Host smart-9e34ff09-1e95-48d6-9bbf-72f136e36be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096574822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2096574822
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.227305418
Short name T951
Test name
Test status
Simulation time 558728567 ps
CPU time 2.35 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:03 PM PDT 24
Peak memory 217484 kb
Host smart-d13f4048-5e92-405c-a091-6b46289420f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227305418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.227305418
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4213495484
Short name T807
Test name
Test status
Simulation time 18504548213 ps
CPU time 14.03 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:15 PM PDT 24
Peak memory 217332 kb
Host smart-d4ae9d21-d791-4322-85a5-b488fa04b691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213495484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4213495484
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2996290854
Short name T899
Test name
Test status
Simulation time 328845780 ps
CPU time 2.28 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 217272 kb
Host smart-661506c9-7844-45b6-b11a-4281b9589e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996290854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2996290854
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2236921777
Short name T879
Test name
Test status
Simulation time 63717131 ps
CPU time 0.76 seconds
Started Aug 19 05:44:00 PM PDT 24
Finished Aug 19 05:44:01 PM PDT 24
Peak memory 206852 kb
Host smart-a0d3288a-56b7-463f-872d-25eb3426d984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236921777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2236921777
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3445877859
Short name T441
Test name
Test status
Simulation time 6686175869 ps
CPU time 6.45 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:07 PM PDT 24
Peak memory 233648 kb
Host smart-10a99f8d-f90a-4d34-ac23-e4acbb716d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445877859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3445877859
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.952624100
Short name T714
Test name
Test status
Simulation time 14962533 ps
CPU time 0.73 seconds
Started Aug 19 05:44:12 PM PDT 24
Finished Aug 19 05:44:13 PM PDT 24
Peak memory 205712 kb
Host smart-cae65a5b-92d2-447d-bc82-ee256b19993f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952624100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.952624100
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2194651422
Short name T84
Test name
Test status
Simulation time 181347222 ps
CPU time 4.83 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:44:09 PM PDT 24
Peak memory 233628 kb
Host smart-383b35db-6fc6-481e-a1c6-febc59fa58c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194651422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2194651422
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.30341886
Short name T344
Test name
Test status
Simulation time 16609516 ps
CPU time 0.79 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:03 PM PDT 24
Peak memory 207472 kb
Host smart-95f2adf5-2615-4ec4-ab48-d4e78b921054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30341886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.30341886
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2409227818
Short name T730
Test name
Test status
Simulation time 13310223977 ps
CPU time 59.27 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:45:03 PM PDT 24
Peak memory 250180 kb
Host smart-8295530c-97c0-4740-980e-1457bc08a7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409227818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2409227818
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3184450275
Short name T545
Test name
Test status
Simulation time 57370647370 ps
CPU time 121.69 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:46:04 PM PDT 24
Peak memory 236228 kb
Host smart-705545ea-3a24-41e2-ae5d-dd5cea2915db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184450275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3184450275
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3187086941
Short name T162
Test name
Test status
Simulation time 4133741208 ps
CPU time 31.41 seconds
Started Aug 19 05:44:06 PM PDT 24
Finished Aug 19 05:44:37 PM PDT 24
Peak memory 233868 kb
Host smart-aff67bf6-d987-46df-9613-a4d67c9eb292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187086941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3187086941
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3333331947
Short name T640
Test name
Test status
Simulation time 1971678614 ps
CPU time 29.05 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 241652 kb
Host smart-e22cc5d7-ab1f-4fdb-bfa6-b63ff9299140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333331947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3333331947
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1864663196
Short name T957
Test name
Test status
Simulation time 10426966379 ps
CPU time 85.27 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:45:29 PM PDT 24
Peak memory 250728 kb
Host smart-8789add3-8d0d-4814-823b-27f43eb7894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864663196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1864663196
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.252923188
Short name T759
Test name
Test status
Simulation time 974840095 ps
CPU time 10.21 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 233592 kb
Host smart-6304547c-734d-40de-957c-5ae6f49f414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252923188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.252923188
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.979164881
Short name T568
Test name
Test status
Simulation time 303635513 ps
CPU time 5.19 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:44:09 PM PDT 24
Peak memory 225444 kb
Host smart-78b45a82-1b56-4fe3-bf16-9ef006d09a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979164881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.979164881
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.543444532
Short name T839
Test name
Test status
Simulation time 125942490 ps
CPU time 2.6 seconds
Started Aug 19 05:44:05 PM PDT 24
Finished Aug 19 05:44:07 PM PDT 24
Peak memory 233244 kb
Host smart-c31a9f69-aa2d-465d-93ad-3de9c683e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543444532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.543444532
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1076387448
Short name T449
Test name
Test status
Simulation time 293061423 ps
CPU time 5.59 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:44:09 PM PDT 24
Peak memory 237344 kb
Host smart-d94388a2-8595-48df-a146-de72f4dbdddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076387448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1076387448
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2243858880
Short name T32
Test name
Test status
Simulation time 2275505713 ps
CPU time 4 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:44:08 PM PDT 24
Peak memory 221468 kb
Host smart-8c9539ac-78ab-456a-8904-1f6e76743bdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2243858880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2243858880
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1668343340
Short name T882
Test name
Test status
Simulation time 5455955441 ps
CPU time 29.45 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 217248 kb
Host smart-907d0d2a-db4a-4579-aefe-135a3089d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668343340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1668343340
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1662779228
Short name T674
Test name
Test status
Simulation time 31001379 ps
CPU time 0.73 seconds
Started Aug 19 05:44:01 PM PDT 24
Finished Aug 19 05:44:02 PM PDT 24
Peak memory 206460 kb
Host smart-7dd3105b-f812-49ec-9838-2f6f1bf2db8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662779228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1662779228
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2237762527
Short name T551
Test name
Test status
Simulation time 39222189 ps
CPU time 0.68 seconds
Started Aug 19 05:44:04 PM PDT 24
Finished Aug 19 05:44:05 PM PDT 24
Peak memory 206404 kb
Host smart-80da0043-7688-4e32-967b-54450bd17773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237762527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2237762527
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2920013580
Short name T649
Test name
Test status
Simulation time 34270679 ps
CPU time 0.7 seconds
Started Aug 19 05:44:02 PM PDT 24
Finished Aug 19 05:44:03 PM PDT 24
Peak memory 206404 kb
Host smart-9411a664-5fa0-419e-ae25-912c5477f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920013580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2920013580
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.810684301
Short name T621
Test name
Test status
Simulation time 3349410040 ps
CPU time 10.55 seconds
Started Aug 19 05:44:03 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 233740 kb
Host smart-05568f84-1253-41ed-a350-2470553d6dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810684301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.810684301
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2873565910
Short name T821
Test name
Test status
Simulation time 28692213 ps
CPU time 0.72 seconds
Started Aug 19 05:44:12 PM PDT 24
Finished Aug 19 05:44:13 PM PDT 24
Peak memory 205528 kb
Host smart-13c6c853-854f-4520-9235-a3567b72cdd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873565910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2873565910
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3908997636
Short name T909
Test name
Test status
Simulation time 567517765 ps
CPU time 2.73 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 225336 kb
Host smart-61478cbe-c92e-48a6-a549-7315e0fda282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908997636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3908997636
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3702663590
Short name T602
Test name
Test status
Simulation time 36400012 ps
CPU time 0.77 seconds
Started Aug 19 05:44:12 PM PDT 24
Finished Aug 19 05:44:13 PM PDT 24
Peak memory 206156 kb
Host smart-4b88acfc-7a76-471d-86ca-a2d788ea9c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702663590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3702663590
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2242298199
Short name T906
Test name
Test status
Simulation time 5760083482 ps
CPU time 112.53 seconds
Started Aug 19 05:44:09 PM PDT 24
Finished Aug 19 05:46:02 PM PDT 24
Peak memory 266232 kb
Host smart-6bedcd75-9036-4703-8579-96529c814443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242298199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2242298199
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2812706961
Short name T372
Test name
Test status
Simulation time 15323606945 ps
CPU time 129.63 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:46:21 PM PDT 24
Peak memory 250236 kb
Host smart-40b3712a-899f-48be-9c18-7b105df26ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812706961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2812706961
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.241725448
Short name T786
Test name
Test status
Simulation time 7657149285 ps
CPU time 115.35 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:46:08 PM PDT 24
Peak memory 258408 kb
Host smart-74561f89-37ee-4819-b16e-e94e5be1fb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241725448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.241725448
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3828805724
Short name T644
Test name
Test status
Simulation time 7078941045 ps
CPU time 54.37 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:45:04 PM PDT 24
Peak memory 241960 kb
Host smart-075a6cce-3414-46d2-a45f-b2fe0215ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828805724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3828805724
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2066134353
Short name T409
Test name
Test status
Simulation time 92200246073 ps
CPU time 150.94 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:46:41 PM PDT 24
Peak memory 253200 kb
Host smart-6039fa58-5d05-462f-bdba-ca7a0ed56d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066134353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2066134353
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3439764884
Short name T525
Test name
Test status
Simulation time 299818021 ps
CPU time 4.83 seconds
Started Aug 19 05:44:09 PM PDT 24
Finished Aug 19 05:44:14 PM PDT 24
Peak memory 233628 kb
Host smart-d2accd01-3abc-4f6f-a464-471a2e5e8695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439764884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3439764884
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2033130582
Short name T230
Test name
Test status
Simulation time 1081158485 ps
CPU time 7.97 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:44:21 PM PDT 24
Peak memory 225388 kb
Host smart-f13a79fa-0c8e-4991-8476-b4a06102bcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033130582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2033130582
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4116494045
Short name T931
Test name
Test status
Simulation time 3563539198 ps
CPU time 9.83 seconds
Started Aug 19 05:44:08 PM PDT 24
Finished Aug 19 05:44:18 PM PDT 24
Peak memory 241176 kb
Host smart-cad8388f-e4d0-4de5-91eb-fb05cebef397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116494045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4116494045
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3154624548
Short name T423
Test name
Test status
Simulation time 1520055182 ps
CPU time 7.12 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:44:24 PM PDT 24
Peak memory 225436 kb
Host smart-88bac22f-4c23-4556-b789-5242a8073518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154624548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3154624548
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1124922820
Short name T42
Test name
Test status
Simulation time 1052454689 ps
CPU time 4.79 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:44:15 PM PDT 24
Peak memory 223564 kb
Host smart-2d22de48-c5bc-4fd3-8934-61ad0d35c0cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124922820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1124922820
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2582762791
Short name T630
Test name
Test status
Simulation time 41253119114 ps
CPU time 103.12 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:45:54 PM PDT 24
Peak memory 255964 kb
Host smart-0b629f96-9dd9-4c4a-af45-434835d23ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582762791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2582762791
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1408947798
Short name T464
Test name
Test status
Simulation time 9092672438 ps
CPU time 5.23 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:25 PM PDT 24
Peak memory 217288 kb
Host smart-460fd365-abed-4241-bc27-f5e6f2bd12a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408947798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1408947798
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.796303983
Short name T767
Test name
Test status
Simulation time 3944475185 ps
CPU time 6.22 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:44:19 PM PDT 24
Peak memory 217384 kb
Host smart-710e9db1-5623-42c7-b190-ef34e85ab982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796303983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.796303983
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4219671978
Short name T893
Test name
Test status
Simulation time 617905646 ps
CPU time 4.91 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:44:15 PM PDT 24
Peak memory 217252 kb
Host smart-8d80e96a-5c04-4c77-8ff4-8b434938c2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219671978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4219671978
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.146271177
Short name T610
Test name
Test status
Simulation time 118178478 ps
CPU time 1 seconds
Started Aug 19 05:44:09 PM PDT 24
Finished Aug 19 05:44:10 PM PDT 24
Peak memory 207972 kb
Host smart-ae30d9d4-2a74-4a11-bfb3-72de9518d2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146271177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.146271177
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3454200988
Short name T45
Test name
Test status
Simulation time 959565741 ps
CPU time 6.1 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:18 PM PDT 24
Peak memory 225388 kb
Host smart-af49813e-ea59-489f-996f-cc67e038e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454200988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3454200988
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3966253964
Short name T569
Test name
Test status
Simulation time 17211286 ps
CPU time 0.77 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:12 PM PDT 24
Peak memory 205752 kb
Host smart-247360aa-a749-4e6b-b80e-91f9c68aa05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966253964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3966253964
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3017035911
Short name T214
Test name
Test status
Simulation time 302379320 ps
CPU time 3.3 seconds
Started Aug 19 05:44:08 PM PDT 24
Finished Aug 19 05:44:12 PM PDT 24
Peak memory 233592 kb
Host smart-ae92bf55-193d-457d-b018-9744d9be450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017035911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3017035911
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2015893823
Short name T702
Test name
Test status
Simulation time 50145875 ps
CPU time 0.8 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:44:11 PM PDT 24
Peak memory 207708 kb
Host smart-1de1796f-96e6-468d-963f-0611a2a47bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015893823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2015893823
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.320175182
Short name T70
Test name
Test status
Simulation time 2902199296 ps
CPU time 58.27 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:45:09 PM PDT 24
Peak memory 257404 kb
Host smart-3b8819b6-42ee-4b71-8749-17cb8e3c5c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320175182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.320175182
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.875729975
Short name T207
Test name
Test status
Simulation time 21198535868 ps
CPU time 95.73 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:45:53 PM PDT 24
Peak memory 250240 kb
Host smart-b14a8173-33ae-4a28-a5f3-b1c8c478772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875729975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.875729975
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.108824517
Short name T451
Test name
Test status
Simulation time 3268322213 ps
CPU time 76.38 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 258436 kb
Host smart-96e93026-b079-4471-a86c-b1a4c88a5c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108824517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.108824517
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.949016860
Short name T281
Test name
Test status
Simulation time 2792634373 ps
CPU time 14.11 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 234796 kb
Host smart-48add24a-3281-4684-b917-9bd330bae87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949016860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.949016860
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1703743344
Short name T159
Test name
Test status
Simulation time 20105276441 ps
CPU time 85.5 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:45:45 PM PDT 24
Peak memory 252508 kb
Host smart-b88c8f5a-5712-4275-b510-5de2f2e7dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703743344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1703743344
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3593509617
Short name T437
Test name
Test status
Simulation time 2803260116 ps
CPU time 25.98 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:44:40 PM PDT 24
Peak memory 233756 kb
Host smart-1442e5f1-4028-431c-b3d5-fdaed2672c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593509617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3593509617
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3694573932
Short name T781
Test name
Test status
Simulation time 62715427502 ps
CPU time 61.31 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:45:12 PM PDT 24
Peak memory 225524 kb
Host smart-2a206ec5-d89b-40d1-8c6d-2de1e727da66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694573932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3694573932
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.610305784
Short name T729
Test name
Test status
Simulation time 1160983379 ps
CPU time 9.89 seconds
Started Aug 19 05:44:12 PM PDT 24
Finished Aug 19 05:44:22 PM PDT 24
Peak memory 233568 kb
Host smart-078fc356-e13e-4b76-bfcd-30e94962e3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610305784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.610305784
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.701109060
Short name T3
Test name
Test status
Simulation time 8520509232 ps
CPU time 19.45 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:44:30 PM PDT 24
Peak memory 233444 kb
Host smart-b0ecc1ee-832c-40a8-b463-211a979835f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701109060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.701109060
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1121344624
Short name T383
Test name
Test status
Simulation time 12459894816 ps
CPU time 11.02 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:22 PM PDT 24
Peak memory 223012 kb
Host smart-f6cf1ae3-ecea-4e4d-8cf9-90229d0268f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1121344624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1121344624
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1044887360
Short name T199
Test name
Test status
Simulation time 54758126173 ps
CPU time 203.07 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:47:37 PM PDT 24
Peak memory 273216 kb
Host smart-549fce4b-4d8a-49ed-9ce8-d2223c3d6562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044887360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1044887360
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1570192963
Short name T293
Test name
Test status
Simulation time 1273129535 ps
CPU time 21.33 seconds
Started Aug 19 05:44:12 PM PDT 24
Finished Aug 19 05:44:33 PM PDT 24
Peak memory 217432 kb
Host smart-374941fd-0a00-463a-85c4-d4721ed1e827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570192963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1570192963
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3160220429
Short name T972
Test name
Test status
Simulation time 885502675 ps
CPU time 5.56 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:17 PM PDT 24
Peak memory 217244 kb
Host smart-e29f9f64-bfee-4a97-be09-6e3f5e9efde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160220429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3160220429
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1274092819
Short name T875
Test name
Test status
Simulation time 111813557 ps
CPU time 1.4 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:19 PM PDT 24
Peak memory 217228 kb
Host smart-754a645c-60cf-4d40-b2d5-c765dfa3b45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274092819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1274092819
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2671387309
Short name T892
Test name
Test status
Simulation time 319800000 ps
CPU time 0.99 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:44:11 PM PDT 24
Peak memory 207936 kb
Host smart-07baffb0-17a3-44bc-8e83-975fbac1d32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671387309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2671387309
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1199329925
Short name T244
Test name
Test status
Simulation time 974813220 ps
CPU time 5.22 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:44:16 PM PDT 24
Peak memory 225396 kb
Host smart-7f576468-efeb-4213-bb72-e2bdb429d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199329925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1199329925
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2722401701
Short name T360
Test name
Test status
Simulation time 34070937 ps
CPU time 0.73 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:44:18 PM PDT 24
Peak memory 205728 kb
Host smart-9c44c2d5-7d4e-4b83-af75-a99132fec3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722401701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2722401701
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2938905982
Short name T376
Test name
Test status
Simulation time 442696556 ps
CPU time 7.92 seconds
Started Aug 19 05:44:14 PM PDT 24
Finished Aug 19 05:44:23 PM PDT 24
Peak memory 225360 kb
Host smart-03c970e0-5f0a-4e93-8f55-defbf095d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938905982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2938905982
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3181967328
Short name T387
Test name
Test status
Simulation time 29071631 ps
CPU time 0.78 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:12 PM PDT 24
Peak memory 207460 kb
Host smart-938b995b-8a31-4ded-999a-2c0b74a1e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181967328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3181967328
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2487634654
Short name T268
Test name
Test status
Simulation time 63914508879 ps
CPU time 249.11 seconds
Started Aug 19 05:44:10 PM PDT 24
Finished Aug 19 05:48:20 PM PDT 24
Peak memory 263776 kb
Host smart-6ba45b1d-711f-49f1-b788-d83c4c3e6998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487634654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2487634654
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1073013403
Short name T148
Test name
Test status
Simulation time 146199711679 ps
CPU time 148.68 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:46:44 PM PDT 24
Peak memory 251584 kb
Host smart-b363befc-1f43-4936-aba7-601ed4cfc58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073013403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1073013403
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3114446533
Short name T236
Test name
Test status
Simulation time 13103639270 ps
CPU time 63.98 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:45:21 PM PDT 24
Peak memory 224224 kb
Host smart-f4535e1f-9d1b-4017-8c41-0bf48a290f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114446533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3114446533
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.946556663
Short name T583
Test name
Test status
Simulation time 2626504334 ps
CPU time 11.5 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:44:29 PM PDT 24
Peak memory 235612 kb
Host smart-ed7d62fd-858a-4fc7-91b2-c47217f15170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946556663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.946556663
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.142560366
Short name T684
Test name
Test status
Simulation time 4934678211 ps
CPU time 55.32 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:45:12 PM PDT 24
Peak memory 250144 kb
Host smart-bb0fffec-b8cd-4619-9c2f-2095abe7ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142560366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.142560366
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4068518185
Short name T197
Test name
Test status
Simulation time 1547306829 ps
CPU time 14.73 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 233660 kb
Host smart-bb010ce8-4e4d-4205-9998-f5475e05f880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068518185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4068518185
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2535288183
Short name T976
Test name
Test status
Simulation time 792195738 ps
CPU time 12.11 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:30 PM PDT 24
Peak memory 225352 kb
Host smart-cea576ed-481c-4238-a199-0ea519826574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535288183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2535288183
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2248502391
Short name T854
Test name
Test status
Simulation time 1102237210 ps
CPU time 3.53 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:44:17 PM PDT 24
Peak memory 225332 kb
Host smart-9520d210-301e-40d5-b695-b9e03b7d9158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248502391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2248502391
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1614918521
Short name T381
Test name
Test status
Simulation time 258075274 ps
CPU time 5.08 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 233616 kb
Host smart-ea9c5a9c-2bd9-4c01-8b50-c3d2dbc1e83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614918521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1614918521
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.796452574
Short name T477
Test name
Test status
Simulation time 671222461 ps
CPU time 7.19 seconds
Started Aug 19 05:44:12 PM PDT 24
Finished Aug 19 05:44:19 PM PDT 24
Peak memory 221180 kb
Host smart-ceb89891-a393-4688-bfb4-5aa3f942b96f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=796452574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.796452574
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3958232529
Short name T279
Test name
Test status
Simulation time 118187641129 ps
CPU time 607.38 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 264836 kb
Host smart-277bd161-2a59-490a-90b4-d52913212235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958232529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3958232529
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.378187587
Short name T923
Test name
Test status
Simulation time 7212770400 ps
CPU time 19.81 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 217420 kb
Host smart-4748ba6c-58f6-45a2-a767-b18d1a49be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378187587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.378187587
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1841882379
Short name T838
Test name
Test status
Simulation time 1954319123 ps
CPU time 6.06 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:25 PM PDT 24
Peak memory 217232 kb
Host smart-b7131ede-3773-488f-966d-233ce11fb3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841882379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1841882379
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1159792473
Short name T310
Test name
Test status
Simulation time 150737147 ps
CPU time 6.97 seconds
Started Aug 19 05:44:13 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 217252 kb
Host smart-dd478632-a518-4a47-9de5-30318233021b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159792473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1159792473
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2016791845
Short name T77
Test name
Test status
Simulation time 258020944 ps
CPU time 0.79 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:12 PM PDT 24
Peak memory 206900 kb
Host smart-d4d84905-2bfc-4132-b657-40f6a4d39d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016791845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2016791845
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3157796517
Short name T233
Test name
Test status
Simulation time 23651823706 ps
CPU time 10.71 seconds
Started Aug 19 05:44:09 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 225484 kb
Host smart-9b2c9e03-5b3b-4535-9ddf-c70870bb310a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157796517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3157796517
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4041511192
Short name T349
Test name
Test status
Simulation time 41067898 ps
CPU time 0.73 seconds
Started Aug 19 05:44:23 PM PDT 24
Finished Aug 19 05:44:24 PM PDT 24
Peak memory 205396 kb
Host smart-556f7289-f81e-49d7-bb27-da39e1a9d19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041511192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4041511192
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2884718815
Short name T121
Test name
Test status
Simulation time 1145171202 ps
CPU time 6.29 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:25 PM PDT 24
Peak memory 225400 kb
Host smart-f82a1e3c-ac7e-4975-81d4-229a95e6be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884718815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2884718815
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2024211620
Short name T333
Test name
Test status
Simulation time 33135086 ps
CPU time 0.8 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:16 PM PDT 24
Peak memory 207460 kb
Host smart-0a257cbe-5f3e-4e73-9e2c-d1311625610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024211620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2024211620
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2584889178
Short name T983
Test name
Test status
Simulation time 1766054037 ps
CPU time 29.84 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 250020 kb
Host smart-bbd1fd96-43a8-4e06-ade7-69ed051ba9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584889178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2584889178
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1367573789
Short name T924
Test name
Test status
Simulation time 135737682938 ps
CPU time 283.94 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:49:01 PM PDT 24
Peak memory 258460 kb
Host smart-83db0cf2-5ea4-493d-8c33-211869480cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367573789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1367573789
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3576366188
Short name T560
Test name
Test status
Simulation time 1031883869 ps
CPU time 19.54 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 225408 kb
Host smart-f960bc78-0fcc-4389-b87e-cbd661639b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576366188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3576366188
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1407791727
Short name T491
Test name
Test status
Simulation time 106705786248 ps
CPU time 147.26 seconds
Started Aug 19 05:44:14 PM PDT 24
Finished Aug 19 05:46:41 PM PDT 24
Peak memory 251712 kb
Host smart-aae21d63-b321-4a6c-a949-394bdd60d696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407791727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1407791727
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3057049161
Short name T967
Test name
Test status
Simulation time 17671332368 ps
CPU time 17.61 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:36 PM PDT 24
Peak memory 225540 kb
Host smart-62925ab1-fe7e-43ad-9e72-b8f437afea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057049161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3057049161
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3398906837
Short name T820
Test name
Test status
Simulation time 6900189675 ps
CPU time 77.72 seconds
Started Aug 19 05:44:14 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 233748 kb
Host smart-8c73c118-0ee3-40f6-9cd1-c6c52ab036bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398906837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3398906837
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.104540991
Short name T788
Test name
Test status
Simulation time 1451339063 ps
CPU time 5.88 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:21 PM PDT 24
Peak memory 225376 kb
Host smart-8379ba58-16fe-4798-9bfd-9d177e70c5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104540991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.104540991
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2131076000
Short name T241
Test name
Test status
Simulation time 17016044189 ps
CPU time 5.45 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 225396 kb
Host smart-43988980-dffa-4ea2-a5b6-86530cd0dbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131076000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2131076000
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.991368973
Short name T836
Test name
Test status
Simulation time 1695312559 ps
CPU time 10.2 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:29 PM PDT 24
Peak memory 221156 kb
Host smart-b18af824-f824-47c8-aecc-e419302d0729
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=991368973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.991368973
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1532166547
Short name T19
Test name
Test status
Simulation time 49522850727 ps
CPU time 77.42 seconds
Started Aug 19 05:44:23 PM PDT 24
Finished Aug 19 05:45:41 PM PDT 24
Peak memory 241308 kb
Host smart-2c3e097a-a164-4462-8969-cef39fd3f0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532166547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1532166547
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3706939948
Short name T530
Test name
Test status
Simulation time 5037341754 ps
CPU time 36.19 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:51 PM PDT 24
Peak memory 217292 kb
Host smart-d886f328-c5c7-42b8-bf4f-e9cb8fb9f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706939948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3706939948
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3411876285
Short name T518
Test name
Test status
Simulation time 3484157015 ps
CPU time 6.39 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:22 PM PDT 24
Peak memory 217364 kb
Host smart-e230562a-65ef-4933-8136-af6b8856b12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411876285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3411876285
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4129274995
Short name T469
Test name
Test status
Simulation time 629555419 ps
CPU time 2.29 seconds
Started Aug 19 05:44:11 PM PDT 24
Finished Aug 19 05:44:13 PM PDT 24
Peak memory 217244 kb
Host smart-230244a5-7c70-40bd-96f0-eabceb0dec9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129274995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4129274995
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3314471276
Short name T1001
Test name
Test status
Simulation time 94157497 ps
CPU time 0.8 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:19 PM PDT 24
Peak memory 206860 kb
Host smart-f9934940-bb17-4df6-9d9c-382254ff44fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314471276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3314471276
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3705166741
Short name T474
Test name
Test status
Simulation time 323067731 ps
CPU time 4.38 seconds
Started Aug 19 05:44:15 PM PDT 24
Finished Aug 19 05:44:19 PM PDT 24
Peak memory 233644 kb
Host smart-187caa88-00a3-4042-884f-225da9333a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705166741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3705166741
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2957158969
Short name T47
Test name
Test status
Simulation time 12478258 ps
CPU time 0.73 seconds
Started Aug 19 05:44:26 PM PDT 24
Finished Aug 19 05:44:27 PM PDT 24
Peak memory 206308 kb
Host smart-a267dbaa-10bb-48a2-80fd-24131cf89d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957158969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2957158969
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1131745529
Short name T706
Test name
Test status
Simulation time 441785554 ps
CPU time 4.02 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:44:24 PM PDT 24
Peak memory 233624 kb
Host smart-6e3281f2-8730-44b5-a3c0-97b142d19d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131745529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1131745529
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2067495044
Short name T701
Test name
Test status
Simulation time 23086818 ps
CPU time 0.76 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:22 PM PDT 24
Peak memory 207408 kb
Host smart-e7456c24-da3a-4d27-b6ac-d45bb9468268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067495044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2067495044
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3323727643
Short name T778
Test name
Test status
Simulation time 1539771900 ps
CPU time 14.67 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:36 PM PDT 24
Peak memory 250008 kb
Host smart-818be34a-7963-4cf6-9a84-8ec1375cc933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323727643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3323727643
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.254444527
Short name T826
Test name
Test status
Simulation time 6700805250 ps
CPU time 75.45 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:45:37 PM PDT 24
Peak memory 254712 kb
Host smart-b5998da9-e922-45bb-860e-bf1753912dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254444527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.254444527
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1754220247
Short name T457
Test name
Test status
Simulation time 268644966257 ps
CPU time 188.97 seconds
Started Aug 19 05:44:17 PM PDT 24
Finished Aug 19 05:47:26 PM PDT 24
Peak memory 266188 kb
Host smart-7dea9e9a-53bc-405d-8cee-fbae380076fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754220247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1754220247
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1078152749
Short name T600
Test name
Test status
Simulation time 15583734054 ps
CPU time 77.73 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:45:37 PM PDT 24
Peak memory 257760 kb
Host smart-f8a8bcdc-f4f4-4a78-b44c-8e60f69c6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078152749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1078152749
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2810530344
Short name T190
Test name
Test status
Simulation time 41369220744 ps
CPU time 178.69 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:47:19 PM PDT 24
Peak memory 258276 kb
Host smart-7d917bf7-e62a-4990-bad3-75e462b6154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810530344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2810530344
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4188444168
Short name T452
Test name
Test status
Simulation time 3671410399 ps
CPU time 36.92 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:45:08 PM PDT 24
Peak memory 225500 kb
Host smart-a6616046-8256-4664-ba84-e02b75e63939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188444168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4188444168
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2435892951
Short name T411
Test name
Test status
Simulation time 33793911 ps
CPU time 2.34 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:44:23 PM PDT 24
Peak memory 233332 kb
Host smart-2dc77883-6141-4ec6-9730-fab95b5bbbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435892951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2435892951
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2200649777
Short name T245
Test name
Test status
Simulation time 25274297436 ps
CPU time 36.84 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:44:57 PM PDT 24
Peak memory 233620 kb
Host smart-e48d61f6-69aa-49c4-8898-816a1dd865a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200649777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2200649777
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.375816594
Short name T646
Test name
Test status
Simulation time 4990207414 ps
CPU time 11.76 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 225552 kb
Host smart-21f83b2f-f10c-442b-861c-0bbb70b4c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375816594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.375816594
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4045122204
Short name T756
Test name
Test status
Simulation time 3089659847 ps
CPU time 28.25 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 222968 kb
Host smart-f15013ea-50fe-4044-a7bb-8f1727a87fa8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045122204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4045122204
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1791059420
Short name T533
Test name
Test status
Simulation time 29367871846 ps
CPU time 296.92 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:49:27 PM PDT 24
Peak memory 255004 kb
Host smart-44a6da23-3809-4f28-8958-ad52118e69f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791059420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1791059420
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2910889781
Short name T291
Test name
Test status
Simulation time 15420624582 ps
CPU time 28.08 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:47 PM PDT 24
Peak memory 217296 kb
Host smart-852f3c33-9293-430f-b50d-c8c5b20da8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910889781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2910889781
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1192691007
Short name T904
Test name
Test status
Simulation time 2949027620 ps
CPU time 12.08 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 217136 kb
Host smart-4e975713-9fe2-4ac2-bbf6-40583320dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192691007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1192691007
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3440257231
Short name T60
Test name
Test status
Simulation time 49087869 ps
CPU time 1.18 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 208192 kb
Host smart-b190dbad-32a3-4fbf-8c18-c879f247256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440257231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3440257231
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3208133347
Short name T526
Test name
Test status
Simulation time 24885583 ps
CPU time 0.75 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 206916 kb
Host smart-d5112895-96fe-463a-92f0-119add56f08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208133347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3208133347
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3190127203
Short name T242
Test name
Test status
Simulation time 17918145089 ps
CPU time 6.2 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:27 PM PDT 24
Peak memory 225544 kb
Host smart-cc8805eb-21a6-4477-bac6-97c8fa3999c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190127203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3190127203
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.697203261
Short name T835
Test name
Test status
Simulation time 12860233 ps
CPU time 0.74 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:22 PM PDT 24
Peak memory 206308 kb
Host smart-03de7035-dfd8-4e1a-bb6e-96aae36295ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697203261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.697203261
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3440269293
Short name T1002
Test name
Test status
Simulation time 19220442491 ps
CPU time 11.31 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 233736 kb
Host smart-ecfdeb37-8053-4ada-a16d-e126656b7032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440269293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3440269293
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3284211417
Short name T364
Test name
Test status
Simulation time 64392457 ps
CPU time 0.77 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:19 PM PDT 24
Peak memory 207704 kb
Host smart-8c8f3172-fc9c-42dd-bcf1-147640b55014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284211417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3284211417
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3697369588
Short name T427
Test name
Test status
Simulation time 19830467192 ps
CPU time 166.31 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:47:05 PM PDT 24
Peak memory 253312 kb
Host smart-6e8b7f46-4085-437b-b9b9-bf31e81ed048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697369588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3697369588
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.106143704
Short name T679
Test name
Test status
Simulation time 26471281701 ps
CPU time 94.06 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:46:05 PM PDT 24
Peak memory 253340 kb
Host smart-4b42e2d4-c10e-4d79-a134-6b86b5f512cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106143704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.106143704
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3145658838
Short name T930
Test name
Test status
Simulation time 4903191280 ps
CPU time 32.2 seconds
Started Aug 19 05:44:22 PM PDT 24
Finished Aug 19 05:44:54 PM PDT 24
Peak memory 257716 kb
Host smart-112e0d00-a79a-413b-b63f-bfba4d0edef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145658838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3145658838
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.769999515
Short name T91
Test name
Test status
Simulation time 393197540 ps
CPU time 6.29 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:37 PM PDT 24
Peak memory 233660 kb
Host smart-ff5a224c-8518-4b1f-b3fc-8bd0e7b1ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769999515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.769999515
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1497590555
Short name T296
Test name
Test status
Simulation time 663157153 ps
CPU time 5.65 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:36 PM PDT 24
Peak memory 234500 kb
Host smart-9c857b62-76b7-4e0c-a953-6d626891e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497590555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1497590555
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.482720881
Short name T710
Test name
Test status
Simulation time 206317194 ps
CPU time 4.37 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:44:25 PM PDT 24
Peak memory 233652 kb
Host smart-4f15252b-1bda-4950-9009-2573620a9da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482720881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.482720881
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.315520780
Short name T837
Test name
Test status
Simulation time 3608303367 ps
CPU time 9.06 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:44:29 PM PDT 24
Peak memory 233772 kb
Host smart-f0b24d65-93d9-40df-96b0-50201a62560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315520780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.315520780
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.84216122
Short name T239
Test name
Test status
Simulation time 90527119 ps
CPU time 1.99 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:33 PM PDT 24
Peak memory 225180 kb
Host smart-4a0df477-6991-4558-8676-2136471430a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84216122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.84216122
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.450035487
Short name T350
Test name
Test status
Simulation time 4931850551 ps
CPU time 9.23 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:40 PM PDT 24
Peak memory 241324 kb
Host smart-5f8ec0f0-e8b3-4422-8564-bb5ce96f8165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450035487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.450035487
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1231752211
Short name T379
Test name
Test status
Simulation time 240779303 ps
CPU time 4.38 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:34 PM PDT 24
Peak memory 221628 kb
Host smart-7588ad90-63ed-426f-9b11-08cf604904e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231752211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1231752211
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3901022966
Short name T27
Test name
Test status
Simulation time 17015891636 ps
CPU time 257.98 seconds
Started Aug 19 05:44:20 PM PDT 24
Finished Aug 19 05:48:38 PM PDT 24
Peak memory 269608 kb
Host smart-6a94e147-7d55-42cf-93d0-0f6e013e9e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901022966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3901022966
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4226634844
Short name T806
Test name
Test status
Simulation time 1203833690 ps
CPU time 3.6 seconds
Started Aug 19 05:44:25 PM PDT 24
Finished Aug 19 05:44:29 PM PDT 24
Peak memory 217568 kb
Host smart-dc39f9ba-68a8-402f-9137-256caf311e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226634844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4226634844
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.725850350
Short name T294
Test name
Test status
Simulation time 26724667229 ps
CPU time 17.36 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:37 PM PDT 24
Peak memory 218824 kb
Host smart-2e99ffbd-9370-4257-90fa-4af5c8a28884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725850350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.725850350
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.736793956
Short name T61
Test name
Test status
Simulation time 110971554 ps
CPU time 0.9 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 206824 kb
Host smart-79e951c9-71a5-4cb6-82e9-54d7429245a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736793956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.736793956
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1083128228
Short name T992
Test name
Test status
Simulation time 100584253 ps
CPU time 1.02 seconds
Started Aug 19 05:44:18 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 207864 kb
Host smart-e7b67892-778c-465f-89f3-f1c8184b3a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083128228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1083128228
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2373603287
Short name T927
Test name
Test status
Simulation time 745980093 ps
CPU time 3 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:34 PM PDT 24
Peak memory 233620 kb
Host smart-c7407c11-7aaf-4919-82fd-1f977a102671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373603287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2373603287
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.276862052
Short name T324
Test name
Test status
Simulation time 32593366 ps
CPU time 0.75 seconds
Started Aug 19 05:42:55 PM PDT 24
Finished Aug 19 05:42:55 PM PDT 24
Peak memory 205716 kb
Host smart-eb961cf5-a14b-4490-98b2-047c559b3475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276862052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.276862052
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3680569751
Short name T606
Test name
Test status
Simulation time 411980490 ps
CPU time 7.81 seconds
Started Aug 19 05:43:01 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 233624 kb
Host smart-1d162900-11b2-4ebc-94fa-fea5610bb090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680569751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3680569751
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3380918915
Short name T385
Test name
Test status
Simulation time 19610807 ps
CPU time 0.87 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:42:53 PM PDT 24
Peak memory 207460 kb
Host smart-fc23cba2-be88-431c-89f3-aaee60aa1d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380918915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3380918915
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1729127444
Short name T269
Test name
Test status
Simulation time 35808517005 ps
CPU time 130.52 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:45:03 PM PDT 24
Peak memory 265728 kb
Host smart-9a83b48e-e13c-4370-bb54-a2608f87bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729127444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1729127444
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3740041988
Short name T524
Test name
Test status
Simulation time 8252811357 ps
CPU time 80.19 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:44:11 PM PDT 24
Peak memory 253204 kb
Host smart-17b27201-2990-4c98-8522-85f25659e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740041988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3740041988
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2387297593
Short name T841
Test name
Test status
Simulation time 180228697182 ps
CPU time 356.81 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:48:48 PM PDT 24
Peak memory 252084 kb
Host smart-5b65f85f-9807-48ba-bb7b-dba387110dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387297593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2387297593
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4161916102
Short name T202
Test name
Test status
Simulation time 142426385 ps
CPU time 3.93 seconds
Started Aug 19 05:42:53 PM PDT 24
Finished Aug 19 05:42:57 PM PDT 24
Peak memory 225468 kb
Host smart-3476da44-dc04-4799-be04-1fc85269e9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161916102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4161916102
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2063117462
Short name T189
Test name
Test status
Simulation time 113135624914 ps
CPU time 234.12 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:46:46 PM PDT 24
Peak memory 269872 kb
Host smart-5be1528a-3f74-42d6-9e9a-583d92036dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063117462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2063117462
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2068981206
Short name T557
Test name
Test status
Simulation time 74807655 ps
CPU time 2.11 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:42:53 PM PDT 24
Peak memory 225312 kb
Host smart-9f5e2115-546f-4c3f-827a-e0995282a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068981206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2068981206
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3499967355
Short name T473
Test name
Test status
Simulation time 8610829942 ps
CPU time 61.58 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:43:54 PM PDT 24
Peak memory 241916 kb
Host smart-b0bfbba8-f4f3-4b68-8cdb-551e1ed215f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499967355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3499967355
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.442671572
Short name T258
Test name
Test status
Simulation time 12824669986 ps
CPU time 19.61 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:43:10 PM PDT 24
Peak memory 230232 kb
Host smart-c49349d3-84a7-4de6-b2e2-4de258286d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442671572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
442671572
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1477905557
Short name T659
Test name
Test status
Simulation time 20053983079 ps
CPU time 27.08 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 236124 kb
Host smart-45c8477d-51b5-410c-8e87-15514b73f069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477905557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1477905557
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1789761546
Short name T512
Test name
Test status
Simulation time 3069382970 ps
CPU time 12.33 seconds
Started Aug 19 05:42:54 PM PDT 24
Finished Aug 19 05:43:06 PM PDT 24
Peak memory 219996 kb
Host smart-a3f242b4-bf7d-47ed-ae3c-4b9e5414f86d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1789761546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1789761546
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1329850491
Short name T56
Test name
Test status
Simulation time 100607638 ps
CPU time 1.17 seconds
Started Aug 19 05:42:53 PM PDT 24
Finished Aug 19 05:42:54 PM PDT 24
Peak memory 236724 kb
Host smart-d222e7a5-c220-4208-8a2a-72d858d7a4f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329850491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1329850491
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1447647684
Short name T188
Test name
Test status
Simulation time 255118370379 ps
CPU time 538.34 seconds
Started Aug 19 05:42:57 PM PDT 24
Finished Aug 19 05:51:55 PM PDT 24
Peak memory 284632 kb
Host smart-c85cefff-bcf6-41dd-bb9e-13b733d0c3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447647684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1447647684
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.660681622
Short name T810
Test name
Test status
Simulation time 14916581100 ps
CPU time 27.32 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 217548 kb
Host smart-eca23bae-7a55-4937-8130-e57487ab6f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660681622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.660681622
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1194150143
Short name T334
Test name
Test status
Simulation time 1522227928 ps
CPU time 4.32 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:42:56 PM PDT 24
Peak memory 217256 kb
Host smart-8e692937-8a62-4ccb-a9e2-dcd9ca85aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194150143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1194150143
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.371185669
Short name T766
Test name
Test status
Simulation time 15876691 ps
CPU time 0.92 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:42:52 PM PDT 24
Peak memory 207980 kb
Host smart-5c013f3f-359a-48f0-82b4-840a60174795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371185669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.371185669
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.105121626
Short name T395
Test name
Test status
Simulation time 75323968 ps
CPU time 0.77 seconds
Started Aug 19 05:42:49 PM PDT 24
Finished Aug 19 05:42:50 PM PDT 24
Peak memory 206900 kb
Host smart-3bf7a3f4-ffdc-4314-a2dc-dc72c732197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105121626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.105121626
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1312170852
Short name T947
Test name
Test status
Simulation time 473579467 ps
CPU time 2.88 seconds
Started Aug 19 05:42:47 PM PDT 24
Finished Aug 19 05:42:50 PM PDT 24
Peak memory 225260 kb
Host smart-dd1a2141-6cbb-497b-a3b6-ede36daca261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312170852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1312170852
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1309128700
Short name T358
Test name
Test status
Simulation time 30067714 ps
CPU time 0.7 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 205744 kb
Host smart-f6491f43-184a-4e4b-b14f-1e56e2fad69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309128700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1309128700
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3362063923
Short name T415
Test name
Test status
Simulation time 1210303516 ps
CPU time 7.6 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:38 PM PDT 24
Peak memory 233632 kb
Host smart-7e4008ff-2b13-4223-ab3d-62ff2db89978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362063923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3362063923
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4188100145
Short name T325
Test name
Test status
Simulation time 38737247 ps
CPU time 0.74 seconds
Started Aug 19 05:44:25 PM PDT 24
Finished Aug 19 05:44:26 PM PDT 24
Peak memory 206440 kb
Host smart-9491c6ea-acab-4f5a-b1ad-a9f85a0ea40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188100145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4188100145
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.181253056
Short name T267
Test name
Test status
Simulation time 60871472546 ps
CPU time 441.85 seconds
Started Aug 19 05:44:34 PM PDT 24
Finished Aug 19 05:51:56 PM PDT 24
Peak memory 255788 kb
Host smart-940fea63-ba68-4c72-9943-834a287d5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181253056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.181253056
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3611718010
Short name T263
Test name
Test status
Simulation time 68699654682 ps
CPU time 180.35 seconds
Started Aug 19 05:44:33 PM PDT 24
Finished Aug 19 05:47:33 PM PDT 24
Peak memory 255820 kb
Host smart-bbd7a5e5-665f-4253-a5d0-6ecd1fb348df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611718010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3611718010
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1326202747
Short name T261
Test name
Test status
Simulation time 4722820588 ps
CPU time 60.12 seconds
Started Aug 19 05:44:36 PM PDT 24
Finished Aug 19 05:45:36 PM PDT 24
Peak memory 257792 kb
Host smart-d364cff6-f792-4e72-a94b-1b5a79934cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326202747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1326202747
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1449487844
Short name T370
Test name
Test status
Simulation time 237441522 ps
CPU time 3.39 seconds
Started Aug 19 05:44:29 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 233660 kb
Host smart-239d5477-3a06-4a3b-8b04-ffa7e8fe04e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449487844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1449487844
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1035805416
Short name T157
Test name
Test status
Simulation time 5921288782 ps
CPU time 78.61 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:45:49 PM PDT 24
Peak memory 265512 kb
Host smart-a32387b7-b0da-4656-82df-e186ecb8a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035805416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1035805416
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1075992412
Short name T229
Test name
Test status
Simulation time 12610578315 ps
CPU time 9.65 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:40 PM PDT 24
Peak memory 225316 kb
Host smart-5b6a1b0e-22e7-45c8-942f-a3cdc7ce42c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075992412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1075992412
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3372699246
Short name T604
Test name
Test status
Simulation time 585101879 ps
CPU time 3.02 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:34 PM PDT 24
Peak memory 228732 kb
Host smart-ab40ecb6-69bc-4701-b373-5357b66feff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372699246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3372699246
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.200374451
Short name T819
Test name
Test status
Simulation time 1408152414 ps
CPU time 9.89 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 233580 kb
Host smart-8b73ea71-94ea-4203-b0b8-962b479aff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200374451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.200374451
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4246952997
Short name T662
Test name
Test status
Simulation time 27402168170 ps
CPU time 25.29 seconds
Started Aug 19 05:44:21 PM PDT 24
Finished Aug 19 05:44:46 PM PDT 24
Peak memory 233704 kb
Host smart-3caeec8e-36c3-48a1-bbd5-7369c8b840f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246952997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4246952997
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1721145185
Short name T137
Test name
Test status
Simulation time 230324817 ps
CPU time 4.44 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:44:36 PM PDT 24
Peak memory 223928 kb
Host smart-88bc1b44-d6f7-4812-af03-faadb8e910fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1721145185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1721145185
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2148506331
Short name T478
Test name
Test status
Simulation time 3610852299 ps
CPU time 17.43 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 217444 kb
Host smart-79c38441-670a-44dd-9766-ff4d543ee08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148506331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2148506331
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2969229558
Short name T486
Test name
Test status
Simulation time 6544471561 ps
CPU time 16.33 seconds
Started Aug 19 05:44:19 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 217340 kb
Host smart-811545f1-dd7f-4d61-98f9-3eeef9413362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969229558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2969229558
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1099372151
Short name T962
Test name
Test status
Simulation time 456913721 ps
CPU time 2.12 seconds
Started Aug 19 05:44:22 PM PDT 24
Finished Aug 19 05:44:24 PM PDT 24
Peak memory 217244 kb
Host smart-610b72bf-7253-4463-b88b-6b96d57e9a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099372151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1099372151
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3239221278
Short name T747
Test name
Test status
Simulation time 11086731 ps
CPU time 0.71 seconds
Started Aug 19 05:44:27 PM PDT 24
Finished Aug 19 05:44:28 PM PDT 24
Peak memory 206476 kb
Host smart-1b7ca2b9-efda-4380-9a98-87724d7b311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239221278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3239221278
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1368939652
Short name T118
Test name
Test status
Simulation time 3317069885 ps
CPU time 14.55 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:46 PM PDT 24
Peak memory 235760 kb
Host smart-e2a53f28-13c2-4dcf-ac90-54fddb7fea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368939652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1368939652
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1827216534
Short name T389
Test name
Test status
Simulation time 49442354 ps
CPU time 0.74 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 206668 kb
Host smart-e30d42c5-6575-482f-b65b-32814b544d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827216534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1827216534
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.73757839
Short name T247
Test name
Test status
Simulation time 232891461 ps
CPU time 2.86 seconds
Started Aug 19 05:44:28 PM PDT 24
Finished Aug 19 05:44:31 PM PDT 24
Peak memory 225436 kb
Host smart-2e986edd-6096-4acf-932d-171e43055249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73757839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.73757839
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3411038853
Short name T419
Test name
Test status
Simulation time 18852117 ps
CPU time 0.82 seconds
Started Aug 19 05:44:33 PM PDT 24
Finished Aug 19 05:44:34 PM PDT 24
Peak memory 207448 kb
Host smart-25eb077d-3525-4ed8-9a54-ae5de1bc60f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411038853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3411038853
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.4022567671
Short name T209
Test name
Test status
Simulation time 64048539234 ps
CPU time 262.83 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:48:55 PM PDT 24
Peak memory 266528 kb
Host smart-064317cc-8c50-42a0-9915-18f3e775c50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022567671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4022567671
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3791052210
Short name T692
Test name
Test status
Simulation time 384273385 ps
CPU time 8.06 seconds
Started Aug 19 05:44:35 PM PDT 24
Finished Aug 19 05:44:44 PM PDT 24
Peak memory 234672 kb
Host smart-797aac9a-e740-4c72-bd35-a8be1785eb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791052210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3791052210
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2354947643
Short name T264
Test name
Test status
Simulation time 10330829604 ps
CPU time 122.06 seconds
Started Aug 19 05:44:36 PM PDT 24
Finished Aug 19 05:46:38 PM PDT 24
Peak memory 258328 kb
Host smart-ffef9269-208f-499d-9084-c6454263e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354947643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2354947643
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3245045026
Short name T283
Test name
Test status
Simulation time 1450475920 ps
CPU time 7.66 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:39 PM PDT 24
Peak memory 239204 kb
Host smart-684cbe70-34f8-4889-93ca-2cf693a2d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245045026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3245045026
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2825262619
Short name T715
Test name
Test status
Simulation time 3524266199 ps
CPU time 50.59 seconds
Started Aug 19 05:44:35 PM PDT 24
Finished Aug 19 05:45:26 PM PDT 24
Peak memory 250148 kb
Host smart-35aacd3a-8176-4ca4-b2b7-2e41ea4ea4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825262619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2825262619
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2879654924
Short name T224
Test name
Test status
Simulation time 12023889252 ps
CPU time 15.16 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:44:47 PM PDT 24
Peak memory 225508 kb
Host smart-33d75eee-8ec8-493f-a22a-4fd6bf54ddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879654924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2879654924
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.727294481
Short name T886
Test name
Test status
Simulation time 33137686844 ps
CPU time 45.27 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 250148 kb
Host smart-49c91ad2-06ad-4e38-b956-43e8d0393d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727294481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.727294481
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2398171456
Short name T33
Test name
Test status
Simulation time 4015122982 ps
CPU time 8.63 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:38 PM PDT 24
Peak memory 225384 kb
Host smart-4b2acd65-de93-4e8b-9e4e-13dd5e6d8686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398171456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2398171456
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.589004506
Short name T816
Test name
Test status
Simulation time 31789227488 ps
CPU time 12.32 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:42 PM PDT 24
Peak memory 233668 kb
Host smart-96e8aad8-a3f6-4034-8282-b8bb7a801816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589004506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.589004506
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3324597196
Short name T329
Test name
Test status
Simulation time 781440878 ps
CPU time 9.94 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:41 PM PDT 24
Peak memory 221428 kb
Host smart-701d07cf-642b-4ff9-aa05-3d215703808c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3324597196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3324597196
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1748297068
Short name T529
Test name
Test status
Simulation time 15137691976 ps
CPU time 37.46 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:45:09 PM PDT 24
Peak memory 217432 kb
Host smart-82574974-3ae4-4030-a107-8b3f840b3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748297068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1748297068
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1261276146
Short name T455
Test name
Test status
Simulation time 36559677629 ps
CPU time 24.2 seconds
Started Aug 19 05:44:33 PM PDT 24
Finished Aug 19 05:44:57 PM PDT 24
Peak memory 217400 kb
Host smart-f005386e-5f18-41f8-a47d-dc32aa65b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261276146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1261276146
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3470372958
Short name T642
Test name
Test status
Simulation time 222509735 ps
CPU time 2.67 seconds
Started Aug 19 05:44:33 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 217268 kb
Host smart-e97f21f0-6766-4f8b-bb78-cbbbc62d2126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470372958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3470372958
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.611667214
Short name T849
Test name
Test status
Simulation time 192942281 ps
CPU time 0.96 seconds
Started Aug 19 05:44:34 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 206920 kb
Host smart-7e9ce78c-37c6-4ebc-a488-0738a65f43b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611667214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.611667214
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2970247845
Short name T877
Test name
Test status
Simulation time 12704623207 ps
CPU time 21.25 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:44:53 PM PDT 24
Peak memory 240524 kb
Host smart-8eaa7f33-0158-4541-90f8-23715b03551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970247845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2970247845
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.870513737
Short name T393
Test name
Test status
Simulation time 52313200 ps
CPU time 0.72 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:44:41 PM PDT 24
Peak memory 205740 kb
Host smart-71112064-d255-4182-bc7a-73df8e25ef39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870513737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.870513737
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3750529455
Short name T80
Test name
Test status
Simulation time 230146666 ps
CPU time 2.58 seconds
Started Aug 19 05:44:37 PM PDT 24
Finished Aug 19 05:44:40 PM PDT 24
Peak memory 233640 kb
Host smart-b4608ffe-b7a7-4dea-841d-960d3dede488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750529455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3750529455
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2987065066
Short name T698
Test name
Test status
Simulation time 16163476 ps
CPU time 0.79 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:44:33 PM PDT 24
Peak memory 207776 kb
Host smart-0a3ef2b6-71ac-4edb-8680-0e86630290ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987065066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2987065066
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.456218773
Short name T639
Test name
Test status
Simulation time 55397994145 ps
CPU time 92.87 seconds
Started Aug 19 05:44:37 PM PDT 24
Finished Aug 19 05:46:10 PM PDT 24
Peak memory 237720 kb
Host smart-1ee0124c-85bd-4d83-bbc2-b59a15b9197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456218773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.456218773
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1485056104
Short name T887
Test name
Test status
Simulation time 29353377693 ps
CPU time 259.31 seconds
Started Aug 19 05:44:45 PM PDT 24
Finished Aug 19 05:49:05 PM PDT 24
Peak memory 266364 kb
Host smart-d1d2906a-5dad-40c5-b8e4-9fb7a2aba4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485056104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1485056104
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1597041707
Short name T128
Test name
Test status
Simulation time 30433881595 ps
CPU time 122.12 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:46:41 PM PDT 24
Peak memory 266292 kb
Host smart-86405b3c-f61b-401d-9d25-42d6e37584f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597041707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1597041707
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.19466018
Short name T373
Test name
Test status
Simulation time 265504434 ps
CPU time 5.16 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:44:46 PM PDT 24
Peak memory 233596 kb
Host smart-c2ac9a61-8c7c-4bf1-bd75-76a8461a7cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19466018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.19466018
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.296251844
Short name T609
Test name
Test status
Simulation time 13467544 ps
CPU time 0.78 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:44:41 PM PDT 24
Peak memory 216664 kb
Host smart-a632c491-ec94-4a05-89aa-484ec63e6a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296251844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.296251844
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3995646323
Short name T933
Test name
Test status
Simulation time 583502653 ps
CPU time 2.79 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:44:42 PM PDT 24
Peak memory 225380 kb
Host smart-a3557b5c-3fb9-4973-a2f5-41ea2646f22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995646323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3995646323
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.33174827
Short name T161
Test name
Test status
Simulation time 1067994872 ps
CPU time 10.2 seconds
Started Aug 19 05:44:38 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 233580 kb
Host smart-b55f3ed7-8e2b-4736-98e3-b63cca15dde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33174827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.33174827
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2694980614
Short name T401
Test name
Test status
Simulation time 5237615677 ps
CPU time 13.79 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:44:45 PM PDT 24
Peak memory 241540 kb
Host smart-a7411259-b286-494c-bcd7-cf8d5e86ca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694980614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2694980614
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.608321314
Short name T907
Test name
Test status
Simulation time 58507796 ps
CPU time 2.57 seconds
Started Aug 19 05:44:32 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 233636 kb
Host smart-91cf55f2-71a6-4787-9937-9577fe9542bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608321314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.608321314
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2530573507
Short name T894
Test name
Test status
Simulation time 996083662 ps
CPU time 3.76 seconds
Started Aug 19 05:44:42 PM PDT 24
Finished Aug 19 05:44:46 PM PDT 24
Peak memory 221000 kb
Host smart-0ee988c8-fb43-43aa-8b7b-5521aa8127a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2530573507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2530573507
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2112569391
Short name T989
Test name
Test status
Simulation time 18877711983 ps
CPU time 258.61 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:48:59 PM PDT 24
Peak memory 268208 kb
Host smart-31b25a83-f866-4db3-8101-2053d691eafb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112569391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2112569391
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3593429665
Short name T444
Test name
Test status
Simulation time 18193958811 ps
CPU time 19.12 seconds
Started Aug 19 05:44:28 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 217352 kb
Host smart-a7e70e57-968b-4656-9c7f-079aa7368d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593429665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3593429665
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2008870565
Short name T865
Test name
Test status
Simulation time 5093735130 ps
CPU time 16.99 seconds
Started Aug 19 05:44:30 PM PDT 24
Finished Aug 19 05:44:47 PM PDT 24
Peak memory 217308 kb
Host smart-92040c0b-c8c5-48f1-9bf0-89a670814ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008870565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2008870565
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1157447880
Short name T920
Test name
Test status
Simulation time 508125223 ps
CPU time 1.97 seconds
Started Aug 19 05:44:33 PM PDT 24
Finished Aug 19 05:44:35 PM PDT 24
Peak memory 217192 kb
Host smart-38854501-7bde-4b91-a81f-633181f1bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157447880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1157447880
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2007934640
Short name T543
Test name
Test status
Simulation time 431585802 ps
CPU time 0.81 seconds
Started Aug 19 05:44:31 PM PDT 24
Finished Aug 19 05:44:32 PM PDT 24
Peak memory 206864 kb
Host smart-328e8bed-41d4-4b8e-95ff-252e3212ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007934640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2007934640
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4234193342
Short name T331
Test name
Test status
Simulation time 9537819754 ps
CPU time 20.49 seconds
Started Aug 19 05:44:41 PM PDT 24
Finished Aug 19 05:45:02 PM PDT 24
Peak memory 233748 kb
Host smart-1f62abeb-c44f-460b-8347-2e624b24945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234193342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4234193342
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4220451314
Short name T741
Test name
Test status
Simulation time 34498113 ps
CPU time 0.72 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:44:39 PM PDT 24
Peak memory 206644 kb
Host smart-f6eed272-32ed-45fe-a120-4162439dcece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220451314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4220451314
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3567874780
Short name T643
Test name
Test status
Simulation time 512789759 ps
CPU time 6.77 seconds
Started Aug 19 05:44:36 PM PDT 24
Finished Aug 19 05:44:43 PM PDT 24
Peak memory 225420 kb
Host smart-c96e932a-5c62-47aa-b9e1-0338ae41507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567874780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3567874780
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2385329203
Short name T632
Test name
Test status
Simulation time 30036946 ps
CPU time 0.77 seconds
Started Aug 19 05:44:42 PM PDT 24
Finished Aug 19 05:44:43 PM PDT 24
Peak memory 207764 kb
Host smart-0daf32d8-597c-47fd-88a2-f68d730a588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385329203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2385329203
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4017345691
Short name T179
Test name
Test status
Simulation time 405001631 ps
CPU time 7.66 seconds
Started Aug 19 05:44:37 PM PDT 24
Finished Aug 19 05:44:44 PM PDT 24
Peak memory 225416 kb
Host smart-3f82013d-c145-4e55-8c17-78099c60f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017345691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4017345691
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3867212197
Short name T523
Test name
Test status
Simulation time 118252328421 ps
CPU time 225.87 seconds
Started Aug 19 05:44:38 PM PDT 24
Finished Aug 19 05:48:24 PM PDT 24
Peak memory 258412 kb
Host smart-e6fefa23-93ad-4814-8e4d-b291f1a6b5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867212197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3867212197
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.696058210
Short name T285
Test name
Test status
Simulation time 755169877 ps
CPU time 13.28 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 225424 kb
Host smart-a87db288-fb5e-42ed-96d9-09e3a75685ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696058210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.696058210
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3524945296
Short name T35
Test name
Test status
Simulation time 64555768271 ps
CPU time 268.39 seconds
Started Aug 19 05:44:43 PM PDT 24
Finished Aug 19 05:49:12 PM PDT 24
Peak memory 272928 kb
Host smart-90cdce85-1d4b-4967-81a4-bef448467e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524945296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3524945296
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1213084473
Short name T804
Test name
Test status
Simulation time 1153372643 ps
CPU time 17.13 seconds
Started Aug 19 05:44:45 PM PDT 24
Finished Aug 19 05:45:02 PM PDT 24
Peak memory 219700 kb
Host smart-3499351c-766f-4b36-976f-43aef50ec739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213084473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1213084473
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1494339111
Short name T687
Test name
Test status
Simulation time 50857111502 ps
CPU time 116.64 seconds
Started Aug 19 05:44:42 PM PDT 24
Finished Aug 19 05:46:39 PM PDT 24
Peak memory 233704 kb
Host smart-19f9897c-6bf5-41a7-94cf-87858498c676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494339111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1494339111
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3084190962
Short name T944
Test name
Test status
Simulation time 123141836 ps
CPU time 2.57 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:44:42 PM PDT 24
Peak memory 233528 kb
Host smart-4c904e13-7574-4811-a3b6-699b79b1fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084190962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3084190962
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1444046603
Short name T873
Test name
Test status
Simulation time 682947013 ps
CPU time 4.4 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:44:44 PM PDT 24
Peak memory 225368 kb
Host smart-060c5d5a-3a67-4b95-9c38-f832ed20e3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444046603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1444046603
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3698313201
Short name T647
Test name
Test status
Simulation time 1952154549 ps
CPU time 11.57 seconds
Started Aug 19 05:44:40 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 221336 kb
Host smart-740bb419-b57e-4e6d-b8bc-3e330e55151e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3698313201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3698313201
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.801476930
Short name T253
Test name
Test status
Simulation time 59349600524 ps
CPU time 168.01 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:47:27 PM PDT 24
Peak memory 266624 kb
Host smart-022ec025-b281-40e5-a102-03ab916eb5df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801476930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.801476930
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3823384805
Short name T622
Test name
Test status
Simulation time 804951397 ps
CPU time 13.41 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 217464 kb
Host smart-c857ca14-4800-4cca-8308-687f4f1efafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823384805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3823384805
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3606508421
Short name T316
Test name
Test status
Simulation time 5984850482 ps
CPU time 15.56 seconds
Started Aug 19 05:44:39 PM PDT 24
Finished Aug 19 05:44:54 PM PDT 24
Peak memory 217308 kb
Host smart-83b9f357-e1c5-40c2-998c-d44f70396437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606508421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3606508421
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3035049037
Short name T463
Test name
Test status
Simulation time 223116755 ps
CPU time 2.14 seconds
Started Aug 19 05:44:46 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 217216 kb
Host smart-bddf3b7c-6a6c-4494-befa-d0f4aa3761eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035049037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3035049037
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.401376120
Short name T869
Test name
Test status
Simulation time 87178732 ps
CPU time 0.78 seconds
Started Aug 19 05:44:38 PM PDT 24
Finished Aug 19 05:44:39 PM PDT 24
Peak memory 206888 kb
Host smart-c4074517-6290-4d15-b447-b197b39bc82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401376120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.401376120
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.572071261
Short name T843
Test name
Test status
Simulation time 6681681678 ps
CPU time 6.84 seconds
Started Aug 19 05:44:42 PM PDT 24
Finished Aug 19 05:44:49 PM PDT 24
Peak memory 225476 kb
Host smart-524868bc-6ddc-4c0b-b18a-f037fa3ed8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572071261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.572071261
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.300189855
Short name T322
Test name
Test status
Simulation time 24948708 ps
CPU time 0.72 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:44:49 PM PDT 24
Peak memory 205700 kb
Host smart-0bbfbaf7-198f-4214-b8ad-7cc9cff59091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300189855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.300189855
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1076770047
Short name T213
Test name
Test status
Simulation time 130968293 ps
CPU time 3.85 seconds
Started Aug 19 05:44:50 PM PDT 24
Finished Aug 19 05:44:54 PM PDT 24
Peak memory 225256 kb
Host smart-041c4d66-2514-47e9-b47f-d0b5bcc46137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076770047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1076770047
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3002963170
Short name T696
Test name
Test status
Simulation time 13553240 ps
CPU time 0.78 seconds
Started Aug 19 05:44:41 PM PDT 24
Finished Aug 19 05:44:42 PM PDT 24
Peak memory 206736 kb
Host smart-840b96e8-faa7-4ab8-a84c-80dea0ec1011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002963170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3002963170
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2017679588
Short name T29
Test name
Test status
Simulation time 105332617798 ps
CPU time 210.17 seconds
Started Aug 19 05:44:50 PM PDT 24
Finished Aug 19 05:48:20 PM PDT 24
Peak memory 250216 kb
Host smart-16c530e1-dbac-4c65-818c-c0964452fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017679588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2017679588
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1446512191
Short name T974
Test name
Test status
Simulation time 13588978448 ps
CPU time 100.43 seconds
Started Aug 19 05:44:52 PM PDT 24
Finished Aug 19 05:46:33 PM PDT 24
Peak memory 250264 kb
Host smart-5d7db1ff-24af-4c2c-a987-100ea54f83d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446512191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1446512191
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.32502331
Short name T521
Test name
Test status
Simulation time 173317470 ps
CPU time 2.69 seconds
Started Aug 19 05:44:50 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 225428 kb
Host smart-47b69df1-7fea-439a-80d7-17fdbbc05654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32502331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.32502331
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3342631197
Short name T628
Test name
Test status
Simulation time 222906198 ps
CPU time 3.16 seconds
Started Aug 19 05:44:51 PM PDT 24
Finished Aug 19 05:44:55 PM PDT 24
Peak memory 233636 kb
Host smart-7b025ecf-7940-4654-8592-2ecc7222f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342631197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3342631197
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.670199690
Short name T417
Test name
Test status
Simulation time 40916287140 ps
CPU time 93 seconds
Started Aug 19 05:44:55 PM PDT 24
Finished Aug 19 05:46:28 PM PDT 24
Peak memory 249964 kb
Host smart-a185a528-a9f9-4955-9b4d-b54ef896a22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670199690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.670199690
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1015810396
Short name T497
Test name
Test status
Simulation time 3722842642 ps
CPU time 5.77 seconds
Started Aug 19 05:44:51 PM PDT 24
Finished Aug 19 05:44:57 PM PDT 24
Peak memory 233728 kb
Host smart-96fdafbb-c0ff-4a1f-bbd6-e7b2274c5a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015810396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1015810396
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3725785890
Short name T748
Test name
Test status
Simulation time 864960769 ps
CPU time 4.48 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 233648 kb
Host smart-a70ea4ce-a8df-4c8b-ad02-9d6b6f23c311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725785890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3725785890
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4234790498
Short name T762
Test name
Test status
Simulation time 1433786718 ps
CPU time 21.26 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:45:10 PM PDT 24
Peak memory 219864 kb
Host smart-c448a229-49fb-4f34-929d-0d6f2f9e6296
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4234790498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4234790498
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.341329358
Short name T761
Test name
Test status
Simulation time 64057950 ps
CPU time 1.11 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:44:49 PM PDT 24
Peak memory 208588 kb
Host smart-e58344c8-463f-45cb-96f2-e970c09470d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341329358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.341329358
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1658607845
Short name T846
Test name
Test status
Simulation time 5571567313 ps
CPU time 31.01 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 217308 kb
Host smart-7989536f-c541-4436-b089-f2326a1ee768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658607845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1658607845
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.807267689
Short name T787
Test name
Test status
Simulation time 8364267410 ps
CPU time 5.49 seconds
Started Aug 19 05:44:38 PM PDT 24
Finished Aug 19 05:44:43 PM PDT 24
Peak memory 217688 kb
Host smart-29f85fa7-5d79-4f03-b9c7-cc0258da1e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807267689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.807267689
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3421170196
Short name T935
Test name
Test status
Simulation time 804899982 ps
CPU time 3.63 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 217228 kb
Host smart-036f96c6-dd09-4033-9478-4471ec22014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421170196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3421170196
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2812476171
Short name T803
Test name
Test status
Simulation time 211937584 ps
CPU time 0.92 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:44:50 PM PDT 24
Peak memory 207920 kb
Host smart-11e06bf5-db3d-42c8-aeb6-58c2eb41df17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812476171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2812476171
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1780909540
Short name T328
Test name
Test status
Simulation time 146548015 ps
CPU time 2.95 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 237404 kb
Host smart-7719e5f4-9922-4c9a-ac84-b2c0d49e4d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780909540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1780909540
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4091628068
Short name T996
Test name
Test status
Simulation time 13286635 ps
CPU time 0.74 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 206656 kb
Host smart-99faa479-08e5-450e-8b5c-c78b6f376539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091628068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4091628068
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1098817594
Short name T217
Test name
Test status
Simulation time 682602800 ps
CPU time 3.54 seconds
Started Aug 19 05:44:50 PM PDT 24
Finished Aug 19 05:44:53 PM PDT 24
Peak memory 225400 kb
Host smart-d951b6bc-5ce1-4cfe-992a-fde6c64fa81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098817594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1098817594
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1061478756
Short name T912
Test name
Test status
Simulation time 72270578 ps
CPU time 0.77 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:44:50 PM PDT 24
Peak memory 206348 kb
Host smart-b8120cb8-03bd-4167-908f-9d98cbf5d5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061478756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1061478756
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3732034921
Short name T274
Test name
Test status
Simulation time 27904728946 ps
CPU time 215.31 seconds
Started Aug 19 05:44:50 PM PDT 24
Finished Aug 19 05:48:25 PM PDT 24
Peak memory 250148 kb
Host smart-3505e451-482d-48e6-9b79-2dfb155e18c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732034921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3732034921
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1236435814
Short name T416
Test name
Test status
Simulation time 6066547328 ps
CPU time 76.12 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:46:05 PM PDT 24
Peak memory 257200 kb
Host smart-9b2b8082-f9f2-4411-9ac5-592d5f8edc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236435814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1236435814
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.471604960
Short name T840
Test name
Test status
Simulation time 45213779976 ps
CPU time 112.36 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:46:41 PM PDT 24
Peak memory 258316 kb
Host smart-01362d3e-078d-4ac9-8d5c-06995688ea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471604960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.471604960
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2169048217
Short name T298
Test name
Test status
Simulation time 56883837 ps
CPU time 2.02 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:44:49 PM PDT 24
Peak memory 225084 kb
Host smart-eef36fb4-b447-4afc-a3c6-e64872315def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169048217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2169048217
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2474324226
Short name T832
Test name
Test status
Simulation time 4387303414 ps
CPU time 30.56 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 241080 kb
Host smart-e0a75bed-2c5c-4dee-a7ef-7623c194ba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474324226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2474324226
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1333805336
Short name T58
Test name
Test status
Simulation time 121806628 ps
CPU time 2.67 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 233628 kb
Host smart-69839609-2f41-44ce-a3df-d4962cf9d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333805336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1333805336
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3502167426
Short name T553
Test name
Test status
Simulation time 3542646482 ps
CPU time 11.11 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:45:00 PM PDT 24
Peak memory 233772 kb
Host smart-95f5122c-6b2d-4f0e-a1c0-e6cdecf8a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502167426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3502167426
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2269864025
Short name T365
Test name
Test status
Simulation time 2133965274 ps
CPU time 17.59 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:45:05 PM PDT 24
Peak memory 221052 kb
Host smart-4e698e7b-c77f-4172-b0e3-3464c3f85195
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2269864025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2269864025
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3822315707
Short name T143
Test name
Test status
Simulation time 47898784 ps
CPU time 0.97 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:44:50 PM PDT 24
Peak memory 208372 kb
Host smart-4dd05d43-d130-40e4-8758-c9d7a7516c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822315707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3822315707
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3952223627
Short name T573
Test name
Test status
Simulation time 6978208493 ps
CPU time 29.32 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 217252 kb
Host smart-5f193606-760d-43d2-ab61-3fd2e5eb7ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952223627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3952223627
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3598325202
Short name T645
Test name
Test status
Simulation time 5158097315 ps
CPU time 14.54 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:45:03 PM PDT 24
Peak memory 217368 kb
Host smart-e0c6a3c6-7100-4bbb-8cb4-7041e17b5ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598325202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3598325202
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3971609895
Short name T313
Test name
Test status
Simulation time 48969812 ps
CPU time 1.28 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:44:49 PM PDT 24
Peak memory 216960 kb
Host smart-a6c157b0-8b37-4d91-9152-cc774113e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971609895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3971609895
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.640182641
Short name T424
Test name
Test status
Simulation time 24609525 ps
CPU time 0.83 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:44:48 PM PDT 24
Peak memory 206820 kb
Host smart-91724033-13ef-4bb4-b104-20121471f7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640182641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.640182641
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2662036900
Short name T705
Test name
Test status
Simulation time 18945833958 ps
CPU time 16.87 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:45:04 PM PDT 24
Peak memory 240420 kb
Host smart-2aff5a87-721a-46dd-8652-1ea20cb87269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662036900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2662036900
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3265822788
Short name T475
Test name
Test status
Simulation time 42239593 ps
CPU time 0.74 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:44:58 PM PDT 24
Peak memory 205712 kb
Host smart-153accf5-d368-43c7-82e7-979150ea2c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265822788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3265822788
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3102280658
Short name T14
Test name
Test status
Simulation time 371176600 ps
CPU time 4.01 seconds
Started Aug 19 05:45:03 PM PDT 24
Finished Aug 19 05:45:07 PM PDT 24
Peak memory 233548 kb
Host smart-a7c49d25-c499-416d-9f4a-0804b6e55157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102280658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3102280658
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4188336790
Short name T429
Test name
Test status
Simulation time 17177657 ps
CPU time 0.78 seconds
Started Aug 19 05:44:48 PM PDT 24
Finished Aug 19 05:44:49 PM PDT 24
Peak memory 207448 kb
Host smart-130eeedf-c333-4003-9bc2-99e171638421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188336790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4188336790
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2704098229
Short name T182
Test name
Test status
Simulation time 7761147982 ps
CPU time 104.12 seconds
Started Aug 19 05:45:01 PM PDT 24
Finished Aug 19 05:46:45 PM PDT 24
Peak memory 256568 kb
Host smart-db27ec0b-9fe4-4d68-9790-73fca3586d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704098229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2704098229
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2411023320
Short name T410
Test name
Test status
Simulation time 4915349429 ps
CPU time 34.4 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:34 PM PDT 24
Peak memory 250136 kb
Host smart-3320ee85-ba97-4e92-93b4-2c25f3818f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411023320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2411023320
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1220642932
Short name T881
Test name
Test status
Simulation time 16722607915 ps
CPU time 26.77 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:27 PM PDT 24
Peak memory 225492 kb
Host smart-28c44b3f-a3b1-4f23-95b3-15e23c091554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220642932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1220642932
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1101714943
Short name T532
Test name
Test status
Simulation time 310402740 ps
CPU time 4.49 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:45:02 PM PDT 24
Peak memory 225432 kb
Host smart-4939cd48-0d57-4df0-8970-61e3a97256dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101714943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1101714943
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.790008152
Short name T680
Test name
Test status
Simulation time 49924256652 ps
CPU time 102.27 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:46:42 PM PDT 24
Peak memory 253936 kb
Host smart-17cd41c7-3796-4d7f-aa79-4f298c60c195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790008152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.790008152
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4272438240
Short name T165
Test name
Test status
Simulation time 970842310 ps
CPU time 7.58 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:45:04 PM PDT 24
Peak memory 225328 kb
Host smart-9305b9b3-dd2d-45f8-9037-d2e4f2a6a3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272438240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4272438240
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3221374747
Short name T483
Test name
Test status
Simulation time 8698246507 ps
CPU time 66.31 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:46:05 PM PDT 24
Peak memory 241820 kb
Host smart-5ae4de28-b087-4920-bca5-313011bfb9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221374747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3221374747
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1735493329
Short name T665
Test name
Test status
Simulation time 269439762 ps
CPU time 2.95 seconds
Started Aug 19 05:45:05 PM PDT 24
Finished Aug 19 05:45:08 PM PDT 24
Peak memory 233564 kb
Host smart-53bb94c2-a3e9-4da3-808c-0885fdc4658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735493329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1735493329
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2030376864
Short name T870
Test name
Test status
Simulation time 8046596508 ps
CPU time 8.06 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:09 PM PDT 24
Peak memory 233768 kb
Host smart-cec0cbd0-fedd-4758-908c-a5b46000e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030376864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2030376864
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2555030053
Short name T481
Test name
Test status
Simulation time 299246755 ps
CPU time 4.37 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:05 PM PDT 24
Peak memory 224076 kb
Host smart-3787e7a6-34c7-4af0-bc5b-cd5444f20625
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2555030053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2555030053
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.732616985
Short name T378
Test name
Test status
Simulation time 3188092778 ps
CPU time 9.48 seconds
Started Aug 19 05:44:47 PM PDT 24
Finished Aug 19 05:44:57 PM PDT 24
Peak memory 217376 kb
Host smart-fd7cb725-fa86-44a6-968c-19a396bb0f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732616985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.732616985
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1961799292
Short name T332
Test name
Test status
Simulation time 3001671870 ps
CPU time 3.34 seconds
Started Aug 19 05:44:49 PM PDT 24
Finished Aug 19 05:44:53 PM PDT 24
Peak memory 217308 kb
Host smart-a18bff07-389b-4aa7-99fd-f4cc290fb276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961799292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1961799292
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.888813694
Short name T299
Test name
Test status
Simulation time 158546897 ps
CPU time 2.18 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:44:59 PM PDT 24
Peak memory 217240 kb
Host smart-71383eeb-1510-4500-9895-93ce280f3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888813694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.888813694
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1985657024
Short name T479
Test name
Test status
Simulation time 68989489 ps
CPU time 0.89 seconds
Started Aug 19 05:44:51 PM PDT 24
Finished Aug 19 05:44:52 PM PDT 24
Peak memory 206892 kb
Host smart-330e92e8-b474-40ab-b310-edc99a209fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985657024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1985657024
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1648164760
Short name T888
Test name
Test status
Simulation time 1370879488 ps
CPU time 6.47 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:06 PM PDT 24
Peak memory 233632 kb
Host smart-8099137d-d3c6-499d-bad1-fd35dbbbd863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648164760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1648164760
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.861259363
Short name T847
Test name
Test status
Simulation time 13445265 ps
CPU time 0.76 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:00 PM PDT 24
Peak memory 206312 kb
Host smart-b62699c0-a281-4b5e-ae05-00be83d9aa00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861259363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.861259363
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3058577914
Short name T82
Test name
Test status
Simulation time 193285071 ps
CPU time 2.31 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:45:01 PM PDT 24
Peak memory 233604 kb
Host smart-c2c68565-e46f-4ef2-8dd0-c5dff83c0e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058577914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3058577914
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1510893393
Short name T384
Test name
Test status
Simulation time 55244585 ps
CPU time 0.82 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:01 PM PDT 24
Peak memory 206436 kb
Host smart-d1fca133-6901-4d5f-b617-88b7cafa5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510893393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1510893393
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1008194174
Short name T871
Test name
Test status
Simulation time 179300444239 ps
CPU time 319.19 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:50:18 PM PDT 24
Peak memory 263228 kb
Host smart-1900e458-f11b-45c6-9df9-128f2f95430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008194174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1008194174
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1779025132
Short name T961
Test name
Test status
Simulation time 78126318779 ps
CPU time 663.56 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:56:02 PM PDT 24
Peak memory 266416 kb
Host smart-8069213a-6b3b-4b34-99a6-d2d4e530be6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779025132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1779025132
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3642182859
Short name T36
Test name
Test status
Simulation time 2146085363 ps
CPU time 44.56 seconds
Started Aug 19 05:45:03 PM PDT 24
Finished Aug 19 05:45:47 PM PDT 24
Peak memory 250156 kb
Host smart-dc19cf8c-7b83-4442-994a-64c273d70ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642182859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3642182859
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.245178539
Short name T46
Test name
Test status
Simulation time 1400498417 ps
CPU time 5.25 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:45:03 PM PDT 24
Peak memory 236764 kb
Host smart-c1038db1-ae98-4960-94b8-38045e1b9b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245178539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.245178539
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3937050466
Short name T763
Test name
Test status
Simulation time 3028872272 ps
CPU time 10.08 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:10 PM PDT 24
Peak memory 233716 kb
Host smart-f890a26a-168d-4e1d-a3e5-d8911f9da4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937050466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3937050466
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1343749434
Short name T240
Test name
Test status
Simulation time 184041989 ps
CPU time 4.23 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:03 PM PDT 24
Peak memory 225420 kb
Host smart-16c8b9f6-9c4c-4705-b923-c916c102e26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343749434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1343749434
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4220614822
Short name T565
Test name
Test status
Simulation time 132131920 ps
CPU time 2.62 seconds
Started Aug 19 05:45:01 PM PDT 24
Finished Aug 19 05:45:03 PM PDT 24
Peak memory 225412 kb
Host smart-9b00dfa9-7a02-4f8b-85ca-9a6841b91722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220614822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4220614822
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3199315265
Short name T453
Test name
Test status
Simulation time 10252845985 ps
CPU time 12.71 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:13 PM PDT 24
Peak memory 233652 kb
Host smart-77954918-dc0d-4bfe-ae92-f39fc8be6ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199315265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3199315265
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.224776289
Short name T631
Test name
Test status
Simulation time 3849796077 ps
CPU time 15.06 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:45:13 PM PDT 24
Peak memory 219864 kb
Host smart-98ab9c4f-97e2-4a2d-b966-09ec8f41a971
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=224776289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.224776289
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.864138241
Short name T834
Test name
Test status
Simulation time 26396913282 ps
CPU time 298.52 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:49:57 PM PDT 24
Peak memory 258472 kb
Host smart-eb8b001c-79af-43cd-b9e2-3820f88f4eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864138241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.864138241
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3200098858
Short name T641
Test name
Test status
Simulation time 9166696590 ps
CPU time 26.54 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 217268 kb
Host smart-b8508cc9-461e-4fb3-8aaf-dec5f0674dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200098858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3200098858
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.17320039
Short name T718
Test name
Test status
Simulation time 2209924125 ps
CPU time 9.45 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:09 PM PDT 24
Peak memory 217300 kb
Host smart-f8f79845-57c3-4561-89b2-d83dec66e809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17320039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.17320039
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3978013289
Short name T998
Test name
Test status
Simulation time 258000762 ps
CPU time 1.5 seconds
Started Aug 19 05:45:05 PM PDT 24
Finished Aug 19 05:45:07 PM PDT 24
Peak memory 217160 kb
Host smart-74f32b13-6dac-4549-8cdd-88e78cb0eb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978013289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3978013289
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1365279624
Short name T817
Test name
Test status
Simulation time 202376542 ps
CPU time 0.9 seconds
Started Aug 19 05:45:01 PM PDT 24
Finished Aug 19 05:45:02 PM PDT 24
Peak memory 206844 kb
Host smart-586d0c60-7ce1-4fab-a631-12d5b5137cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365279624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1365279624
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.37424223
Short name T219
Test name
Test status
Simulation time 10438387957 ps
CPU time 17.27 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 233668 kb
Host smart-341831f4-9e38-4b91-939e-3e4b7fa25e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37424223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.37424223
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2480561767
Short name T922
Test name
Test status
Simulation time 18791257 ps
CPU time 0.75 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:00 PM PDT 24
Peak memory 205748 kb
Host smart-987db734-c780-4bec-b9de-98e302ccb3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480561767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2480561767
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1266343938
Short name T435
Test name
Test status
Simulation time 105984305 ps
CPU time 3.75 seconds
Started Aug 19 05:45:01 PM PDT 24
Finished Aug 19 05:45:05 PM PDT 24
Peak memory 233628 kb
Host smart-7421f9ef-ace0-4c9c-bbed-32f04831355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266343938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1266343938
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4279340430
Short name T769
Test name
Test status
Simulation time 14371152 ps
CPU time 0.8 seconds
Started Aug 19 05:44:58 PM PDT 24
Finished Aug 19 05:44:59 PM PDT 24
Peak memory 207404 kb
Host smart-ed4d2acb-2195-4e36-978c-cf42fb72dcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279340430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4279340430
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.305398663
Short name T564
Test name
Test status
Simulation time 11335025 ps
CPU time 0.72 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:01 PM PDT 24
Peak memory 216644 kb
Host smart-e2939877-acc4-4466-806f-907209bc6fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305398663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.305398663
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.284962167
Short name T271
Test name
Test status
Simulation time 629967036 ps
CPU time 15.53 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 235796 kb
Host smart-fb6971a7-d889-4214-b7a6-3ef71bf7950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284962167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.284962167
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1705228713
Short name T571
Test name
Test status
Simulation time 2982316119 ps
CPU time 21.56 seconds
Started Aug 19 05:45:05 PM PDT 24
Finished Aug 19 05:45:27 PM PDT 24
Peak memory 225500 kb
Host smart-1f615b9a-6daf-4986-bcbc-6d7c0b010a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705228713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1705228713
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.280070919
Short name T742
Test name
Test status
Simulation time 355497262 ps
CPU time 0.84 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:00 PM PDT 24
Peak memory 216896 kb
Host smart-e64b3027-1d4e-4e97-a813-fc943eb9a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280070919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.280070919
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1828492048
Short name T677
Test name
Test status
Simulation time 934540870 ps
CPU time 4.86 seconds
Started Aug 19 05:45:01 PM PDT 24
Finished Aug 19 05:45:06 PM PDT 24
Peak memory 225368 kb
Host smart-425f7aed-ab83-41de-8317-c6f49e7f2932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828492048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1828492048
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1539920384
Short name T793
Test name
Test status
Simulation time 6733672745 ps
CPU time 17.83 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 249920 kb
Host smart-df96d25a-f865-4616-b502-73909e7f31a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539920384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1539920384
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2737273086
Short name T664
Test name
Test status
Simulation time 187215222 ps
CPU time 2.54 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:02 PM PDT 24
Peak memory 233628 kb
Host smart-a3c8d9db-954b-4aec-bfd6-1c8adc1ff93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737273086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2737273086
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1130073812
Short name T954
Test name
Test status
Simulation time 25926496047 ps
CPU time 19.25 seconds
Started Aug 19 05:45:03 PM PDT 24
Finished Aug 19 05:45:22 PM PDT 24
Peak memory 233756 kb
Host smart-21dd347c-1543-4de2-8dfd-c42a310895de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130073812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1130073812
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2160152354
Short name T539
Test name
Test status
Simulation time 808346583 ps
CPU time 5.34 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:06 PM PDT 24
Peak memory 220184 kb
Host smart-fe05deff-00ff-4e97-9dd6-b67f8967daa2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2160152354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2160152354
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.551290584
Short name T993
Test name
Test status
Simulation time 47716238 ps
CPU time 0.97 seconds
Started Aug 19 05:44:59 PM PDT 24
Finished Aug 19 05:45:01 PM PDT 24
Peak memory 207592 kb
Host smart-5290d18e-781d-4452-862e-32907c6e36a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551290584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.551290584
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.553154085
Short name T546
Test name
Test status
Simulation time 4699382184 ps
CPU time 26.3 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:45:23 PM PDT 24
Peak memory 217388 kb
Host smart-d0ff52fe-530e-463c-822f-58fcfdd49792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553154085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.553154085
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1817965836
Short name T407
Test name
Test status
Simulation time 3310954704 ps
CPU time 4.13 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:04 PM PDT 24
Peak memory 217156 kb
Host smart-e7f47e8d-ce51-422b-9899-7773cc75cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817965836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1817965836
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1091833203
Short name T856
Test name
Test status
Simulation time 69229702 ps
CPU time 1.7 seconds
Started Aug 19 05:44:57 PM PDT 24
Finished Aug 19 05:44:59 PM PDT 24
Peak memory 217276 kb
Host smart-9c22f59b-c09b-43dd-bfce-50cf7faf5207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091833203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1091833203
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1111359883
Short name T955
Test name
Test status
Simulation time 115270169 ps
CPU time 0.8 seconds
Started Aug 19 05:45:05 PM PDT 24
Finished Aug 19 05:45:06 PM PDT 24
Peak memory 206868 kb
Host smart-ee65e1c3-3948-4654-9c33-6c012bd79a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111359883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1111359883
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1083163800
Short name T517
Test name
Test status
Simulation time 3098817285 ps
CPU time 7.79 seconds
Started Aug 19 05:45:00 PM PDT 24
Finished Aug 19 05:45:08 PM PDT 24
Peak memory 225452 kb
Host smart-85f1db18-7d0b-4ca0-bad5-93721ee25aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083163800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1083163800
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1075328928
Short name T948
Test name
Test status
Simulation time 44894759 ps
CPU time 0.72 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 206676 kb
Host smart-8684ccbc-a695-4bc9-b915-2b5462cda4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075328928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1075328928
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3824562386
Short name T81
Test name
Test status
Simulation time 117039442 ps
CPU time 2.75 seconds
Started Aug 19 05:45:12 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 233588 kb
Host smart-9ca085d2-abee-4057-918d-d82718f6d0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824562386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3824562386
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.281176550
Short name T369
Test name
Test status
Simulation time 79050397 ps
CPU time 0.76 seconds
Started Aug 19 05:45:15 PM PDT 24
Finished Aug 19 05:45:16 PM PDT 24
Peak memory 206468 kb
Host smart-2f5feec0-5d42-4d5b-b5dc-d6668cc950e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281176550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.281176550
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.31274912
Short name T303
Test name
Test status
Simulation time 21048665 ps
CPU time 0.79 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:14 PM PDT 24
Peak memory 216688 kb
Host smart-2bfba23d-f0cd-44b5-8083-9f3c5609ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31274912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.31274912
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2699832637
Short name T146
Test name
Test status
Simulation time 41356783906 ps
CPU time 204.9 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:48:38 PM PDT 24
Peak memory 242000 kb
Host smart-493c52cd-43c7-454a-9692-67dd31b7f047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699832637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2699832637
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2892709752
Short name T272
Test name
Test status
Simulation time 76707661078 ps
CPU time 47 seconds
Started Aug 19 05:45:11 PM PDT 24
Finished Aug 19 05:45:58 PM PDT 24
Peak memory 233892 kb
Host smart-8800237f-2fe6-4876-87e8-d3c9b702afb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892709752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2892709752
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2672614511
Short name T862
Test name
Test status
Simulation time 142068256 ps
CPU time 3.05 seconds
Started Aug 19 05:45:12 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 233580 kb
Host smart-df055246-5ed4-43fa-8d76-7cebc62ecf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672614511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2672614511
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.985513831
Short name T12
Test name
Test status
Simulation time 6331570162 ps
CPU time 63.92 seconds
Started Aug 19 05:45:10 PM PDT 24
Finished Aug 19 05:46:14 PM PDT 24
Peak memory 251172 kb
Host smart-2289518c-6ca6-4d39-8c9a-31e164d5bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985513831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.985513831
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.868988957
Short name T183
Test name
Test status
Simulation time 1551171900 ps
CPU time 11.42 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:25 PM PDT 24
Peak memory 233636 kb
Host smart-69e1f3f8-fc9c-4347-8059-1758c9ffa09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868988957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.868988957
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3743723415
Short name T348
Test name
Test status
Simulation time 3124790704 ps
CPU time 18.17 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 251860 kb
Host smart-2a4eb69e-7e4f-4e78-b8c9-682d0700cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743723415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3743723415
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.200211263
Short name T555
Test name
Test status
Simulation time 4511039814 ps
CPU time 17.08 seconds
Started Aug 19 05:45:11 PM PDT 24
Finished Aug 19 05:45:28 PM PDT 24
Peak memory 233688 kb
Host smart-5ef2a9fb-ce84-4424-b078-3a6345b163d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200211263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.200211263
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2966098814
Short name T570
Test name
Test status
Simulation time 38278051565 ps
CPU time 28.51 seconds
Started Aug 19 05:45:12 PM PDT 24
Finished Aug 19 05:45:40 PM PDT 24
Peak memory 233712 kb
Host smart-1dbcc734-ee74-4b88-9f94-cc489c102742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966098814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2966098814
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1939572282
Short name T581
Test name
Test status
Simulation time 428785512 ps
CPU time 6.52 seconds
Started Aug 19 05:45:11 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 224012 kb
Host smart-e338ee85-914c-4365-b8b0-aed416a36256
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1939572282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1939572282
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2841865331
Short name T863
Test name
Test status
Simulation time 45185605 ps
CPU time 1.04 seconds
Started Aug 19 05:45:12 PM PDT 24
Finished Aug 19 05:45:13 PM PDT 24
Peak memory 208588 kb
Host smart-45c5939d-9dbc-42d1-b581-0ea4fd0811a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841865331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2841865331
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1633569433
Short name T404
Test name
Test status
Simulation time 1753393018 ps
CPU time 6.06 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 217368 kb
Host smart-978f4099-dbeb-48b8-80ea-aa426137db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633569433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1633569433
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.469747570
Short name T394
Test name
Test status
Simulation time 520341695 ps
CPU time 3.37 seconds
Started Aug 19 05:45:10 PM PDT 24
Finished Aug 19 05:45:14 PM PDT 24
Peak memory 217240 kb
Host smart-1c7acd44-fa0f-4606-85f1-22499d46aba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469747570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.469747570
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3965731290
Short name T516
Test name
Test status
Simulation time 309551669 ps
CPU time 5.44 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:20 PM PDT 24
Peak memory 217252 kb
Host smart-c0dcdba4-ca58-43b3-803c-1f7f97c5f1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965731290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3965731290
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.176775770
Short name T979
Test name
Test status
Simulation time 63401716 ps
CPU time 0.77 seconds
Started Aug 19 05:45:10 PM PDT 24
Finished Aug 19 05:45:11 PM PDT 24
Peak memory 206696 kb
Host smart-f7ac10b4-a72e-4a63-a89d-14ac4bd78dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176775770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.176775770
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1708745245
Short name T317
Test name
Test status
Simulation time 1901907952 ps
CPU time 14.82 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:29 PM PDT 24
Peak memory 233732 kb
Host smart-2509d153-c7bb-4c6e-b1da-6d7da7771bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708745245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1708745245
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1975814684
Short name T772
Test name
Test status
Simulation time 42451642 ps
CPU time 0.71 seconds
Started Aug 19 05:42:53 PM PDT 24
Finished Aug 19 05:42:53 PM PDT 24
Peak memory 205744 kb
Host smart-daa8d915-bb8f-4a94-afb9-c9fa41f8335c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975814684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
975814684
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.867172858
Short name T212
Test name
Test status
Simulation time 4743129989 ps
CPU time 15.5 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:43:06 PM PDT 24
Peak memory 233672 kb
Host smart-9044a2ae-bfa8-4f86-bd53-da68f3bb839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867172858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.867172858
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2703057462
Short name T501
Test name
Test status
Simulation time 35311654 ps
CPU time 0.8 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:42:53 PM PDT 24
Peak memory 206464 kb
Host smart-fb6d6cfb-670d-4099-afc7-3c137eeee2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703057462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2703057462
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.606642643
Short name T201
Test name
Test status
Simulation time 2155408651 ps
CPU time 30.12 seconds
Started Aug 19 05:42:53 PM PDT 24
Finished Aug 19 05:43:24 PM PDT 24
Peak memory 237740 kb
Host smart-a3a88b17-38aa-4970-be60-bc1447380673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606642643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.606642643
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3040693935
Short name T149
Test name
Test status
Simulation time 20321035717 ps
CPU time 158.79 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 238312 kb
Host smart-41368e3f-1119-433d-8f60-2bd1203b71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040693935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3040693935
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.881053194
Short name T561
Test name
Test status
Simulation time 20926559203 ps
CPU time 115.49 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:44:47 PM PDT 24
Peak memory 242368 kb
Host smart-2fc96d90-8bea-4621-aed6-96d21d795093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881053194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
881053194
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.864120508
Short name T436
Test name
Test status
Simulation time 2536469419 ps
CPU time 9.93 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:43:00 PM PDT 24
Peak memory 225444 kb
Host smart-e9e39d0a-72ed-4e5b-a547-005a0847e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864120508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.864120508
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.296688239
Short name T277
Test name
Test status
Simulation time 77059208241 ps
CPU time 86.15 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:44:18 PM PDT 24
Peak memory 269116 kb
Host smart-8fe1041b-f407-458e-a556-b77976975eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296688239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
296688239
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2037170300
Short name T681
Test name
Test status
Simulation time 256037601 ps
CPU time 4.8 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:42:55 PM PDT 24
Peak memory 225360 kb
Host smart-f6af909b-29ba-4806-a2ab-549e50d7e072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037170300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2037170300
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4084704601
Short name T823
Test name
Test status
Simulation time 1450027707 ps
CPU time 5.62 seconds
Started Aug 19 05:42:54 PM PDT 24
Finished Aug 19 05:43:00 PM PDT 24
Peak memory 225316 kb
Host smart-75ff1d47-4500-4188-9b01-ee9d0c1dc0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084704601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4084704601
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.308290023
Short name T265
Test name
Test status
Simulation time 2170586838 ps
CPU time 9.28 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:43:01 PM PDT 24
Peak memory 233704 kb
Host smart-16ce4c46-8963-456c-bec7-01d73ee78ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308290023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
308290023
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.660248407
Short name T678
Test name
Test status
Simulation time 385174364 ps
CPU time 7.48 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:42:59 PM PDT 24
Peak memory 233596 kb
Host smart-587e5939-aeb4-4eed-b447-906c31c907f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660248407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.660248407
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1252089561
Short name T534
Test name
Test status
Simulation time 1118529444 ps
CPU time 13.96 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:43:05 PM PDT 24
Peak memory 222660 kb
Host smart-9f06e695-e248-490d-a4db-93e109052e02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1252089561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1252089561
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.402058492
Short name T54
Test name
Test status
Simulation time 1728124107 ps
CPU time 1.45 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:42:52 PM PDT 24
Peak memory 237208 kb
Host smart-6268dee2-144d-4d9c-a8c1-21fe885e8cf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402058492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.402058492
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2141397277
Short name T145
Test name
Test status
Simulation time 5221985554 ps
CPU time 41.72 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:43:34 PM PDT 24
Peak memory 241000 kb
Host smart-3c001c23-355b-4acc-a434-616dcba7ce23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141397277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2141397277
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2863013856
Short name T779
Test name
Test status
Simulation time 13499455971 ps
CPU time 20.3 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:43:10 PM PDT 24
Peak memory 217260 kb
Host smart-c4bf27e5-69cb-4a2c-836b-95fc2293adb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863013856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2863013856
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1752080875
Short name T855
Test name
Test status
Simulation time 6748436201 ps
CPU time 15.37 seconds
Started Aug 19 05:42:53 PM PDT 24
Finished Aug 19 05:43:08 PM PDT 24
Peak memory 217324 kb
Host smart-d0e4912a-429a-460a-bd4d-d1098e732e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752080875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1752080875
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3571129133
Short name T566
Test name
Test status
Simulation time 34308974 ps
CPU time 1.42 seconds
Started Aug 19 05:42:52 PM PDT 24
Finished Aug 19 05:42:54 PM PDT 24
Peak memory 217176 kb
Host smart-7cbe42b7-1426-4eaf-9dbf-a3ae888cad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571129133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3571129133
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3119735220
Short name T319
Test name
Test status
Simulation time 161994916 ps
CPU time 1.02 seconds
Started Aug 19 05:42:50 PM PDT 24
Finished Aug 19 05:42:51 PM PDT 24
Peak memory 207872 kb
Host smart-9638484b-ccae-4550-9952-3dd809d7b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119735220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3119735220
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.990037971
Short name T540
Test name
Test status
Simulation time 66063058 ps
CPU time 2.77 seconds
Started Aug 19 05:42:51 PM PDT 24
Finished Aug 19 05:42:54 PM PDT 24
Peak memory 233628 kb
Host smart-43aabafe-6f8f-4ced-a64d-7ea7744dda69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990037971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.990037971
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3319021580
Short name T673
Test name
Test status
Simulation time 57071411 ps
CPU time 0.72 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 206656 kb
Host smart-f0f01db6-795c-471e-b302-f8b83dab16a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319021580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3319021580
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3104644438
Short name T619
Test name
Test status
Simulation time 7129723622 ps
CPU time 11.77 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:25 PM PDT 24
Peak memory 225584 kb
Host smart-505836cc-8d36-4acb-8d52-6dc6d50ab326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104644438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3104644438
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1726687934
Short name T492
Test name
Test status
Simulation time 49883238 ps
CPU time 0.83 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:14 PM PDT 24
Peak memory 206732 kb
Host smart-56896ba8-6f0d-486c-9026-70082dc7fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726687934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1726687934
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3683838898
Short name T223
Test name
Test status
Simulation time 81196231684 ps
CPU time 305.1 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:50:19 PM PDT 24
Peak memory 253744 kb
Host smart-1965b0b9-3836-4dc6-a8b0-fafd28dbaaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683838898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3683838898
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1613512031
Short name T596
Test name
Test status
Simulation time 767552083 ps
CPU time 5.69 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 220208 kb
Host smart-a5d4ac59-42ce-4693-9f1d-4011c50627ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613512031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1613512031
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.531882656
Short name T757
Test name
Test status
Simulation time 274059551527 ps
CPU time 342.13 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:50:55 PM PDT 24
Peak memory 266644 kb
Host smart-0d4c3b62-f4c4-46df-9231-d65e43dd1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531882656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.531882656
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4172769682
Short name T284
Test name
Test status
Simulation time 422654922 ps
CPU time 9.96 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 237720 kb
Host smart-4ee9519f-240f-4ffb-b353-c400bf30012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172769682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4172769682
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3318702284
Short name T147
Test name
Test status
Simulation time 19270446356 ps
CPU time 152 seconds
Started Aug 19 05:45:12 PM PDT 24
Finished Aug 19 05:47:44 PM PDT 24
Peak memory 250164 kb
Host smart-9adbac11-38f8-465a-8fc5-d2e532e2feca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318702284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3318702284
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1046550985
Short name T890
Test name
Test status
Simulation time 563912946 ps
CPU time 4.73 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 233672 kb
Host smart-05dbef60-705c-4c7b-a7b5-56f2cc661657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046550985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1046550985
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2482196900
Short name T368
Test name
Test status
Simulation time 16372102779 ps
CPU time 70.4 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:46:25 PM PDT 24
Peak memory 238028 kb
Host smart-3a7467d0-c1c2-4b67-9375-0e8d94290007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482196900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2482196900
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.163462554
Short name T883
Test name
Test status
Simulation time 4624581265 ps
CPU time 14.85 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:28 PM PDT 24
Peak memory 233732 kb
Host smart-3ff4c91d-0c58-44e4-a760-92a48cb99d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163462554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.163462554
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3399592911
Short name T697
Test name
Test status
Simulation time 57847085477 ps
CPU time 17.47 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 233752 kb
Host smart-73e5183e-71f7-4372-9f63-4793366d129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399592911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3399592911
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.138110040
Short name T425
Test name
Test status
Simulation time 731957275 ps
CPU time 6.15 seconds
Started Aug 19 05:45:13 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 223936 kb
Host smart-3b4fd7f4-02ef-4672-b9f4-fbbec2fb4de6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=138110040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.138110040
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.86599573
Short name T345
Test name
Test status
Simulation time 3466491191 ps
CPU time 13.25 seconds
Started Aug 19 05:45:11 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 221240 kb
Host smart-84247d23-ef2d-4c8b-9675-ff0ed9d0604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86599573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.86599573
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1929670289
Short name T652
Test name
Test status
Simulation time 2242857215 ps
CPU time 7.63 seconds
Started Aug 19 05:45:11 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 217372 kb
Host smart-bd9124f2-8fed-4588-b558-00ca51192df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929670289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1929670289
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3340332024
Short name T295
Test name
Test status
Simulation time 196449779 ps
CPU time 2.12 seconds
Started Aug 19 05:45:12 PM PDT 24
Finished Aug 19 05:45:14 PM PDT 24
Peak memory 217284 kb
Host smart-c0e4e48b-234e-40b3-a0e0-5bcfceea2918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340332024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3340332024
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2580875920
Short name T466
Test name
Test status
Simulation time 323764349 ps
CPU time 1.01 seconds
Started Aug 19 05:45:15 PM PDT 24
Finished Aug 19 05:45:16 PM PDT 24
Peak memory 206920 kb
Host smart-b7ef6809-4386-4195-b284-f30f3a39cd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580875920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2580875920
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.490714907
Short name T776
Test name
Test status
Simulation time 442887110 ps
CPU time 2.49 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:17 PM PDT 24
Peak memory 233656 kb
Host smart-4a0c723d-c99a-4827-bb8e-140d464e2d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490714907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.490714907
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3150966485
Short name T300
Test name
Test status
Simulation time 17359409 ps
CPU time 0.73 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 206288 kb
Host smart-7efd66c0-a8ba-4d40-8168-52aaecba32c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150966485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3150966485
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1884841559
Short name T341
Test name
Test status
Simulation time 158656896 ps
CPU time 3.01 seconds
Started Aug 19 05:45:15 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 233628 kb
Host smart-e9e435d7-a0cd-4aa0-b271-a4e45f6c8cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884841559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1884841559
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.524094005
Short name T123
Test name
Test status
Simulation time 14369924 ps
CPU time 0.85 seconds
Started Aug 19 05:45:23 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 207432 kb
Host smart-36239841-4bc1-4d29-a7e0-8b5a92cb2a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524094005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.524094005
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.334885923
Short name T270
Test name
Test status
Simulation time 12865430412 ps
CPU time 116.76 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:47:15 PM PDT 24
Peak memory 274056 kb
Host smart-13532c9d-f440-4664-8bb9-2be41eb926c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334885923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.334885923
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2018126933
Short name T399
Test name
Test status
Simulation time 97414965889 ps
CPU time 222.49 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:48:59 PM PDT 24
Peak memory 255252 kb
Host smart-a046a64d-3bf3-48dc-9c06-2e3cc459af48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018126933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2018126933
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4025252910
Short name T78
Test name
Test status
Simulation time 18467770406 ps
CPU time 46.17 seconds
Started Aug 19 05:45:25 PM PDT 24
Finished Aug 19 05:46:11 PM PDT 24
Peak memory 234556 kb
Host smart-c6e6d669-31cf-43ad-b280-468df5516223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025252910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4025252910
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2860056221
Short name T615
Test name
Test status
Simulation time 307951961 ps
CPU time 7.26 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:21 PM PDT 24
Peak memory 225360 kb
Host smart-8fcc9540-c963-48af-9e5d-638aece6ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860056221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2860056221
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2031554875
Short name T667
Test name
Test status
Simulation time 12838109964 ps
CPU time 48.17 seconds
Started Aug 19 05:45:25 PM PDT 24
Finished Aug 19 05:46:13 PM PDT 24
Peak memory 241940 kb
Host smart-1dc7fa34-9cb2-4511-a10c-0a1f4e7d5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031554875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2031554875
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.279556714
Short name T164
Test name
Test status
Simulation time 2967872526 ps
CPU time 32.71 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 225544 kb
Host smart-8594d077-77a5-461a-81aa-0d9111debfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279556714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.279556714
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2455401478
Short name T711
Test name
Test status
Simulation time 299185263 ps
CPU time 5.01 seconds
Started Aug 19 05:45:24 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 233616 kb
Host smart-e6c3e636-0e38-41d5-b110-9cff87aeb096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455401478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2455401478
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.177548484
Short name T580
Test name
Test status
Simulation time 15870521348 ps
CPU time 21.82 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:45:38 PM PDT 24
Peak memory 233604 kb
Host smart-c6a03ce5-3c6a-4673-ba7e-8beb6ae1cdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177548484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.177548484
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1983304894
Short name T41
Test name
Test status
Simulation time 561884530 ps
CPU time 2.71 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:21 PM PDT 24
Peak memory 233584 kb
Host smart-d0251ca9-238e-4066-99ab-ade464710aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983304894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1983304894
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.406630512
Short name T618
Test name
Test status
Simulation time 1522713544 ps
CPU time 5.3 seconds
Started Aug 19 05:45:21 PM PDT 24
Finished Aug 19 05:45:26 PM PDT 24
Peak memory 220088 kb
Host smart-10de320d-3628-4fb0-902f-930fc3e0e5be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=406630512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.406630512
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3645571473
Short name T925
Test name
Test status
Simulation time 43257225 ps
CPU time 1.09 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:45:17 PM PDT 24
Peak memory 207652 kb
Host smart-16d98895-1082-4c8b-8cf1-86f2e2df8e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645571473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3645571473
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.927317730
Short name T292
Test name
Test status
Simulation time 6443444743 ps
CPU time 37.19 seconds
Started Aug 19 05:45:24 PM PDT 24
Finished Aug 19 05:46:01 PM PDT 24
Peak memory 217352 kb
Host smart-49d6f1fd-3b02-4adf-acb8-1781e9f6733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927317730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.927317730
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.300750304
Short name T813
Test name
Test status
Simulation time 1706673255 ps
CPU time 4.95 seconds
Started Aug 19 05:45:21 PM PDT 24
Finished Aug 19 05:45:27 PM PDT 24
Peak memory 217180 kb
Host smart-d943b22b-881a-4bce-9d49-afbad2baa905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300750304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.300750304
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3110889593
Short name T902
Test name
Test status
Simulation time 43981665 ps
CPU time 0.83 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 207488 kb
Host smart-8b5c5363-34ce-46c1-a0c6-524127658dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110889593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3110889593
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1869514947
Short name T472
Test name
Test status
Simulation time 84521116 ps
CPU time 0.81 seconds
Started Aug 19 05:45:19 PM PDT 24
Finished Aug 19 05:45:20 PM PDT 24
Peak memory 206828 kb
Host smart-8644c15e-2caf-480f-9216-f0e0b6a3aafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869514947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1869514947
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2396493111
Short name T878
Test name
Test status
Simulation time 1851029002 ps
CPU time 13.67 seconds
Started Aug 19 05:45:25 PM PDT 24
Finished Aug 19 05:45:38 PM PDT 24
Peak memory 240948 kb
Host smart-cd5ac57f-09c8-4532-9d5a-815a974fa175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396493111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2396493111
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3542108922
Short name T578
Test name
Test status
Simulation time 72727293 ps
CPU time 0.73 seconds
Started Aug 19 05:45:23 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 206292 kb
Host smart-02a692e9-1eb1-478c-8604-ef5f3f2eea1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542108922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3542108922
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.866680032
Short name T682
Test name
Test status
Simulation time 117505667 ps
CPU time 2.49 seconds
Started Aug 19 05:45:25 PM PDT 24
Finished Aug 19 05:45:27 PM PDT 24
Peak memory 233628 kb
Host smart-b0bfff9a-695e-4c67-b265-b29575d84828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866680032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.866680032
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3954615231
Short name T318
Test name
Test status
Simulation time 13911423 ps
CPU time 0.75 seconds
Started Aug 19 05:45:23 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 206408 kb
Host smart-fe38acd8-d472-44ea-809d-aa9b0bc226f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954615231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3954615231
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1601503301
Short name T235
Test name
Test status
Simulation time 15904157663 ps
CPU time 154.75 seconds
Started Aug 19 05:45:20 PM PDT 24
Finished Aug 19 05:47:55 PM PDT 24
Peak memory 258200 kb
Host smart-b796710a-ad53-4831-8b10-cb2a965ac131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601503301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1601503301
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1180148380
Short name T932
Test name
Test status
Simulation time 56759848108 ps
CPU time 304.74 seconds
Started Aug 19 05:45:21 PM PDT 24
Finished Aug 19 05:50:26 PM PDT 24
Peak memory 256388 kb
Host smart-74679fdd-4cfb-4eb9-b1ef-f534842f78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180148380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1180148380
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3333330
Short name T901
Test name
Test status
Simulation time 40661107501 ps
CPU time 392.13 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:51:50 PM PDT 24
Peak memory 258044 kb
Host smart-646b45b7-37fa-45f0-99fe-f39908557069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.3333330
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1948687578
Short name T737
Test name
Test status
Simulation time 1256650612 ps
CPU time 8.75 seconds
Started Aug 19 05:45:24 PM PDT 24
Finished Aug 19 05:45:33 PM PDT 24
Peak memory 233596 kb
Host smart-e55925e8-4303-4c41-86c1-18463397fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948687578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1948687578
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2357019437
Short name T198
Test name
Test status
Simulation time 4824018838 ps
CPU time 100.82 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:46:57 PM PDT 24
Peak memory 274728 kb
Host smart-c0ec1def-64a8-41d3-ba78-18dc97ad706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357019437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2357019437
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2609324905
Short name T921
Test name
Test status
Simulation time 2219108896 ps
CPU time 15.8 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:34 PM PDT 24
Peak memory 225516 kb
Host smart-4c516044-ab2e-4c45-9c98-c8ee6f1e24b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609324905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2609324905
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4115354422
Short name T723
Test name
Test status
Simulation time 3391263370 ps
CPU time 7.66 seconds
Started Aug 19 05:45:21 PM PDT 24
Finished Aug 19 05:45:29 PM PDT 24
Peak memory 241888 kb
Host smart-165e5001-e4cb-4605-bad6-16a83a7d1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115354422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4115354422
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1269666711
Short name T995
Test name
Test status
Simulation time 4444148495 ps
CPU time 8.19 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:23 PM PDT 24
Peak memory 225568 kb
Host smart-623875e8-e9df-4860-8948-99fbdbcda038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269666711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1269666711
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3941555301
Short name T362
Test name
Test status
Simulation time 1730350756 ps
CPU time 6.99 seconds
Started Aug 19 05:45:17 PM PDT 24
Finished Aug 19 05:45:24 PM PDT 24
Peak memory 233620 kb
Host smart-dcbc4a54-d5ec-47d5-b99a-f1caf748aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941555301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3941555301
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3217441370
Short name T814
Test name
Test status
Simulation time 1348600163 ps
CPU time 11.63 seconds
Started Aug 19 05:45:17 PM PDT 24
Finished Aug 19 05:45:28 PM PDT 24
Peak memory 223556 kb
Host smart-904c769d-6a17-48f1-92a9-ef64080542f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217441370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3217441370
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2416876605
Short name T21
Test name
Test status
Simulation time 49689179 ps
CPU time 1.01 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:19 PM PDT 24
Peak memory 208608 kb
Host smart-8bdfef89-4acf-4721-a932-2a4e97863c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416876605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2416876605
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3555642982
Short name T655
Test name
Test status
Simulation time 1888713607 ps
CPU time 3.3 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:45:20 PM PDT 24
Peak memory 217236 kb
Host smart-4e659364-7806-4fcb-8df6-446a0cc88d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555642982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3555642982
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2936465214
Short name T120
Test name
Test status
Simulation time 569910002 ps
CPU time 1.69 seconds
Started Aug 19 05:45:16 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 208804 kb
Host smart-c42d7051-8fa4-406b-8d5a-779ad79426a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936465214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2936465214
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2962510184
Short name T709
Test name
Test status
Simulation time 16613165 ps
CPU time 0.7 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 206484 kb
Host smart-c9f0b01e-c546-474b-8ee4-8878ef8d4bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962510184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2962510184
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.881917149
Short name T421
Test name
Test status
Simulation time 31630393 ps
CPU time 0.74 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:15 PM PDT 24
Peak memory 206888 kb
Host smart-b336eabe-7e4c-4801-9f4a-0f2cf8d25073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881917149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.881917149
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.317131629
Short name T119
Test name
Test status
Simulation time 3887297901 ps
CPU time 5.36 seconds
Started Aug 19 05:45:25 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 225540 kb
Host smart-fae317a6-91fc-47da-9e0a-d48411116070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317131629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.317131629
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.196160876
Short name T326
Test name
Test status
Simulation time 24177662 ps
CPU time 0.71 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 206632 kb
Host smart-3c9a6ec9-b292-4452-ae15-60c6dc882bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196160876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.196160876
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.646548848
Short name T915
Test name
Test status
Simulation time 267395870 ps
CPU time 4.3 seconds
Started Aug 19 05:45:19 PM PDT 24
Finished Aug 19 05:45:23 PM PDT 24
Peak memory 233572 kb
Host smart-1dd6e662-a62d-4f5e-a8ee-cfd23c78de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646548848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.646548848
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.457663308
Short name T96
Test name
Test status
Simulation time 187457749 ps
CPU time 0.77 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:45:27 PM PDT 24
Peak memory 207784 kb
Host smart-1a3e9faa-14bf-47bb-8df2-9b3938233f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457663308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.457663308
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.218124877
Short name T39
Test name
Test status
Simulation time 216530720994 ps
CPU time 94.77 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:47:02 PM PDT 24
Peak memory 251988 kb
Host smart-d29f2266-fa3e-4810-af4a-4ab3b894331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218124877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.218124877
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1177785518
Short name T167
Test name
Test status
Simulation time 2601643044 ps
CPU time 61.24 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:46:28 PM PDT 24
Peak memory 250412 kb
Host smart-f2a9b558-b2bc-4749-9d37-3231f9c5df25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177785518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1177785518
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3133315958
Short name T255
Test name
Test status
Simulation time 117741110242 ps
CPU time 406.03 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:52:17 PM PDT 24
Peak memory 250244 kb
Host smart-0049d41b-5dac-4c2a-973f-29ce925dcc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133315958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3133315958
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3262323441
Short name T812
Test name
Test status
Simulation time 13399975066 ps
CPU time 13.44 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:44 PM PDT 24
Peak memory 241964 kb
Host smart-6715aab7-23db-4095-8749-0da504b7cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262323441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3262323441
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3992382193
Short name T703
Test name
Test status
Simulation time 25888051870 ps
CPU time 62.91 seconds
Started Aug 19 05:45:30 PM PDT 24
Finished Aug 19 05:46:34 PM PDT 24
Peak memory 251684 kb
Host smart-4b4479ad-8856-4856-84ae-0fed1b0fc9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992382193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3992382193
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1912153787
Short name T232
Test name
Test status
Simulation time 4953181433 ps
CPU time 7.23 seconds
Started Aug 19 05:45:23 PM PDT 24
Finished Aug 19 05:45:31 PM PDT 24
Peak memory 225480 kb
Host smart-ecbc241e-6683-44ef-9f7c-c947c93aec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912153787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1912153787
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.436019990
Short name T169
Test name
Test status
Simulation time 1552682713 ps
CPU time 16.76 seconds
Started Aug 19 05:45:21 PM PDT 24
Finished Aug 19 05:45:38 PM PDT 24
Peak memory 234580 kb
Host smart-a2af79d4-f2e4-4341-a1bc-cf054f041e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436019990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.436019990
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.65576980
Short name T749
Test name
Test status
Simulation time 3144469135 ps
CPU time 11.48 seconds
Started Aug 19 05:45:22 PM PDT 24
Finished Aug 19 05:45:33 PM PDT 24
Peak memory 241580 kb
Host smart-41ff0ac0-50ff-4466-917b-c3766e6ac658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65576980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.65576980
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1902887308
Short name T613
Test name
Test status
Simulation time 298683390 ps
CPU time 2.52 seconds
Started Aug 19 05:45:19 PM PDT 24
Finished Aug 19 05:45:21 PM PDT 24
Peak memory 233580 kb
Host smart-6b99a6d6-ed4d-47cd-8ca1-d1c6af1b8b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902887308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1902887308
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1987226693
Short name T559
Test name
Test status
Simulation time 606612262 ps
CPU time 4.39 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 221016 kb
Host smart-9fe65e73-28e3-4009-ba2e-d233fe5e8805
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987226693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1987226693
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.949058487
Short name T260
Test name
Test status
Simulation time 41880757710 ps
CPU time 317.92 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:50:44 PM PDT 24
Peak memory 274104 kb
Host smart-30c99136-2fd6-4194-b05a-2f1965deb685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949058487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.949058487
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.595889
Short name T798
Test name
Test status
Simulation time 7218120917 ps
CPU time 30.54 seconds
Started Aug 19 05:45:18 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 217356 kb
Host smart-b9b2174a-4737-4c52-a12d-c48a1aee7ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.595889
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1627566851
Short name T354
Test name
Test status
Simulation time 1284738773 ps
CPU time 6.18 seconds
Started Aug 19 05:45:14 PM PDT 24
Finished Aug 19 05:45:21 PM PDT 24
Peak memory 217212 kb
Host smart-cf07392a-4a4d-4764-9cba-00277e53ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627566851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1627566851
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3194429408
Short name T688
Test name
Test status
Simulation time 59061365 ps
CPU time 0.96 seconds
Started Aug 19 05:45:19 PM PDT 24
Finished Aug 19 05:45:20 PM PDT 24
Peak memory 207872 kb
Host smart-615d4121-55fd-4f1a-a8e0-23f3f32b36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194429408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3194429408
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.83685747
Short name T357
Test name
Test status
Simulation time 309942472 ps
CPU time 0.9 seconds
Started Aug 19 05:45:17 PM PDT 24
Finished Aug 19 05:45:18 PM PDT 24
Peak memory 207844 kb
Host smart-adc29539-83f3-45de-949c-b30ffa1e5b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83685747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.83685747
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2300619282
Short name T343
Test name
Test status
Simulation time 4899581099 ps
CPU time 10.69 seconds
Started Aug 19 05:45:25 PM PDT 24
Finished Aug 19 05:45:36 PM PDT 24
Peak memory 225528 kb
Host smart-20d23ed7-d1a4-4082-b0b6-77ca089fe69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300619282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2300619282
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.224300482
Short name T693
Test name
Test status
Simulation time 77585788 ps
CPU time 0.71 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 206260 kb
Host smart-295b3483-8ad0-45b9-adca-be9fd32b4476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224300482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.224300482
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3544523435
Short name T903
Test name
Test status
Simulation time 691457852 ps
CPU time 2.28 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 225408 kb
Host smart-26d284ba-8aec-4a3c-a86c-2dbd245c8c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544523435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3544523435
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1295459510
Short name T620
Test name
Test status
Simulation time 67594565 ps
CPU time 0.78 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:29 PM PDT 24
Peak memory 207496 kb
Host smart-cc4723b8-afad-4439-8fa3-5015af2c57ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295459510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1295459510
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.421583027
Short name T228
Test name
Test status
Simulation time 3518632638 ps
CPU time 27.59 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:56 PM PDT 24
Peak memory 250136 kb
Host smart-7485da76-77f1-468e-aa42-918352b24f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421583027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.421583027
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.929891845
Short name T1003
Test name
Test status
Simulation time 1696284140 ps
CPU time 31.7 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:45:58 PM PDT 24
Peak memory 250048 kb
Host smart-11700deb-1c17-439e-8b13-4f2de9106473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929891845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.929891845
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.949229156
Short name T960
Test name
Test status
Simulation time 336326289698 ps
CPU time 301.28 seconds
Started Aug 19 05:45:32 PM PDT 24
Finished Aug 19 05:50:34 PM PDT 24
Peak memory 251984 kb
Host smart-44438de6-af19-4e24-9e12-97c16ba30746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949229156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.949229156
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1365694847
Short name T510
Test name
Test status
Simulation time 2030802117 ps
CPU time 15.23 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:44 PM PDT 24
Peak memory 233672 kb
Host smart-d41bba0f-b8d9-4710-8eeb-bf1111f3ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365694847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1365694847
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.399995474
Short name T500
Test name
Test status
Simulation time 7834669875 ps
CPU time 70.23 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:46:40 PM PDT 24
Peak memory 237160 kb
Host smart-601e7bed-927e-4160-963f-7bdc79487342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399995474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.399995474
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2008030525
Short name T740
Test name
Test status
Simulation time 1230078023 ps
CPU time 12.54 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:45:38 PM PDT 24
Peak memory 225392 kb
Host smart-8cece792-6afd-44cd-83e6-9e8f0d2c3f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008030525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2008030525
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.998335539
Short name T977
Test name
Test status
Simulation time 542186223 ps
CPU time 9.8 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:45:37 PM PDT 24
Peak memory 233656 kb
Host smart-4f31c687-7bf8-41c1-8f25-d97b0a737ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998335539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.998335539
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3837712660
Short name T446
Test name
Test status
Simulation time 342807423 ps
CPU time 3.49 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:45:30 PM PDT 24
Peak memory 225320 kb
Host smart-041ab512-b860-4356-ac91-dae052ceee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837712660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3837712660
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1138788695
Short name T773
Test name
Test status
Simulation time 46940138 ps
CPU time 2.38 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:45:29 PM PDT 24
Peak memory 233316 kb
Host smart-3bdff554-f4b6-481f-a95c-a9f161bab2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138788695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1138788695
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2500091829
Short name T496
Test name
Test status
Simulation time 1465569763 ps
CPU time 10.2 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:41 PM PDT 24
Peak memory 220380 kb
Host smart-0c41bf11-c5b9-4ab7-af4f-7c54fa25cba2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2500091829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2500091829
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.288867446
Short name T774
Test name
Test status
Simulation time 3831918910 ps
CPU time 21.54 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:45:50 PM PDT 24
Peak memory 234956 kb
Host smart-80d52d7e-dde5-4bcc-981e-d1437e7c6101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288867446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.288867446
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3955084003
Short name T502
Test name
Test status
Simulation time 1025400036 ps
CPU time 16.66 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:45:44 PM PDT 24
Peak memory 220436 kb
Host smart-68188c66-e608-4258-809c-f50daab06648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955084003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3955084003
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1998603416
Short name T513
Test name
Test status
Simulation time 2716195758 ps
CPU time 6.53 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:35 PM PDT 24
Peak memory 217244 kb
Host smart-2df7a007-2811-4722-a1aa-482795b03b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998603416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1998603416
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4105234601
Short name T943
Test name
Test status
Simulation time 159717955 ps
CPU time 0.98 seconds
Started Aug 19 05:45:30 PM PDT 24
Finished Aug 19 05:45:31 PM PDT 24
Peak memory 208476 kb
Host smart-0c0a7ce9-ca9a-4db2-9361-48c602e4eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105234601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4105234601
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2519796650
Short name T637
Test name
Test status
Simulation time 247591232 ps
CPU time 0.89 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 206872 kb
Host smart-6cb4db63-8d21-4006-b8a0-8a3d53f067c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519796650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2519796650
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3331344783
Short name T220
Test name
Test status
Simulation time 464782290 ps
CPU time 4.95 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 233652 kb
Host smart-09089fd5-3cef-4619-927f-54f225d54ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331344783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3331344783
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4003332294
Short name T575
Test name
Test status
Simulation time 15327172 ps
CPU time 0.71 seconds
Started Aug 19 05:45:42 PM PDT 24
Finished Aug 19 05:45:43 PM PDT 24
Peak memory 205764 kb
Host smart-332d1407-28a1-40ca-9e2a-9c1175a5538f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003332294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4003332294
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1017717194
Short name T594
Test name
Test status
Simulation time 720787367 ps
CPU time 7.59 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:36 PM PDT 24
Peak memory 233560 kb
Host smart-f6767a82-813e-46ec-9c21-dab182991814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017717194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1017717194
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1953931878
Short name T929
Test name
Test status
Simulation time 76913961 ps
CPU time 0.82 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 207464 kb
Host smart-cfe303a8-5f40-4f33-a3b5-d2484bb4504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953931878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1953931878
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.682079759
Short name T751
Test name
Test status
Simulation time 1519182993 ps
CPU time 31 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:59 PM PDT 24
Peak memory 250068 kb
Host smart-af10d657-5915-447b-b150-32b39fabb173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682079759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.682079759
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3533437893
Short name T238
Test name
Test status
Simulation time 17650896731 ps
CPU time 197.37 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:48:43 PM PDT 24
Peak memory 250656 kb
Host smart-d3fdae32-e5ec-4284-bc22-2bf6b9c6d275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533437893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3533437893
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.320796189
Short name T590
Test name
Test status
Simulation time 16398669875 ps
CPU time 75.51 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:46:45 PM PDT 24
Peak memory 257924 kb
Host smart-5ab9c356-9732-4d8f-a38a-25c3e1afdf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320796189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.320796189
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3303120983
Short name T866
Test name
Test status
Simulation time 147680112 ps
CPU time 4.69 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:36 PM PDT 24
Peak memory 233572 kb
Host smart-d8ff8079-a67b-4e4c-b7e0-ec42754ebd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303120983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3303120983
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2155939996
Short name T876
Test name
Test status
Simulation time 82798589576 ps
CPU time 276.73 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:50:06 PM PDT 24
Peak memory 239980 kb
Host smart-ffcc0276-b12d-4f5f-8903-2c74d06b9850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155939996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2155939996
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4288660796
Short name T489
Test name
Test status
Simulation time 1959930220 ps
CPU time 6.26 seconds
Started Aug 19 05:45:30 PM PDT 24
Finished Aug 19 05:45:37 PM PDT 24
Peak memory 225448 kb
Host smart-3c90b97f-0084-4b68-983e-4195489133a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288660796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4288660796
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2817109689
Short name T845
Test name
Test status
Simulation time 11243777242 ps
CPU time 43.22 seconds
Started Aug 19 05:45:30 PM PDT 24
Finished Aug 19 05:46:13 PM PDT 24
Peak memory 237660 kb
Host smart-ddc17ad2-ffe9-4a6c-a165-7a99d9e9cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817109689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2817109689
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.793051964
Short name T511
Test name
Test status
Simulation time 2067972705 ps
CPU time 8.76 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:36 PM PDT 24
Peak memory 233548 kb
Host smart-2b65e96c-e945-46b9-a2c2-c72d3fb2ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793051964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.793051964
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1468868164
Short name T535
Test name
Test status
Simulation time 115463605 ps
CPU time 2.56 seconds
Started Aug 19 05:45:29 PM PDT 24
Finished Aug 19 05:45:32 PM PDT 24
Peak memory 225328 kb
Host smart-6080c413-bcda-45a0-80c0-efd7f206b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468868164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1468868164
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.662069819
Short name T494
Test name
Test status
Simulation time 247330365 ps
CPU time 6.21 seconds
Started Aug 19 05:45:28 PM PDT 24
Finished Aug 19 05:45:34 PM PDT 24
Peak memory 223932 kb
Host smart-89a4150f-c244-42d4-a4d0-feaede2492fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=662069819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.662069819
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.575458150
Short name T755
Test name
Test status
Simulation time 239918672 ps
CPU time 1.14 seconds
Started Aug 19 05:45:42 PM PDT 24
Finished Aug 19 05:45:44 PM PDT 24
Peak memory 216820 kb
Host smart-3ff5e82b-d5db-49eb-a5c4-2e17e8340d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575458150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.575458150
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3740825339
Short name T459
Test name
Test status
Simulation time 25104056949 ps
CPU time 33.28 seconds
Started Aug 19 05:45:27 PM PDT 24
Finished Aug 19 05:46:01 PM PDT 24
Peak memory 217348 kb
Host smart-d8eae2a7-a3c8-4ea1-9b95-f5987cdf5575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740825339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3740825339
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.395900495
Short name T911
Test name
Test status
Simulation time 110406682864 ps
CPU time 16.35 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:47 PM PDT 24
Peak memory 217312 kb
Host smart-fe96fa83-b1b3-4eff-b683-ae4dd2a5a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395900495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.395900495
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4169106812
Short name T956
Test name
Test status
Simulation time 77010173 ps
CPU time 1.19 seconds
Started Aug 19 05:45:26 PM PDT 24
Finished Aug 19 05:45:28 PM PDT 24
Peak memory 209056 kb
Host smart-f4f9a5e1-8800-4d20-ba31-4755e79b5aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169106812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4169106812
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.489873223
Short name T745
Test name
Test status
Simulation time 486614770 ps
CPU time 0.94 seconds
Started Aug 19 05:45:33 PM PDT 24
Finished Aug 19 05:45:34 PM PDT 24
Peak memory 206868 kb
Host smart-8d1eef6a-8cbf-4581-b347-1e849d2dc3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489873223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.489873223
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3341772020
Short name T180
Test name
Test status
Simulation time 3006822496 ps
CPU time 13.66 seconds
Started Aug 19 05:45:31 PM PDT 24
Finished Aug 19 05:45:45 PM PDT 24
Peak memory 241736 kb
Host smart-e4f1e113-8d8a-46d3-92f2-9da5a01fe809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341772020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3341772020
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1163186004
Short name T750
Test name
Test status
Simulation time 13590126 ps
CPU time 0.76 seconds
Started Aug 19 05:45:37 PM PDT 24
Finished Aug 19 05:45:38 PM PDT 24
Peak memory 206300 kb
Host smart-c8b9fa60-e063-49ef-ac00-b4d04cb75bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163186004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1163186004
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1013862982
Short name T390
Test name
Test status
Simulation time 107225240 ps
CPU time 2.16 seconds
Started Aug 19 05:45:37 PM PDT 24
Finished Aug 19 05:45:39 PM PDT 24
Peak memory 225384 kb
Host smart-d0a9bc07-df6e-4954-a3bc-edf93a1b3ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013862982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1013862982
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.718512342
Short name T975
Test name
Test status
Simulation time 49709500 ps
CPU time 0.77 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:40 PM PDT 24
Peak memory 206744 kb
Host smart-a7d8b381-ed80-4d4e-a76a-52b313c07ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718512342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.718512342
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4016129117
Short name T725
Test name
Test status
Simulation time 21675496792 ps
CPU time 66.58 seconds
Started Aug 19 05:45:42 PM PDT 24
Finished Aug 19 05:46:48 PM PDT 24
Peak memory 250288 kb
Host smart-ef5797cd-07b4-4a94-b8c2-4e1bd11d39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016129117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4016129117
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.929592642
Short name T184
Test name
Test status
Simulation time 33189902980 ps
CPU time 97.38 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:47:16 PM PDT 24
Peak memory 233684 kb
Host smart-0e49817d-1526-4ad2-940e-f6279c30b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929592642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.929592642
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.445019218
Short name T418
Test name
Test status
Simulation time 9158684464 ps
CPU time 49.79 seconds
Started Aug 19 05:45:41 PM PDT 24
Finished Aug 19 05:46:31 PM PDT 24
Peak memory 251276 kb
Host smart-0b791584-5c6d-450e-aa64-3141442fa4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445019218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.445019218
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.231218179
Short name T796
Test name
Test status
Simulation time 465853990 ps
CPU time 10.41 seconds
Started Aug 19 05:45:36 PM PDT 24
Finished Aug 19 05:45:47 PM PDT 24
Peak memory 225448 kb
Host smart-f4cdcbfd-1c86-4a20-bb00-309d51b904f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231218179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.231218179
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1264562785
Short name T396
Test name
Test status
Simulation time 35489752754 ps
CPU time 127.42 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:47:45 PM PDT 24
Peak memory 250276 kb
Host smart-3fe7ed4f-7a96-43f5-9bd4-eb95e8fbc7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264562785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1264562785
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.409892235
Short name T765
Test name
Test status
Simulation time 73188633 ps
CPU time 2.89 seconds
Started Aug 19 05:45:41 PM PDT 24
Finished Aug 19 05:45:45 PM PDT 24
Peak memory 233652 kb
Host smart-774978ad-6f59-425a-bafa-de868773b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409892235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.409892235
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3876923126
Short name T686
Test name
Test status
Simulation time 2502975562 ps
CPU time 16.55 seconds
Started Aug 19 05:45:40 PM PDT 24
Finished Aug 19 05:45:57 PM PDT 24
Peak memory 233684 kb
Host smart-89bdfbf4-04ce-4f7b-bfdd-f318f48ad2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876923126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3876923126
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1884329899
Short name T467
Test name
Test status
Simulation time 215766333 ps
CPU time 2.39 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:42 PM PDT 24
Peak memory 225356 kb
Host smart-4bd58fb6-c602-4af9-b031-6dbc84a695d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884329899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1884329899
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3001705387
Short name T187
Test name
Test status
Simulation time 8804503547 ps
CPU time 18 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:56 PM PDT 24
Peak memory 241936 kb
Host smart-bcfeca5e-3a41-452e-b6ca-bd2e19f816f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001705387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3001705387
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.498200275
Short name T928
Test name
Test status
Simulation time 157208515 ps
CPU time 3.63 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:42 PM PDT 24
Peak memory 221492 kb
Host smart-ec9487cb-003b-47a4-9ec7-be29a9dcb5c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=498200275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.498200275
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3140015898
Short name T760
Test name
Test status
Simulation time 14786980388 ps
CPU time 47.46 seconds
Started Aug 19 05:45:34 PM PDT 24
Finished Aug 19 05:46:22 PM PDT 24
Peak memory 240984 kb
Host smart-91d703ae-127a-4950-8b07-127f111256f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140015898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3140015898
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.398089124
Short name T289
Test name
Test status
Simulation time 23971698280 ps
CPU time 25.14 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:46:03 PM PDT 24
Peak memory 217376 kb
Host smart-a07653dd-eb52-4569-a87e-1d23b099d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398089124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.398089124
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.856588113
Short name T685
Test name
Test status
Simulation time 1559727765 ps
CPU time 8.3 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:47 PM PDT 24
Peak memory 217144 kb
Host smart-89277970-539c-4e89-8619-ab36b481a6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856588113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.856588113
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2637918838
Short name T721
Test name
Test status
Simulation time 47457438 ps
CPU time 1.17 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:40 PM PDT 24
Peak memory 208812 kb
Host smart-3f68cb6e-5d56-46ee-a63f-aa69ac6decd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637918838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2637918838
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3089146887
Short name T699
Test name
Test status
Simulation time 27220978 ps
CPU time 0.78 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:38 PM PDT 24
Peak memory 206904 kb
Host smart-0f63733f-c990-4f7a-8889-11e925b825cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089146887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3089146887
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.699649494
Short name T695
Test name
Test status
Simulation time 239898655 ps
CPU time 2.89 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:42 PM PDT 24
Peak memory 233628 kb
Host smart-fefab9cc-8859-4b7e-9d5c-324c32427af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699649494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.699649494
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2572680126
Short name T726
Test name
Test status
Simulation time 15421453 ps
CPU time 0.69 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:45:47 PM PDT 24
Peak memory 206616 kb
Host smart-1bfac8a9-f79c-4aad-aceb-ad3c450a1e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572680126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2572680126
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1300601870
Short name T617
Test name
Test status
Simulation time 125317517 ps
CPU time 2.75 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:41 PM PDT 24
Peak memory 233524 kb
Host smart-4068950f-ed21-4452-980c-3918b979d61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300601870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1300601870
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1559228223
Short name T708
Test name
Test status
Simulation time 33163230 ps
CPU time 0.77 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:39 PM PDT 24
Peak memory 207476 kb
Host smart-b3ce7f69-52b7-4b2c-af4f-7a891f31e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559228223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1559228223
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1616984072
Short name T811
Test name
Test status
Simulation time 59139616961 ps
CPU time 423.48 seconds
Started Aug 19 05:45:37 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 250144 kb
Host smart-a4187399-a23d-4960-8386-561dbac5c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616984072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1616984072
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2742262686
Short name T297
Test name
Test status
Simulation time 232719342 ps
CPU time 3.56 seconds
Started Aug 19 05:45:37 PM PDT 24
Finished Aug 19 05:45:40 PM PDT 24
Peak memory 225404 kb
Host smart-28e52bba-04fe-4472-b5bb-5fa17c24da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742262686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2742262686
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2472446936
Short name T490
Test name
Test status
Simulation time 694133274 ps
CPU time 4.2 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:45:49 PM PDT 24
Peak memory 233628 kb
Host smart-db274857-7e6f-46af-ac39-ea09705b8c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472446936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2472446936
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1566677182
Short name T874
Test name
Test status
Simulation time 5561882753 ps
CPU time 41.08 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:46:20 PM PDT 24
Peak memory 241788 kb
Host smart-1b3bc229-3ad9-47a3-bb2c-52a12920cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566677182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1566677182
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.508974863
Short name T450
Test name
Test status
Simulation time 486409117 ps
CPU time 7.01 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:45 PM PDT 24
Peak memory 233600 kb
Host smart-fe66ad39-3f78-481b-a8a9-824d9122679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508974863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.508974863
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3964850320
Short name T868
Test name
Test status
Simulation time 2784734192 ps
CPU time 6.71 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:45 PM PDT 24
Peak memory 233748 kb
Host smart-98154a1a-1059-4505-b609-23c94c8b149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964850320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3964850320
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1599564763
Short name T964
Test name
Test status
Simulation time 205089839 ps
CPU time 4.88 seconds
Started Aug 19 05:45:41 PM PDT 24
Finished Aug 19 05:45:46 PM PDT 24
Peak memory 224032 kb
Host smart-0d2aad51-a5b2-427d-a9b8-d4e330c72bbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1599564763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1599564763
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3173891336
Short name T144
Test name
Test status
Simulation time 4116689611 ps
CPU time 62.9 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:46:48 PM PDT 24
Peak memory 255984 kb
Host smart-dd018e1d-3235-4ad4-b249-01a08ab16999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173891336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3173891336
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2251709352
Short name T859
Test name
Test status
Simulation time 1769357921 ps
CPU time 22.39 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:46:00 PM PDT 24
Peak memory 217640 kb
Host smart-16b7e6a5-b9ed-4335-b5d3-958502d40661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251709352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2251709352
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3872514697
Short name T531
Test name
Test status
Simulation time 2036681524 ps
CPU time 7.17 seconds
Started Aug 19 05:45:35 PM PDT 24
Finished Aug 19 05:45:43 PM PDT 24
Peak memory 217100 kb
Host smart-25d18d93-f7e2-4a42-bb26-71391744626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872514697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3872514697
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.121903341
Short name T361
Test name
Test status
Simulation time 696323077 ps
CPU time 3 seconds
Started Aug 19 05:45:38 PM PDT 24
Finished Aug 19 05:45:42 PM PDT 24
Peak memory 217180 kb
Host smart-82939927-8ecd-4149-a4f7-5f7e168ac75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121903341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.121903341
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3354679079
Short name T616
Test name
Test status
Simulation time 102382743 ps
CPU time 0.86 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:40 PM PDT 24
Peak memory 207892 kb
Host smart-54fa741d-7f74-4809-96b2-b8b097e4098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354679079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3354679079
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2401041108
Short name T430
Test name
Test status
Simulation time 19834953722 ps
CPU time 18.31 seconds
Started Aug 19 05:45:39 PM PDT 24
Finished Aug 19 05:45:58 PM PDT 24
Peak memory 233700 kb
Host smart-4417737a-7d29-495f-8a19-a2a128cf2dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401041108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2401041108
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2191016756
Short name T657
Test name
Test status
Simulation time 14655708 ps
CPU time 0.75 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 206608 kb
Host smart-58df9634-97c3-4981-90c9-8a12f4594514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191016756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2191016756
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2659509659
Short name T541
Test name
Test status
Simulation time 203958049 ps
CPU time 2.36 seconds
Started Aug 19 05:45:54 PM PDT 24
Finished Aug 19 05:45:57 PM PDT 24
Peak memory 224780 kb
Host smart-34579cca-7920-42a0-a609-179df1f45361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659509659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2659509659
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3312457584
Short name T625
Test name
Test status
Simulation time 19984974 ps
CPU time 0.77 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:45:46 PM PDT 24
Peak memory 207788 kb
Host smart-ee41cbed-8f94-4119-a284-69917312ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312457584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3312457584
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1329129934
Short name T66
Test name
Test status
Simulation time 7513111038 ps
CPU time 46.71 seconds
Started Aug 19 05:45:48 PM PDT 24
Finished Aug 19 05:46:34 PM PDT 24
Peak memory 253136 kb
Host smart-8f32149f-4273-417e-a81f-8bbed7d5601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329129934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1329129934
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1296264825
Short name T946
Test name
Test status
Simulation time 157557981923 ps
CPU time 696.37 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:57:22 PM PDT 24
Peak memory 258440 kb
Host smart-5dd3d77b-da32-4e26-b16e-fa0d9a83cde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296264825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1296264825
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3128541839
Short name T527
Test name
Test status
Simulation time 31317429624 ps
CPU time 78.5 seconds
Started Aug 19 05:45:48 PM PDT 24
Finished Aug 19 05:47:06 PM PDT 24
Peak memory 250232 kb
Host smart-7bc943a8-4b09-4c49-b5d0-f729e73c77f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128541839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3128541839
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.826505847
Short name T136
Test name
Test status
Simulation time 2272518633 ps
CPU time 15 seconds
Started Aug 19 05:45:44 PM PDT 24
Finished Aug 19 05:46:00 PM PDT 24
Peak memory 225564 kb
Host smart-4705048c-c77f-40e0-a170-e06a1a906cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826505847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.826505847
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4023200048
Short name T808
Test name
Test status
Simulation time 6426108156 ps
CPU time 31.63 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:46:19 PM PDT 24
Peak memory 252644 kb
Host smart-f0faf2bb-2f09-4b53-9565-2edc66c86962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023200048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4023200048
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2707598732
Short name T215
Test name
Test status
Simulation time 920937404 ps
CPU time 4.01 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:45:51 PM PDT 24
Peak memory 225316 kb
Host smart-ec7f995c-2cc9-431c-b0f8-3ec67b626be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707598732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2707598732
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.917085283
Short name T231
Test name
Test status
Simulation time 616630218 ps
CPU time 12.94 seconds
Started Aug 19 05:45:44 PM PDT 24
Finished Aug 19 05:45:57 PM PDT 24
Peak memory 241092 kb
Host smart-e1482d4b-c0b0-4b8c-a46e-e990fd986a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917085283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.917085283
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3263340907
Short name T939
Test name
Test status
Simulation time 13913860897 ps
CPU time 35.08 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:46:21 PM PDT 24
Peak memory 249916 kb
Host smart-45f93108-0ce3-4d55-9b95-795dbe86149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263340907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3263340907
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2186503396
Short name T626
Test name
Test status
Simulation time 32724727 ps
CPU time 2.36 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:49 PM PDT 24
Peak memory 233308 kb
Host smart-6c7b2575-b77b-45fc-903c-1628a07728d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186503396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2186503396
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1958107850
Short name T355
Test name
Test status
Simulation time 2746137775 ps
CPU time 9.38 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:57 PM PDT 24
Peak memory 223840 kb
Host smart-c7a5f2f4-0056-4c76-840e-53b50bb9bbbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1958107850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1958107850
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1584126327
Short name T471
Test name
Test status
Simulation time 107159793951 ps
CPU time 226.5 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:49:32 PM PDT 24
Peak memory 251628 kb
Host smart-29a56dd2-d28b-49c7-84e0-c9ed8031c10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584126327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1584126327
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1013742532
Short name T739
Test name
Test status
Simulation time 2668690933 ps
CPU time 24.51 seconds
Started Aug 19 05:45:43 PM PDT 24
Finished Aug 19 05:46:07 PM PDT 24
Peak memory 221312 kb
Host smart-4b3942bd-4e13-46f2-b88a-6ce8d2974911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013742532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1013742532
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4257405303
Short name T934
Test name
Test status
Simulation time 12100102 ps
CPU time 0.7 seconds
Started Aug 19 05:45:55 PM PDT 24
Finished Aug 19 05:45:56 PM PDT 24
Peak memory 206560 kb
Host smart-eb19d1d1-b875-4455-8863-8aecfb466e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257405303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4257405303
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.125144957
Short name T340
Test name
Test status
Simulation time 176781481 ps
CPU time 1.95 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:49 PM PDT 24
Peak memory 217212 kb
Host smart-1f66c3d5-c484-40b2-bdf5-bb9c5445a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125144957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.125144957
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.533381605
Short name T896
Test name
Test status
Simulation time 24157129 ps
CPU time 0.8 seconds
Started Aug 19 05:45:48 PM PDT 24
Finished Aug 19 05:45:49 PM PDT 24
Peak memory 206908 kb
Host smart-1d0386cd-802c-4174-9042-94bd0d88e626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533381605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.533381605
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2177621310
Short name T193
Test name
Test status
Simulation time 3440786171 ps
CPU time 3.49 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 225540 kb
Host smart-a5089853-1b85-4184-8711-14a66e06511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177621310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2177621310
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.389897063
Short name T567
Test name
Test status
Simulation time 22540816 ps
CPU time 0.72 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:45:47 PM PDT 24
Peak memory 206640 kb
Host smart-45de95ea-ea19-4ff2-ba31-0663350cd6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389897063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.389897063
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1061339493
Short name T635
Test name
Test status
Simulation time 1749015611 ps
CPU time 13.27 seconds
Started Aug 19 05:45:55 PM PDT 24
Finished Aug 19 05:46:08 PM PDT 24
Peak memory 225372 kb
Host smart-035fb908-0d8c-4a2a-a32c-b142b557e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061339493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1061339493
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3753125526
Short name T308
Test name
Test status
Simulation time 60017382 ps
CPU time 0.79 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 206740 kb
Host smart-00acff2c-6bd0-4e84-9fcf-ed7d03848b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753125526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3753125526
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.315086334
Short name T777
Test name
Test status
Simulation time 1794775050 ps
CPU time 31.91 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:46:18 PM PDT 24
Peak memory 249952 kb
Host smart-e11ec9f2-d28e-4d2b-88d5-f20c52f82e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315086334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.315086334
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1713270379
Short name T65
Test name
Test status
Simulation time 7466004305 ps
CPU time 57.37 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:46:44 PM PDT 24
Peak memory 225672 kb
Host smart-ca46b5d6-56c9-4387-806f-d744a252fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713270379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1713270379
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3333439952
Short name T290
Test name
Test status
Simulation time 1691313288 ps
CPU time 7.45 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:54 PM PDT 24
Peak memory 218532 kb
Host smart-9cc1fb43-1dce-4150-87c7-1c72e2967b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333439952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3333439952
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2356915297
Short name T363
Test name
Test status
Simulation time 120204474 ps
CPU time 3.09 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 225392 kb
Host smart-714fa9c9-f1ff-4f93-960c-cb58cfe78d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356915297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2356915297
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2265482040
Short name T940
Test name
Test status
Simulation time 2824219645 ps
CPU time 54.7 seconds
Started Aug 19 05:45:44 PM PDT 24
Finished Aug 19 05:46:39 PM PDT 24
Peak memory 252532 kb
Host smart-294c743c-158e-4a67-9d51-4babe4a6f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265482040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2265482040
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2917132525
Short name T970
Test name
Test status
Simulation time 12377592200 ps
CPU time 27.7 seconds
Started Aug 19 05:45:48 PM PDT 24
Finished Aug 19 05:46:16 PM PDT 24
Peak memory 225560 kb
Host smart-722e192d-c8c8-41dc-bb14-68de1ec1cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917132525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2917132525
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.890092776
Short name T809
Test name
Test status
Simulation time 3631129431 ps
CPU time 22.15 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:46:09 PM PDT 24
Peak memory 251952 kb
Host smart-672a187f-152b-4f92-ba88-4bdac8582ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890092776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.890092776
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2823599919
Short name T926
Test name
Test status
Simulation time 974161931 ps
CPU time 6.68 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:45:52 PM PDT 24
Peak memory 233648 kb
Host smart-298e1ffd-4ba3-42c2-8bb7-6b8f54190178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823599919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2823599919
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.344338525
Short name T736
Test name
Test status
Simulation time 5497236576 ps
CPU time 8.86 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:56 PM PDT 24
Peak memory 233748 kb
Host smart-50985787-978a-46e3-a459-94a92ebddd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344338525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.344338525
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3413774564
Short name T135
Test name
Test status
Simulation time 259117900 ps
CPU time 4.01 seconds
Started Aug 19 05:45:46 PM PDT 24
Finished Aug 19 05:45:50 PM PDT 24
Peak memory 220196 kb
Host smart-1f493b5f-781b-439f-98db-b4cf4b515774
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3413774564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3413774564
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2636371504
Short name T556
Test name
Test status
Simulation time 34469042033 ps
CPU time 143.64 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:48:09 PM PDT 24
Peak memory 254796 kb
Host smart-27c42980-597a-4241-b91c-89f362ad4d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636371504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2636371504
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.298089585
Short name T7
Test name
Test status
Simulation time 8814666856 ps
CPU time 23.08 seconds
Started Aug 19 05:45:52 PM PDT 24
Finished Aug 19 05:46:15 PM PDT 24
Peak memory 217372 kb
Host smart-24ea133d-fa99-4f84-ab0c-9dcd5751b4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298089585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.298089585
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4111453444
Short name T973
Test name
Test status
Simulation time 2378928337 ps
CPU time 4.31 seconds
Started Aug 19 05:45:45 PM PDT 24
Finished Aug 19 05:45:49 PM PDT 24
Peak memory 217252 kb
Host smart-f65080ac-08ae-4b12-961d-87adf0ebd33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111453444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4111453444
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.50753350
Short name T844
Test name
Test status
Simulation time 25988082 ps
CPU time 1.02 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:45:48 PM PDT 24
Peak memory 207680 kb
Host smart-1eb670bb-75cc-489c-827d-bf578ac0d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50753350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.50753350
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4004249153
Short name T338
Test name
Test status
Simulation time 139850057 ps
CPU time 0.8 seconds
Started Aug 19 05:45:55 PM PDT 24
Finished Aug 19 05:45:56 PM PDT 24
Peak memory 206868 kb
Host smart-e6fc4e22-7f21-41fd-bdf0-d436d81971b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004249153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4004249153
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.437250509
Short name T690
Test name
Test status
Simulation time 14478731726 ps
CPU time 38.92 seconds
Started Aug 19 05:45:47 PM PDT 24
Finished Aug 19 05:46:26 PM PDT 24
Peak memory 233684 kb
Host smart-6572cf54-5bb5-41c5-a498-7f85a08cb5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437250509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.437250509
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1965904955
Short name T654
Test name
Test status
Simulation time 34551071 ps
CPU time 0.73 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:06 PM PDT 24
Peak memory 206308 kb
Host smart-5842f5c1-5293-4ee5-b34f-49fb534056e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965904955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
965904955
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3216713307
Short name T330
Test name
Test status
Simulation time 61766495 ps
CPU time 2.51 seconds
Started Aug 19 05:43:01 PM PDT 24
Finished Aug 19 05:43:04 PM PDT 24
Peak memory 233216 kb
Host smart-73167b83-35d6-40cf-8207-f4a1f9da3317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216713307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3216713307
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3239766564
Short name T386
Test name
Test status
Simulation time 18627570 ps
CPU time 0.81 seconds
Started Aug 19 05:42:49 PM PDT 24
Finished Aug 19 05:42:50 PM PDT 24
Peak memory 207704 kb
Host smart-edfa1f5b-ce4d-43de-b9d9-7b5ec0c7b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239766564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3239766564
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1903724532
Short name T506
Test name
Test status
Simulation time 7777687083 ps
CPU time 47.99 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:52 PM PDT 24
Peak memory 240488 kb
Host smart-8ecaa4b5-e85d-4d8b-9954-edbd94046310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903724532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1903724532
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1114861732
Short name T638
Test name
Test status
Simulation time 6936203654 ps
CPU time 48.34 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:53 PM PDT 24
Peak memory 242076 kb
Host smart-ad2639b7-4af9-4ff6-8371-9158e0dc5710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114861732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1114861732
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.820268972
Short name T771
Test name
Test status
Simulation time 21962617940 ps
CPU time 216.34 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:46:42 PM PDT 24
Peak memory 250272 kb
Host smart-855d83ce-2b30-427c-af06-7e40ffaa1e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820268972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
820268972
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1410940671
Short name T203
Test name
Test status
Simulation time 1587403139 ps
CPU time 21.17 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:27 PM PDT 24
Peak memory 235188 kb
Host smart-72e73610-50dc-450f-93ee-60406e793664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410940671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1410940671
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.94272875
Short name T550
Test name
Test status
Simulation time 10681868413 ps
CPU time 43.85 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:48 PM PDT 24
Peak memory 250136 kb
Host smart-585f7340-bfdd-4b7c-ab2b-01e912bf5dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94272875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.94272875
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.472600854
Short name T658
Test name
Test status
Simulation time 6622705958 ps
CPU time 13.54 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 233772 kb
Host smart-ff9b585c-2b4c-4247-bc0f-90c8a082e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472600854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.472600854
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.996289563
Short name T768
Test name
Test status
Simulation time 645867922 ps
CPU time 13.77 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 236536 kb
Host smart-085ed268-2ed9-42ef-8f6e-e734f2b987a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996289563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.996289563
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3476463557
Short name T173
Test name
Test status
Simulation time 3758509697 ps
CPU time 10.03 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:15 PM PDT 24
Peak memory 233744 kb
Host smart-8a39865f-abfd-4f43-9519-89bae1e48a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476463557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3476463557
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3053760938
Short name T250
Test name
Test status
Simulation time 14308294554 ps
CPU time 20.7 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:29 PM PDT 24
Peak memory 241468 kb
Host smart-26b720ad-c32c-4f2c-8c6e-381e5e2bd405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053760938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3053760938
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3860582181
Short name T938
Test name
Test status
Simulation time 1636191818 ps
CPU time 9.84 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:16 PM PDT 24
Peak memory 222944 kb
Host smart-bca526d4-9fbf-449d-b319-782bfac52ed6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3860582181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3860582181
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3386353553
Short name T63
Test name
Test status
Simulation time 248459137315 ps
CPU time 521.75 seconds
Started Aug 19 05:43:07 PM PDT 24
Finished Aug 19 05:51:48 PM PDT 24
Peak memory 255796 kb
Host smart-e4909102-e655-477e-9de0-131b53b379fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386353553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3386353553
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1621157360
Short name T562
Test name
Test status
Simulation time 2277724324 ps
CPU time 9.34 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 217584 kb
Host smart-890d9e1e-d11b-4d97-b65c-c9fcddd2fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621157360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1621157360
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.586951955
Short name T733
Test name
Test status
Simulation time 1627303470 ps
CPU time 3.6 seconds
Started Aug 19 05:42:57 PM PDT 24
Finished Aug 19 05:43:01 PM PDT 24
Peak memory 217152 kb
Host smart-74c665ae-8875-456b-9ec6-b658a4680fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586951955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.586951955
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.417575077
Short name T827
Test name
Test status
Simulation time 689281481 ps
CPU time 1.36 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:05 PM PDT 24
Peak memory 217196 kb
Host smart-6f925e4a-a379-436a-9cc0-3f9d5e9911da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417575077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.417575077
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2155783618
Short name T352
Test name
Test status
Simulation time 32282357 ps
CPU time 0.88 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:05 PM PDT 24
Peak memory 206816 kb
Host smart-132c59ce-7ecd-46fe-9e4f-689d66c2f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155783618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2155783618
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.36838226
Short name T728
Test name
Test status
Simulation time 18177268128 ps
CPU time 7.13 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 225588 kb
Host smart-964671a0-0519-493b-b417-6895897026f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36838226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.36838226
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.921557866
Short name T716
Test name
Test status
Simulation time 10596640 ps
CPU time 0.72 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:43:04 PM PDT 24
Peak memory 205664 kb
Host smart-fedca0c9-f922-43d3-8592-851156ca6db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921557866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.921557866
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2083388895
Short name T311
Test name
Test status
Simulation time 7238515384 ps
CPU time 24.46 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:30 PM PDT 24
Peak memory 225596 kb
Host smart-7454f21d-c0af-4c94-8900-525bc0bd664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083388895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2083388895
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2032151524
Short name T320
Test name
Test status
Simulation time 59367908 ps
CPU time 0.78 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:07 PM PDT 24
Peak memory 207808 kb
Host smart-e4f8f707-f98a-4270-afe2-380fc5487b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032151524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2032151524
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1191674707
Short name T68
Test name
Test status
Simulation time 2286867962 ps
CPU time 49.54 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:56 PM PDT 24
Peak memory 256948 kb
Host smart-73395d70-a445-41ff-b784-686e40515134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191674707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1191674707
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.710725295
Short name T434
Test name
Test status
Simulation time 15574733625 ps
CPU time 77.54 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:44:20 PM PDT 24
Peak memory 239792 kb
Host smart-10426654-cf6c-42d1-8cf1-3b32dee2d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710725295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.710725295
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1760090972
Short name T174
Test name
Test status
Simulation time 25306708408 ps
CPU time 41.08 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:46 PM PDT 24
Peak memory 242072 kb
Host smart-56ff3a49-6699-4b2b-9970-ec23803b944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760090972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1760090972
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1355150453
Short name T872
Test name
Test status
Simulation time 789706224 ps
CPU time 13.31 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 234596 kb
Host smart-94580e50-fb25-4f4a-b036-13fa8dcb3fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355150453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1355150453
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1439368780
Short name T994
Test name
Test status
Simulation time 354176834 ps
CPU time 4.13 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:43:07 PM PDT 24
Peak memory 225384 kb
Host smart-f156ea86-0b79-45be-909f-482ebe8635b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439368780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1439368780
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1473810435
Short name T738
Test name
Test status
Simulation time 547588086 ps
CPU time 12.12 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 223544 kb
Host smart-e047bb5d-f51f-45fd-a4c0-29cfd4e7ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473810435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1473810435
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2588380898
Short name T195
Test name
Test status
Simulation time 316235286 ps
CPU time 4.24 seconds
Started Aug 19 05:43:02 PM PDT 24
Finished Aug 19 05:43:06 PM PDT 24
Peak memory 233628 kb
Host smart-cc419e10-365c-41ab-84ef-20551427b772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588380898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2588380898
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.387625697
Short name T624
Test name
Test status
Simulation time 6064775771 ps
CPU time 15.25 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 241764 kb
Host smart-30121159-155b-4e06-8d8b-a7db531bcd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387625697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.387625697
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2901152847
Short name T462
Test name
Test status
Simulation time 1234851550 ps
CPU time 9.86 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 222812 kb
Host smart-78cfa72d-9390-4cc1-993c-8a6f5cb2ddf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2901152847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2901152847
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2850906327
Short name T860
Test name
Test status
Simulation time 6779605975 ps
CPU time 119.38 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:45:05 PM PDT 24
Peak memory 256112 kb
Host smart-de2df017-0112-49ba-82a9-599d56314f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850906327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2850906327
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4026602400
Short name T499
Test name
Test status
Simulation time 12011210999 ps
CPU time 31.91 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:36 PM PDT 24
Peak memory 217240 kb
Host smart-172d5576-668f-4e8a-965a-de6522a6673c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026602400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4026602400
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4223948311
Short name T359
Test name
Test status
Simulation time 4688774618 ps
CPU time 7.76 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 217300 kb
Host smart-45abdd44-55d8-4778-92e4-40d7f24f72a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223948311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4223948311
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3360145769
Short name T636
Test name
Test status
Simulation time 447553075 ps
CPU time 1.93 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:07 PM PDT 24
Peak memory 215516 kb
Host smart-6f7129f1-217c-4ec5-b6d7-b17353afaf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360145769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3360145769
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4068789674
Short name T591
Test name
Test status
Simulation time 73949738 ps
CPU time 0.95 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:05 PM PDT 24
Peak memory 207892 kb
Host smart-604dd00c-b675-4bc2-ba2e-25e05ef5b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068789674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4068789674
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4059996704
Short name T913
Test name
Test status
Simulation time 8164971483 ps
CPU time 13.13 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:18 PM PDT 24
Peak memory 240924 kb
Host smart-580f564d-b77b-41ed-8651-956658541590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059996704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4059996704
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.829736395
Short name T853
Test name
Test status
Simulation time 12399439 ps
CPU time 0.72 seconds
Started Aug 19 05:43:10 PM PDT 24
Finished Aug 19 05:43:11 PM PDT 24
Peak memory 205736 kb
Host smart-41d0e265-478a-440c-b4a5-5d88c35fa3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829736395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.829736395
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3482359954
Short name T428
Test name
Test status
Simulation time 120158627 ps
CPU time 2.19 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:07 PM PDT 24
Peak memory 233120 kb
Host smart-33545ff9-aecc-4291-8a82-0c2912cc1d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482359954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3482359954
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3507658548
Short name T480
Test name
Test status
Simulation time 46549885 ps
CPU time 0.72 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 206432 kb
Host smart-0a02b644-0d4c-4f9c-883a-6df73c31efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507658548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3507658548
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4042547047
Short name T185
Test name
Test status
Simulation time 21781452051 ps
CPU time 150.72 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:45:39 PM PDT 24
Peak memory 225548 kb
Host smart-63472a40-c23d-495c-a245-bf1662187bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042547047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4042547047
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4038848027
Short name T792
Test name
Test status
Simulation time 118937563311 ps
CPU time 432.41 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:50:22 PM PDT 24
Peak memory 264748 kb
Host smart-b448e508-a739-4c9a-8d7f-daf9977c8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038848027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4038848027
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3747068152
Short name T597
Test name
Test status
Simulation time 43482426171 ps
CPU time 335.51 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:48:41 PM PDT 24
Peak memory 257368 kb
Host smart-a54471af-296a-4225-b1ff-be68897e05b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747068152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3747068152
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.212607207
Short name T731
Test name
Test status
Simulation time 852245466 ps
CPU time 5.2 seconds
Started Aug 19 05:43:02 PM PDT 24
Finished Aug 19 05:43:07 PM PDT 24
Peak memory 235984 kb
Host smart-be1deb0a-a1b0-4490-859b-ae07020d2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212607207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.212607207
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2403771144
Short name T784
Test name
Test status
Simulation time 24281786132 ps
CPU time 48.99 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:43:52 PM PDT 24
Peak memory 225480 kb
Host smart-c48a1e69-5ff2-494b-9def-eb0b82c0bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403771144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2403771144
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2870534750
Short name T985
Test name
Test status
Simulation time 126896085 ps
CPU time 5.13 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:10 PM PDT 24
Peak memory 225468 kb
Host smart-0e8af093-fbe5-4a5c-aecb-91a3693f2a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870534750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2870534750
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2752292403
Short name T612
Test name
Test status
Simulation time 99447800 ps
CPU time 2 seconds
Started Aug 19 05:43:07 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 224836 kb
Host smart-47818355-5971-4ace-8cfc-17744805f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752292403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2752292403
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.819389038
Short name T603
Test name
Test status
Simulation time 263688691 ps
CPU time 2.54 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:08 PM PDT 24
Peak memory 233564 kb
Host smart-4a801e0a-5253-4ca3-bd7e-d45d76aa049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819389038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
819389038
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1071346721
Short name T864
Test name
Test status
Simulation time 15171952072 ps
CPU time 13.33 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 233676 kb
Host smart-020cc7b3-f0e9-4c29-afb4-9904cde0f4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071346721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1071346721
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3934293404
Short name T829
Test name
Test status
Simulation time 181635390 ps
CPU time 4.33 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:10 PM PDT 24
Peak memory 220216 kb
Host smart-b32d33c7-f643-4f35-a4bb-ad6f75a2edbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3934293404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3934293404
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3621595939
Short name T218
Test name
Test status
Simulation time 46573437211 ps
CPU time 414.27 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:50:00 PM PDT 24
Peak memory 274772 kb
Host smart-e0e29a8c-c54c-45e2-90a9-762f9394cc55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621595939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3621595939
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1026838233
Short name T987
Test name
Test status
Simulation time 259692293 ps
CPU time 5.8 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:11 PM PDT 24
Peak memory 217200 kb
Host smart-408aed56-fd82-495a-bd45-6df2baa61e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026838233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1026838233
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3538426792
Short name T842
Test name
Test status
Simulation time 675508663 ps
CPU time 2.83 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:08 PM PDT 24
Peak memory 217192 kb
Host smart-3770c915-3fea-4d95-b4d3-db19d0754102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538426792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3538426792
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.431900136
Short name T4
Test name
Test status
Simulation time 418541561 ps
CPU time 4.17 seconds
Started Aug 19 05:43:02 PM PDT 24
Finished Aug 19 05:43:06 PM PDT 24
Peak memory 217240 kb
Host smart-e7440c34-87b9-4d2c-ba28-4eefb8d7368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431900136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.431900136
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.176123238
Short name T353
Test name
Test status
Simulation time 51830088 ps
CPU time 0.84 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:10 PM PDT 24
Peak memory 206880 kb
Host smart-0f14047a-01b8-4283-8e90-90509548697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176123238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.176123238
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1226903771
Short name T375
Test name
Test status
Simulation time 4206209732 ps
CPU time 9.64 seconds
Started Aug 19 05:43:07 PM PDT 24
Finished Aug 19 05:43:16 PM PDT 24
Peak memory 230096 kb
Host smart-6c9e3840-7470-4891-b0b7-e97fc9329893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226903771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1226903771
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1412153734
Short name T633
Test name
Test status
Simulation time 45298101 ps
CPU time 0.73 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 205656 kb
Host smart-997ded5f-2c6c-4f5e-bcb9-199bfa8e8ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412153734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
412153734
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.117527975
Short name T689
Test name
Test status
Simulation time 1776127276 ps
CPU time 9.43 seconds
Started Aug 19 05:43:10 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 233540 kb
Host smart-a5bbfb6c-3c7f-46f0-9cc8-c771a181c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117527975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.117527975
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1475432343
Short name T476
Test name
Test status
Simulation time 14898603 ps
CPU time 0.78 seconds
Started Aug 19 05:43:03 PM PDT 24
Finished Aug 19 05:43:04 PM PDT 24
Peak memory 206444 kb
Host smart-e270e6de-576c-48ee-b979-e9f57fe4f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475432343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1475432343
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2184730045
Short name T880
Test name
Test status
Simulation time 43390748344 ps
CPU time 358.63 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:49:13 PM PDT 24
Peak memory 270040 kb
Host smart-3441a760-b0a6-4d6b-a80e-a9bdce6a20e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184730045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2184730045
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.903751793
Short name T28
Test name
Test status
Simulation time 11428256497 ps
CPU time 100.13 seconds
Started Aug 19 05:43:19 PM PDT 24
Finished Aug 19 05:44:59 PM PDT 24
Peak memory 250276 kb
Host smart-d1cd7a8a-ebef-41ff-bb61-f317b7201b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903751793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.903751793
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3504557937
Short name T196
Test name
Test status
Simulation time 3164408112 ps
CPU time 74.79 seconds
Started Aug 19 05:43:15 PM PDT 24
Finished Aug 19 05:44:30 PM PDT 24
Peak memory 265572 kb
Host smart-bf2287c1-1991-462e-b8b3-0a89fd35c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504557937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3504557937
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3854700583
Short name T498
Test name
Test status
Simulation time 34737684 ps
CPU time 2.63 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:11 PM PDT 24
Peak memory 233564 kb
Host smart-e2acb526-b763-40ac-9689-74df3c8f3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854700583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3854700583
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2647844744
Short name T13
Test name
Test status
Simulation time 10972737494 ps
CPU time 104.85 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:44:53 PM PDT 24
Peak memory 250112 kb
Host smart-53a74ffa-68f7-4ddf-b0ac-183d69d69e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647844744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2647844744
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2358260332
Short name T178
Test name
Test status
Simulation time 296469071 ps
CPU time 5.46 seconds
Started Aug 19 05:43:07 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 225444 kb
Host smart-c3ea7994-9ad5-48e4-ac8a-bbe70cd29860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358260332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2358260332
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2337580139
Short name T669
Test name
Test status
Simulation time 10177689205 ps
CPU time 35.29 seconds
Started Aug 19 05:43:11 PM PDT 24
Finished Aug 19 05:43:47 PM PDT 24
Peak memory 233764 kb
Host smart-f1821265-38e0-4966-baa0-e448f68e4629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337580139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2337580139
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2726154218
Short name T634
Test name
Test status
Simulation time 1121506037 ps
CPU time 8.53 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:26 PM PDT 24
Peak memory 233632 kb
Host smart-a168a3b3-1c4b-449c-b831-d03412a7d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726154218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2726154218
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1102762569
Short name T554
Test name
Test status
Simulation time 7279974654 ps
CPU time 6.45 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:11 PM PDT 24
Peak memory 233684 kb
Host smart-e4163302-09b4-4be0-8657-e870432e5392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102762569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1102762569
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3144246039
Short name T8
Test name
Test status
Simulation time 657783638 ps
CPU time 4.51 seconds
Started Aug 19 05:43:15 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 221396 kb
Host smart-23881cf9-cf37-4259-805c-231cb23eda5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3144246039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3144246039
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3649033527
Short name T130
Test name
Test status
Simulation time 74497845300 ps
CPU time 830.09 seconds
Started Aug 19 05:43:11 PM PDT 24
Finished Aug 19 05:57:01 PM PDT 24
Peak memory 284948 kb
Host smart-d6034d5e-8d8f-49db-8411-d8845f9b5105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649033527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3649033527
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.765434534
Short name T982
Test name
Test status
Simulation time 2935931264 ps
CPU time 24.95 seconds
Started Aug 19 05:43:05 PM PDT 24
Finished Aug 19 05:43:31 PM PDT 24
Peak memory 221648 kb
Host smart-d46a6ac0-fe9c-420e-a732-4e18e7331ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765434534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.765434534
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3400350176
Short name T717
Test name
Test status
Simulation time 4045303204 ps
CPU time 6.83 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 217332 kb
Host smart-83fa4e7c-f67b-4244-b8af-31c17bf5a8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400350176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3400350176
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2596266510
Short name T582
Test name
Test status
Simulation time 195918744 ps
CPU time 1.07 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:06 PM PDT 24
Peak memory 207904 kb
Host smart-d28e8671-3ed6-4e29-865f-ceb63c38d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596266510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2596266510
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.539093730
Short name T377
Test name
Test status
Simulation time 117479123 ps
CPU time 0.89 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:05 PM PDT 24
Peak memory 207308 kb
Host smart-f7e40b9b-6bdd-49cc-a474-bf9d91fd4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539093730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.539093730
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.523347035
Short name T470
Test name
Test status
Simulation time 840513346 ps
CPU time 7.05 seconds
Started Aug 19 05:43:04 PM PDT 24
Finished Aug 19 05:43:11 PM PDT 24
Peak memory 219092 kb
Host smart-cade8ca8-cf05-466f-be72-7891497eb483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523347035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.523347035
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1533048513
Short name T509
Test name
Test status
Simulation time 15084263 ps
CPU time 0.74 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:19 PM PDT 24
Peak memory 206324 kb
Host smart-77c0152a-72b8-4749-8fff-168f1a6db464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533048513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
533048513
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.244785225
Short name T919
Test name
Test status
Simulation time 34851238 ps
CPU time 2.15 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:43:16 PM PDT 24
Peak memory 225392 kb
Host smart-998eb30b-7332-4bd8-8ab6-a6965600129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244785225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.244785225
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3774814110
Short name T720
Test name
Test status
Simulation time 17874762 ps
CPU time 0.77 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 207784 kb
Host smart-6b96e520-8f8f-4531-8394-2bdf9396c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774814110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3774814110
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1847967414
Short name T587
Test name
Test status
Simulation time 4993939567 ps
CPU time 20.79 seconds
Started Aug 19 05:43:10 PM PDT 24
Finished Aug 19 05:43:30 PM PDT 24
Peak memory 234808 kb
Host smart-5a875c68-9b0d-4244-8680-8d6959dd3bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847967414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1847967414
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4224475187
Short name T31
Test name
Test status
Simulation time 2959337198 ps
CPU time 25.03 seconds
Started Aug 19 05:43:10 PM PDT 24
Finished Aug 19 05:43:35 PM PDT 24
Peak memory 250192 kb
Host smart-18c745bc-aa44-4d3a-acc6-bc013b705fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224475187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4224475187
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4153740021
Short name T172
Test name
Test status
Simulation time 26443747774 ps
CPU time 92.34 seconds
Started Aug 19 05:43:13 PM PDT 24
Finished Aug 19 05:44:46 PM PDT 24
Peak memory 258312 kb
Host smart-978589e2-db50-4f34-9894-77f4098e6f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153740021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4153740021
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4145738288
Short name T508
Test name
Test status
Simulation time 241170061 ps
CPU time 4.49 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 225432 kb
Host smart-8e6059cf-deb9-46ca-aa78-0d0b37fc44ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145738288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4145738288
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.4142816797
Short name T831
Test name
Test status
Simulation time 23583121206 ps
CPU time 164.99 seconds
Started Aug 19 05:43:15 PM PDT 24
Finished Aug 19 05:46:00 PM PDT 24
Peak memory 269012 kb
Host smart-348aa33b-acf4-41a1-b1cd-8235c038f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142816797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.4142816797
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1152794574
Short name T802
Test name
Test status
Simulation time 187911136 ps
CPU time 6.28 seconds
Started Aug 19 05:43:14 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 225464 kb
Host smart-8928c796-05fd-4f48-af31-5af2dd08c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152794574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1152794574
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2736621738
Short name T895
Test name
Test status
Simulation time 350573672 ps
CPU time 6.16 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:16 PM PDT 24
Peak memory 238708 kb
Host smart-2db821b9-8854-4133-b853-358a14de2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736621738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2736621738
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.430464986
Short name T815
Test name
Test status
Simulation time 356566531 ps
CPU time 2.48 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 225384 kb
Host smart-90e809ed-bb65-4567-b7c8-d7fc99ab7c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430464986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
430464986
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2732803336
Short name T544
Test name
Test status
Simulation time 761706273 ps
CPU time 4.51 seconds
Started Aug 19 05:43:09 PM PDT 24
Finished Aug 19 05:43:14 PM PDT 24
Peak memory 225360 kb
Host smart-e8808fed-5e00-4454-ab96-7a6bb8ab7323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732803336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2732803336
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.512980248
Short name T999
Test name
Test status
Simulation time 945505649 ps
CPU time 8.46 seconds
Started Aug 19 05:43:06 PM PDT 24
Finished Aug 19 05:43:15 PM PDT 24
Peak memory 219656 kb
Host smart-39a1c4c1-6791-4698-83d7-9c2802173a94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512980248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.512980248
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3517795182
Short name T936
Test name
Test status
Simulation time 17690152774 ps
CPU time 40.33 seconds
Started Aug 19 05:43:11 PM PDT 24
Finished Aug 19 05:43:51 PM PDT 24
Peak memory 217368 kb
Host smart-2310c300-ef5f-4cb0-8f41-a294028201eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517795182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3517795182
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1900400097
Short name T941
Test name
Test status
Simulation time 214579739 ps
CPU time 2.21 seconds
Started Aug 19 05:43:18 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 217184 kb
Host smart-98a2c062-8620-451b-9027-2a1f6d8eef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900400097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1900400097
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1470527123
Short name T25
Test name
Test status
Simulation time 361767031 ps
CPU time 2.16 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:10 PM PDT 24
Peak memory 217272 kb
Host smart-284040a5-649d-43d3-acc3-318e7d46f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470527123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1470527123
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.928848900
Short name T1000
Test name
Test status
Simulation time 230194766 ps
CPU time 0.9 seconds
Started Aug 19 05:43:08 PM PDT 24
Finished Aug 19 05:43:09 PM PDT 24
Peak memory 206904 kb
Host smart-9a3cf5dd-a324-405c-819c-c02bd31526be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928848900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.928848900
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3941453744
Short name T210
Test name
Test status
Simulation time 741200396 ps
CPU time 5.09 seconds
Started Aug 19 05:43:12 PM PDT 24
Finished Aug 19 05:43:17 PM PDT 24
Peak memory 233636 kb
Host smart-d459e6a4-5699-46e9-b760-1ff65627cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941453744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3941453744
Directory /workspace/9.spi_device_upload/latest
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