Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2965845	1			T1	1		T2	1		T3	1
all_values[1]	2965845	1			T1	1		T2	1		T3	1
all_values[2]	2965845	1			T1	1		T2	1		T3	1
all_values[3]	2965845	1			T1	1		T2	1		T3	1
all_values[4]	2965845	1			T1	1		T2	1		T3	1
all_values[5]	2965845	1			T1	1		T2	1		T3	1
all_values[6]	2965845	1			T1	1		T2	1		T3	1
all_values[7]	2965845	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23158707

1

T1

8

T2

8

T3

8

auto[1]

568053

1

T24

55

T34

115

T35

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23699580

1

T1

8

T2

8

T3

8

auto[1]

27180

1

T24

33

T56

39

T34

106

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2870262	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12966	1			T24	4		T56	20		T34	6
all_values[0]	auto[1]	auto[0]	82103	1			T24	3		T34	9		T35	8
all_values[0]	auto[1]	auto[1]	514	1			T24	3		T34	7		T35	8
all_values[1]	auto[0]	auto[0]	2878888	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8378	1			T24	1		T56	19		T34	10
all_values[1]	auto[1]	auto[0]	78161	1			T24	10		T34	5		T35	3
all_values[1]	auto[1]	auto[1]	418	1			T24	2		T34	6		T35	3
all_values[2]	auto[0]	auto[0]	2855418	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2564	1			T24	6		T34	10		T108	9
all_values[2]	auto[1]	auto[0]	107509	1			T24	1		T34	6		T36	7
all_values[2]	auto[1]	auto[1]	354	1			T24	3		T34	6		T35	2
all_values[3]	auto[0]	auto[0]	2878290	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	229	1			T34	6		T35	9		T36	1
all_values[3]	auto[1]	auto[0]	87138	1			T24	4		T34	12		T35	2
all_values[3]	auto[1]	auto[1]	188	1			T24	3		T34	5		T35	1
all_values[4]	auto[0]	auto[0]	2940909	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	213	1			T24	3		T34	10		T120	2
all_values[4]	auto[1]	auto[0]	24510	1			T24	5		T34	10		T35	4
all_values[4]	auto[1]	auto[1]	213	1			T24	1		T34	7		T35	6
all_values[5]	auto[0]	auto[0]	2905922	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	183	1			T24	2		T34	7		T35	4
all_values[5]	auto[1]	auto[0]	59558	1			T24	4		T34	5		T35	4
all_values[5]	auto[1]	auto[1]	182	1			T24	1		T34	7		T35	1
all_values[6]	auto[0]	auto[0]	2926985	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	159	1			T34	8		T35	5		T36	5
all_values[6]	auto[1]	auto[0]	38489	1			T24	5		T34	6		T35	5
all_values[6]	auto[1]	auto[1]	212	1			T34	5		T35	4		T36	5
all_values[7]	auto[0]	auto[0]	2877156	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	185	1			T34	1		T35	5		T36	8
all_values[7]	auto[1]	auto[0]	88282	1			T24	6		T34	14		T35	4
all_values[7]	auto[1]	auto[1]	222	1			T24	4		T34	5		T35	7