Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34759	1			T3	4		T15	21		T19	8
auto[SpiFlashAddrCfg]	7770	1			T3	2		T15	2		T16	4
auto[SpiFlashAddr3b]	9314	1			T3	6		T15	2		T23	19
auto[SpiFlashAddr4b]	7676	1			T18	3		T20	2		T23	29

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33960

1

T3

12

T15

25

T16

4

auto[1]

25559

1

T17

2

T23

148

T59

14

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32702

1

T3

12

T15

4

T16

4

auto[1]

26817

1

T15

21

T20

6

T23

143

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39599	1			T3	8		T15	21		T19	8
values[1]	1152	1			T79	2		T61	2		T55	2
values[2]	1424	1			T23	2		T80	1		T49	4
values[3]	1465	1			T15	2		T23	4		T59	4
values[4]	1479	1			T18	1		T23	8		T79	2
values[5]	1504	1			T23	1		T57	2		T79	6
values[6]	1372	1			T3	2		T15	2		T18	3
values[7]	1545	1			T23	4		T57	2		T59	2
values[8]	9979	1			T3	2		T16	4		T17	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30736

1

T3

12

T15

25

T16

4

auto[1]

28783

1

T18

5

T23

216

T50

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56231

1

T3

12

T15

25

T16

4

write

3288

1

T23

13

T60

2

T61

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19812

1

T3

4

T15

6

T16

4

valids[0x1]

39707

1

T3

8

T15

19

T17

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1621	1			T23	7		T60	2		T78	2
internal_process_ops[0x5a]	1533	1			T3	4		T23	8		T57	2
internal_process_ops[0x05]	20433	1			T3	4		T15	17		T23	98
internal_process_ops[0x35]	1567	1			T23	11		T125	2		T78	6
internal_process_ops[0x15]	1613	1			T23	6		T125	4		T122	6
internal_process_ops[0x03]	1036	1			T18	1		T23	1		T57	2
internal_process_ops[0x0b]	1010	1			T15	2		T18	1		T57	2
internal_process_ops[0x3b]	1049	1			T3	2		T101	2		T60	2
internal_process_ops[0x6b]	1074	1			T3	2		T16	4		T18	3
internal_process_ops[0xbb]	1095	1			T23	1		T50	1		T79	6
internal_process_ops[0xeb]	1002	1			T57	2		T58	2		T202	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57890

1

T3

12

T15

25

T16

4

auto[1]

1629

1

T23

7

T60

2

T61

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57125

1

T3

12

T15

23

T16

4

auto[1]

2394

1

T15

2

T23

7

T57

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10660

1

T3

4

T15

21

T19

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6251

1

T60

2

T61

2

T203

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2085

1

T3

2

T15

2

T16

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1772

1

T17

2

T59

6

T60

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2472

1

T3

6

T15

2

T57

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2182

1

T59

4

T60

6

T61

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2029

1

T20

2

T57

6

T101

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1731

1

T59

4

T60

2

T61

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T97

4

T204

4

T72

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

74

1

T124

1

T72

1

T74

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

90

1

T62

2

T65

1

T98

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T69

3

T74

3

T75

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

111

1

T62

2

T205

6

T92

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

73

1

T70

4

T73

1

T75

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

84

1

T70

2

T102

2

T72

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T70

6

T72

1

T74

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

121

1

T49

2

T205

2

T69

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T206

3

T53

1

T168

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

95

1

T62

1

T69

2

T72

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

128

1

T61

2

T65

4

T69

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T63

2

T97

2

T207

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

85

1

T124

2

T72

1

T73

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T65

1

T124

1

T102

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T60

2

T66

8

T69

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10070

1

T23

41

T55

13

T56

35

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6999

1

T23

105

T55

2

T56

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1562

1

T18

2

T23

11

T55

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1521

1

T23

4

T55

8

T56

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1976

1

T23

5

T80

1

T55

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1873

1

T23

11

T55

3

T56

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1488

1

T18

3

T23

5

T50

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1560

1

T23

21

T55

7

T56

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T55

1

T96

3

T208

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T56

3

T95

1

T108

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T23

1

T35

1

T99

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T23

3

T96

6

T108

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

134

1

T23

1

T209

4

T99

12

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T108

1

T109

1

T35

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T108

2

T109

2

T210

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

131

1

T23

2

T56

1

T96

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

100

1

T55

2

T95

2

T109

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T23

2

T95

1

T96

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T23

1

T95

1

T109

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T95

3

T96

5

T109

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T23

3

T56

1

T96

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

119

1

T96

1

T209

1

T211

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

132

1

T56

1

T95

2

T96

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

125

1

T95

2

T96

5

T108

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3920	1			T15	4		T19	8		T20	2
auto[0]	values[0]	valids[0x1]	15860	1			T3	8		T15	17		T57	11
auto[0]	values[1]	valids[0x1]	599	1			T79	2		T61	2		T212	4
auto[0]	values[2]	valids[0x0]	530	1			T49	4		T212	2		T201	2
auto[0]	values[2]	valids[0x1]	263	1			T63	4		T88	4		T65	1
auto[0]	values[3]	valids[0x0]	474	1			T59	4		T60	2		T62	3
auto[0]	values[3]	valids[0x1]	317	1			T15	2		T213	2		T69	3
auto[0]	values[4]	valids[0x0]	552	1			T79	2		T214	2		T205	2
auto[0]	values[4]	valids[0x1]	266	1			T202	2		T65	1		T69	1
auto[0]	values[5]	valids[0x0]	524	1			T57	2		T79	6		T65	6
auto[0]	values[5]	valids[0x1]	310	1			T122	2		T215	4		T69	4
auto[0]	values[6]	valids[0x0]	505	1			T3	2		T15	2		T60	2
auto[0]	values[6]	valids[0x1]	267	1			T101	4		T62	1		T69	2
auto[0]	values[7]	valids[0x0]	527	1			T59	2		T101	2		T60	4
auto[0]	values[7]	valids[0x1]	341	1			T57	2		T213	2		T62	1
auto[0]	values[8]	valids[0x0]	3496	1			T3	2		T16	4		T20	4
auto[0]	values[8]	valids[0x1]	1985	1			T17	2		T57	2		T61	2
auto[1]	values[0]	valids[0x0]	4284	1			T23	24		T55	9		T56	16
auto[1]	values[0]	valids[0x1]	15535	1			T23	139		T55	10		T56	30
auto[1]	values[1]	valids[0x1]	553	1			T55	2		T56	4		T95	7
auto[1]	values[2]	valids[0x0]	386	1			T23	2		T56	2		T95	2
auto[1]	values[2]	valids[0x1]	245	1			T80	1		T56	1		T96	3
auto[1]	values[3]	valids[0x0]	372	1			T23	1		T55	1		T174	1
auto[1]	values[3]	valids[0x1]	302	1			T23	3		T95	5		T109	7
auto[1]	values[4]	valids[0x0]	393	1			T23	4		T95	4		T96	4
auto[1]	values[4]	valids[0x1]	268	1			T18	1		T23	4		T55	3
auto[1]	values[5]	valids[0x0]	408	1			T23	1		T132	2		T216	3
auto[1]	values[5]	valids[0x1]	262	1			T55	3		T56	2		T95	5
auto[1]	values[6]	valids[0x0]	318	1			T18	3		T56	1		T95	2
auto[1]	values[6]	valids[0x1]	282	1			T23	1		T56	3		T95	3
auto[1]	values[7]	valids[0x0]	440	1			T23	3		T55	4		T95	2
auto[1]	values[7]	valids[0x1]	237	1			T23	1		T56	1		T95	3
auto[1]	values[8]	valids[0x0]	2683	1			T23	14		T50	1		T55	6
auto[1]	values[8]	valids[0x1]	1815	1			T18	1		T23	19		T55	2