Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3286671

1

T3

17580

T8

1

T13

39

auto[1]

30884

1

T15

13

T23

96

T57

7

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

922381

1

T3

17580

T8

1

T13

39

auto[1]

2395174

1

T15

1037

T23

4766

T57

263

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	615581	1			T3	7211		T8	1		T13	38
auto[524288:1048575]	367941	1			T3	5629		T19	10		T22	81
auto[1048576:1572863]	387046	1			T3	926		T22	145		T23	3
auto[1572864:2097151]	409801	1			T3	428		T18	72		T19	5
auto[2097152:2621439]	415320	1			T3	247		T19	285		T23	1589
auto[2621440:3145727]	368797	1			T3	1250		T19	94		T22	2
auto[3145728:3670015]	392212	1			T3	1889		T19	200		T22	56
auto[3670016:4194303]	360857	1			T13	1		T18	7		T23	1258

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2428012

1

T3

38

T8

1

T13

5

auto[1]

889543

1

T3

17542

T13

34

T15

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2834952

1

T3

17580

T8

1

T13

39

auto[1]

482603

1

T19

10

T22

134

T23

772

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	188926	1			T3	7211		T8	1		T13	38
auto[0]	auto[0]	auto[0:524287]	auto[1]	338230	1			T15	1026		T23	129		T57	258
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	88663	1			T3	5629		T19	1		T22	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	228270	1			T56	1		T95	3		T62	696
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	123938	1			T3	926		T22	145		T23	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	202694	1			T201	256		T95	512		T96	95
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	124346	1			T3	428		T18	72		T19	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	220064	1			T23	661		T55	1		T95	1024
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	113554	1			T3	247		T19	284		T23	10
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	231721	1			T23	1501		T122	518		T55	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	83664	1			T3	1250		T19	94		T22	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	222087	1			T23	512		T122	30		T56	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	89744	1			T3	1889		T19	200		T22	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	250716	1			T23	132		T56	865		T95	2421
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	98633	1			T13	1		T18	7		T23	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	204904	1			T23	974		T56	256		T95	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	1122	1			T77	20		T55	11		T301	13
auto[0]	auto[1]	auto[0:524287]	auto[1]	82932	1			T23	512		T55	256		T56	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	855	1			T19	9		T22	77		T108	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46064	1			T109	214		T91	1246		T210	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1032	1			T95	2		T109	13		T35	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56323	1			T35	257		T228	3873		T72	10
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	712	1			T22	2		T95	10		T108	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	60890	1			T95	129		T108	3039		T109	1538
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	688	1			T19	1		T56	3		T96	14
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	63608	1			T56	1543		T35	2		T65	3621
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	804	1			T96	6		T62	2		T109	15
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	59354	1			T62	262		T109	232		T70	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	985	1			T22	55		T23	1		T110	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47765	1			T108	513		T99	1		T69	2988
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	574	1			T23	3		T110	46		T55	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	52809	1			T23	256		T56	128		T95	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	606	1			T15	2		T57	2		T49	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3264	1			T15	11		T57	5		T49	51
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	359	1			T55	3		T56	1		T96	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3156	1			T56	1		T35	1		T210	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	340	1			T96	7		T109	16		T35	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1761	1			T35	5		T210	13		T99	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	402	1			T55	23		T96	19		T108	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2007	1			T55	163		T96	1		T108	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	416	1			T23	5		T55	9		T95	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	4697	1			T23	73		T96	4		T109	243
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	293	1			T96	9		T209	1		T208	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2117	1			T96	465		T209	1		T208	13
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	409	1			T55	2		T56	2		T96	17
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2099	1			T56	6		T228	128		T209	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	479	1			T23	2		T55	4		T95	22
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2393	1			T23	16		T96	3		T109	26
auto[1]	auto[1]	auto[0:524287]	auto[0]	104	1			T96	18		T109	5		T35	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	397	1			T35	7		T72	65		T166	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	119	1			T109	8		T210	1		T209	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	455	1			T109	9		T209	2		T72	132
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	122	1			T96	5		T35	1		T72	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	836	1			T96	128		T35	6		T72	19
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	118	1			T109	5		T210	1		T302	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1262	1			T210	3		T302	128		T99	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	103	1			T56	1		T96	9		T35	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	533	1			T56	4		T35	15		T65	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	80	1			T109	8		T70	1		T72	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	398	1			T109	24		T70	31		T53	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	104	1			T108	1		T109	2		T99	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	390	1			T108	2		T99	5		T72	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	87	1			T95	3		T96	12		T72	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	978	1			T95	94		T96	113		T72	241

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1923037	1			T3	38		T8	1		T13	5
auto[0]	auto[0]	auto[1]	887117	1			T3	17542		T13	34		T15	1
auto[0]	auto[1]	auto[0]	474779	1			T19	4		T22	31		T23	772
auto[0]	auto[1]	auto[1]	1738	1			T19	6		T22	103		T110	46
auto[1]	auto[0]	auto[0]	24239	1			T15	12		T23	94		T57	6
auto[1]	auto[0]	auto[1]	559	1			T15	1		T23	2		T57	1
auto[1]	auto[1]	auto[0]	5957	1			T56	5		T95	96		T96	279
auto[1]	auto[1]	auto[1]	129	1			T95	1		T96	6		T109	3