Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2965845	1			T1	1		T2	1		T3	1
all_pins[1]	2965845	1			T1	1		T2	1		T3	1
all_pins[2]	2965845	1			T1	1		T2	1		T3	1
all_pins[3]	2965845	1			T1	1		T2	1		T3	1
all_pins[4]	2965845	1			T1	1		T2	1		T3	1
all_pins[5]	2965845	1			T1	1		T2	1		T3	1
all_pins[6]	2965845	1			T1	1		T2	1		T3	1
all_pins[7]	2965845	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23687031	1			T1	8		T2	8		T3	8
values[0x1]	39729	1			T24	17		T34	48		T35	32
transitions[0x0=>0x1]	39065	1			T24	14		T34	34		T35	23
transitions[0x1=>0x0]	39076	1			T24	14		T34	34		T35	23

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2965293	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	552	1			T24	3		T34	7		T35	8
all_pins[0]	transitions[0x0=>0x1]	375	1			T24	3		T34	4		T35	7
all_pins[0]	transitions[0x1=>0x0]	267	1			T24	2		T34	3		T35	2
all_pins[1]	values[0x0]	2965401	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	444	1			T24	2		T34	6		T35	3
all_pins[1]	transitions[0x0=>0x1]	291	1			T24	1		T34	5		T35	3
all_pins[1]	transitions[0x1=>0x0]	226	1			T24	2		T34	5		T35	2
all_pins[2]	values[0x0]	2965466	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	379	1			T24	3		T34	6		T35	2
all_pins[2]	transitions[0x0=>0x1]	326	1			T24	3		T34	4		T35	1
all_pins[2]	transitions[0x1=>0x0]	135	1			T24	3		T34	3		T36	4
all_pins[3]	values[0x0]	2965657	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	188	1			T24	3		T34	5		T35	1
all_pins[3]	transitions[0x0=>0x1]	139	1			T24	3		T34	4		T35	1
all_pins[3]	transitions[0x1=>0x0]	164	1			T24	1		T34	6		T35	6
all_pins[4]	values[0x0]	2965632	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	213	1			T24	1		T34	7		T35	6
all_pins[4]	transitions[0x0=>0x1]	165	1			T24	1		T34	6		T35	5
all_pins[4]	transitions[0x1=>0x0]	559	1			T24	1		T34	6		T36	1
all_pins[5]	values[0x0]	2965238	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	607	1			T24	1		T34	7		T35	1
all_pins[5]	transitions[0x0=>0x1]	562	1			T24	1		T34	5		T36	2
all_pins[5]	transitions[0x1=>0x0]	37079	1			T34	3		T35	3		T36	4
all_pins[6]	values[0x0]	2928721	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	37124	1			T34	5		T35	4		T36	5
all_pins[6]	transitions[0x0=>0x1]	37061	1			T34	3		T35	4		T36	3
all_pins[6]	transitions[0x1=>0x0]	159	1			T24	4		T34	3		T35	7
all_pins[7]	values[0x0]	2965623	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	222	1			T24	4		T34	5		T35	7
all_pins[7]	transitions[0x0=>0x1]	146	1			T24	2		T34	3		T35	2
all_pins[7]	transitions[0x1=>0x0]	487	1			T24	1		T34	5		T35	3