Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18011

1

T3

12

T15

25

T16

4

auto[1]

12725

1

T17

2

T59

14

T60

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3393	1			T125	6		T78	8		T280	6
values[1]	3820	1			T3	12		T19	8		T57	21
values[2]	4063	1			T17	2		T202	4		T203	4
values[3]	4172	1			T61	20		T62	45		T63	20
values[4]	4145	1			T22	8		T110	4		T122	10
values[5]	4006	1			T15	25		T212	14		T303	6
values[6]	3469	1			T16	4		T20	6		T59	14
values[7]	3668	1			T101	14		T214	18		T49	73

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4351	1			T57	21		T59	14		T101	14
values[1]	3306	1			T22	8		T215	6		T98	20
values[2]	3968	1			T125	6		T64	10		T62	45
values[3]	4311	1			T15	25		T16	4		T19	8
values[4]	4028	1			T58	2		T205	18		T274	16
values[5]	3141	1			T213	16		T246	24		T267	6
values[6]	3843	1			T3	12		T122	10		T202	4
values[7]	3788	1			T17	2		T20	6		T61	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	167	1			T301	4		T74	15		T241	19
auto[0]	values[0]	values[1]	229	1			T240	80		T251	31		T245	42
auto[0]	values[0]	values[2]	499	1			T125	6		T69	14		T72	357
auto[0]	values[0]	values[3]	292	1			T78	8		T304	10		T75	11
auto[0]	values[0]	values[4]	120	1			T305	6		T266	5		T306	16
auto[0]	values[0]	values[5]	185	1			T268	11		T231	6		T273	13
auto[0]	values[0]	values[6]	176	1			T73	14		T276	12		T249	18
auto[0]	values[0]	values[7]	229	1			T280	6		T69	10		T307	20
auto[0]	values[1]	values[0]	206	1			T57	21		T102	14		T204	20
auto[0]	values[1]	values[1]	297	1			T308	10		T72	24		T52	40
auto[0]	values[1]	values[2]	392	1			T197	6		T70	12		T102	15
auto[0]	values[1]	values[3]	320	1			T19	8		T77	6		T79	16
auto[0]	values[1]	values[4]	370	1			T58	2		T70	9		T206	16
auto[0]	values[1]	values[5]	197	1			T213	16		T257	14		T69	6
auto[0]	values[1]	values[6]	297	1			T3	12		T207	18		T72	89
auto[0]	values[1]	values[7]	207	1			T309	2		T281	8		T310	8
auto[0]	values[2]	values[0]	384	1			T92	27		T72	75		T249	11
auto[0]	values[2]	values[1]	341	1			T311	4		T312	6		T273	14
auto[0]	values[2]	values[2]	322	1			T65	21		T72	8		T53	13
auto[0]	values[2]	values[3]	258	1			T206	25		T168	11		T313	4
auto[0]	values[2]	values[4]	486	1			T314	14		T75	72		T315	22
auto[0]	values[2]	values[5]	170	1			T246	24		T74	10		T285	11
auto[0]	values[2]	values[6]	322	1			T316	6		T240	12		T168	12
auto[0]	values[2]	values[7]	211	1			T286	13		T317	6		T318	16
auto[0]	values[3]	values[0]	400	1			T75	105		T319	14		T320	4
auto[0]	values[3]	values[1]	282	1			T282	12		T206	15		T53	11
auto[0]	values[3]	values[2]	186	1			T62	13		T321	6		T70	13
auto[0]	values[3]	values[3]	349	1			T322	6		T52	122		T323	8
auto[0]	values[3]	values[4]	303	1			T88	22		T52	14		T241	26
auto[0]	values[3]	values[5]	293	1			T267	6		T123	12		T73	12
auto[0]	values[3]	values[6]	200	1			T324	14		T52	72		T206	13
auto[0]	values[3]	values[7]	329	1			T63	20		T65	12		T69	14
auto[0]	values[4]	values[0]	305	1			T325	2		T102	8		T74	34
auto[0]	values[4]	values[1]	252	1			T22	8		T215	6		T98	10
auto[0]	values[4]	values[2]	282	1			T97	46		T268	12		T249	13
auto[0]	values[4]	values[3]	219	1			T110	4		T98	12		T326	8
auto[0]	values[4]	values[4]	189	1			T73	11		T53	12		T327	18
auto[0]	values[4]	values[5]	305	1			T297	4		T69	15		T264	20
auto[0]	values[4]	values[6]	455	1			T122	10		T268	118		T328	6
auto[0]	values[4]	values[7]	270	1			T201	14		T121	20		T70	11
auto[0]	values[5]	values[0]	231	1			T69	9		T249	20		T52	9
auto[0]	values[5]	values[1]	263	1			T67	4		T329	16		T330	52
auto[0]	values[5]	values[2]	395	1			T263	10		T331	13		T332	30
auto[0]	values[5]	values[3]	349	1			T15	25		T206	9		T333	12
auto[0]	values[5]	values[4]	355	1			T70	71		T124	68		T284	10
auto[0]	values[5]	values[5]	322	1			T303	6		T334	12		T335	114
auto[0]	values[5]	values[6]	187	1			T212	14		T89	10		T70	16
auto[0]	values[5]	values[7]	275	1			T75	11		T240	7		T262	15
auto[0]	values[6]	values[0]	310	1			T279	23		T249	8		T336	27
auto[0]	values[6]	values[1]	164	1			T194	2		T240	13		T241	21
auto[0]	values[6]	values[2]	179	1			T64	10		T337	10		T230	16
auto[0]	values[6]	values[3]	346	1			T16	4		T65	18		T69	11
auto[0]	values[6]	values[4]	199	1			T338	14		T339	4		T340	11
auto[0]	values[6]	values[5]	262	1			T70	48		T74	10		T53	11
auto[0]	values[6]	values[6]	346	1			T72	22		T73	13		T164	12
auto[0]	values[6]	values[7]	310	1			T20	6		T118	16		T72	17
auto[0]	values[7]	values[0]	365	1			T101	14		T75	8		T286	10
auto[0]	values[7]	values[1]	188	1			T229	10		T249	14		T206	16
auto[0]	values[7]	values[2]	155	1			T72	12		T279	16		T341	26
auto[0]	values[7]	values[3]	461	1			T49	73		T279	12		T240	57
auto[0]	values[7]	values[4]	336	1			T205	18		T342	6		T72	63
auto[0]	values[7]	values[5]	202	1			T343	4		T286	11		T236	8
auto[0]	values[7]	values[6]	275	1			T72	10		T75	20		T241	8
auto[0]	values[7]	values[7]	240	1			T214	18		T344	10		T249	6
auto[1]	values[0]	values[0]	109	1			T74	5		T241	5		T345	12
auto[1]	values[0]	values[1]	217	1			T240	12		T251	24		T245	24
auto[1]	values[0]	values[2]	167	1			T69	9		T72	3		T206	48
auto[1]	values[0]	values[3]	253	1			T75	78		T262	11		T299	2
auto[1]	values[0]	values[4]	251	1			T266	17		T346	19		T347	10
auto[1]	values[0]	values[5]	109	1			T268	9		T273	7		T348	4
auto[1]	values[0]	values[6]	207	1			T73	6		T235	12		T249	12
auto[1]	values[0]	values[7]	183	1			T69	25		T349	16		T293	11
auto[1]	values[1]	values[0]	222	1			T60	16		T102	6		T249	4
auto[1]	values[1]	values[1]	202	1			T72	16		T52	10		T251	8
auto[1]	values[1]	values[2]	269	1			T70	8		T102	5		T279	10
auto[1]	values[1]	values[3]	201	1			T65	7		T72	10		T52	10
auto[1]	values[1]	values[4]	247	1			T70	11		T206	4		T240	85
auto[1]	values[1]	values[5]	168	1			T69	14		T262	8		T241	14
auto[1]	values[1]	values[6]	138	1			T72	5		T240	11		T293	12
auto[1]	values[1]	values[7]	87	1			T350	8		T351	4		T352	2
auto[1]	values[2]	values[0]	384	1			T71	20		T72	11		T249	9
auto[1]	values[2]	values[1]	140	1			T273	6		T287	36		T353	4
auto[1]	values[2]	values[2]	257	1			T65	6		T72	94		T354	14
auto[1]	values[2]	values[3]	166	1			T203	4		T206	21		T168	9
auto[1]	values[2]	values[4]	157	1			T75	9		T186	9		T355	12
auto[1]	values[2]	values[5]	124	1			T74	10		T285	9		T245	7
auto[1]	values[2]	values[6]	258	1			T202	4		T356	2		T240	8
auto[1]	values[2]	values[7]	83	1			T17	2		T286	7		T357	8
auto[1]	values[3]	values[0]	278	1			T75	5		T266	9		T357	14
auto[1]	values[3]	values[1]	142	1			T206	5		T53	13		T240	6
auto[1]	values[3]	values[2]	213	1			T62	32		T70	81		T259	8
auto[1]	values[3]	values[3]	233	1			T52	23		T168	6		T251	51
auto[1]	values[3]	values[4]	375	1			T52	6		T241	16		T242	87
auto[1]	values[3]	values[5]	183	1			T73	8		T249	10		T168	11
auto[1]	values[3]	values[6]	135	1			T52	15		T206	14		T236	9
auto[1]	values[3]	values[7]	271	1			T61	20		T65	8		T68	10
auto[1]	values[4]	values[0]	359	1			T102	12		T74	8		T164	13
auto[1]	values[4]	values[1]	132	1			T98	10		T69	4		T249	8
auto[1]	values[4]	values[2]	263	1			T268	8		T249	36		T206	6
auto[1]	values[4]	values[3]	191	1			T98	8		T53	7		T273	9
auto[1]	values[4]	values[4]	145	1			T274	16		T73	21		T53	8
auto[1]	values[4]	values[5]	233	1			T66	20		T69	5		T268	12
auto[1]	values[4]	values[6]	176	1			T268	12		T236	3		T275	11
auto[1]	values[4]	values[7]	369	1			T201	6		T70	112		T53	7
auto[1]	values[5]	values[0]	227	1			T69	15		T249	20		T52	11
auto[1]	values[5]	values[1]	159	1			T329	6		T330	14		T358	9
auto[1]	values[5]	values[2]	181	1			T359	12		T263	10		T331	7
auto[1]	values[5]	values[3]	296	1			T206	11		T271	9		T241	6
auto[1]	values[5]	values[4]	198	1			T70	8		T124	7		T240	5
auto[1]	values[5]	values[5]	155	1			T353	6		T299	7		T360	14
auto[1]	values[5]	values[6]	127	1			T70	4		T273	9		T275	7
auto[1]	values[5]	values[7]	286	1			T75	9		T240	13		T262	5
auto[1]	values[6]	values[0]	220	1			T59	14		T279	10		T249	12
auto[1]	values[6]	values[1]	90	1			T240	7		T241	10		T266	7
auto[1]	values[6]	values[2]	110	1			T340	7		T329	12		T361	2
auto[1]	values[6]	values[3]	229	1			T65	8		T69	10		T362	6
auto[1]	values[6]	values[4]	106	1			T340	9		T236	8		T237	9
auto[1]	values[6]	values[5]	122	1			T70	4		T74	29		T53	9
auto[1]	values[6]	values[6]	219	1			T72	6		T73	19		T295	18
auto[1]	values[6]	values[7]	257	1			T72	4		T73	70		T236	9
auto[1]	values[7]	values[0]	184	1			T75	12		T286	10		T259	21
auto[1]	values[7]	values[1]	208	1			T249	71		T206	4		T53	7
auto[1]	values[7]	values[2]	98	1			T72	28		T279	22		T363	10
auto[1]	values[7]	values[3]	148	1			T279	8		T240	10		T168	7
auto[1]	values[7]	values[4]	191	1			T72	11		T75	8		T206	8
auto[1]	values[7]	values[5]	111	1			T286	9		T236	12		T299	15
auto[1]	values[7]	values[6]	325	1			T72	104		T75	10		T241	20
auto[1]	values[7]	values[7]	181	1			T249	43		T273	12		T353	7