Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	361	1			T267	4		T215	2		T88	2
auto[ReadAddrCrossIntoMailbox]	270	1			T62	1		T88	4		T65	2
auto[ReadAddrCrossOutOfMailbox]	322	1			T215	2		T88	8		T65	1
auto[ReadAddrCrossAllMailbox]	213	1			T267	2		T215	2		T88	8
auto[ReadAddrOutsideMailbox]	3486	1			T3	4		T15	2		T16	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296

1

T3

2

T15

1

T16

2

auto[1]

2356

1

T3

2

T15

1

T16

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	797	1			T57	2		T59	4		T101	4
read_ops[0x0b]	734	1			T15	2		T57	2		T101	2
read_ops[0x3b]	778	1			T3	2		T101	2		T60	2
read_ops[0x6b]	770	1			T3	2		T16	4		T59	4
read_ops[0xbb]	824	1			T79	6		T214	2		T212	2
read_ops[0xeb]	749	1			T57	2		T58	2		T202	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T267	2		T89	2		T343	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T267	2		T89	2		T343	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T73	1		T270	1		T299	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T73	1		T270	1		T168	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T88	1		T284	1		T75	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T88	1		T284	1		T72	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T267	1		T88	1		T284	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T267	1		T88	1		T284	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T57	1		T59	2		T101	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T57	1		T59	2		T101	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T72	2		T206	1		T240	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T72	3		T249	1		T262	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T65	1		T279	1		T249	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T124	1		T340	1		T242	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T215	1		T88	1		T284	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T215	1		T88	1		T65	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T215	1		T88	1		T72	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T215	1		T88	1		T75	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T15	1		T57	1		T101	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	285	1			T15	1		T57	1		T101	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T65	2		T73	1		T279	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T72	1		T74	1		T365	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T65	1		T73	1		T344	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T62	1		T69	1		T70	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T194	1		T240	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T194	1		T69	1		T72	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T88	1		T65	1		T344	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T88	1		T72	1		T344	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T3	1		T101	1		T60	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T3	1		T101	1		T60	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T70	1		T72	1		T334	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T73	1		T334	1		T164	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T88	1		T279	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T88	1		T70	3		T72	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T206	1		T323	3		T240	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T69	1		T323	3		T273	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T88	1		T72	1		T299	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T88	1		T69	1		T72	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T3	1		T16	2		T59	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T3	1		T16	2		T59	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T88	1		T343	1		T268	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T88	1		T65	1		T343	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T88	1		T73	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T88	1		T279	1		T249	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T88	2		T69	1		T366	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T88	2		T124	1		T72	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T70	1		T285	1		T262	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T69	1		T72	1		T74	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T79	3		T214	1		T212	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T79	3		T214	1		T212	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T215	1		T297	1		T197	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T215	1		T297	1		T197	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T72	1		T311	1		T286	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T72	1		T311	1		T262	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T72	1		T236	2		T259	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T168	3		T262	2		T273	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T72	1		T323	1		T275	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T65	1		T75	1		T323	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T57	1		T58	1		T202	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T57	1		T58	1		T202	1